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Prezentare tcs2011

Prezentare tcs2011






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    Prezentare tcs2011 Prezentare tcs2011 Presentation Transcript

    • JTAG and System on Chip Testing
      Alexandru IOVANOVICI
      January 2011
    • TDI (Test Data In)
      TDO (Test Data Out)
      TCK (Test Clock)
      TMS (Test Mode Select)
      TRST (Test Reset) optional.
      The protocol is serial
    • Communication model
      • one or more test access ports (TAPs);
      • More TAPS  scan chain;
      • JTAG adapter: at least level shifting, galvanic isolation
      • Host manipulates TMS and TDI and reads TDO
      • On top of this primitives are some higher level protocols for specific tests:
      • state switch;
      • Register shifting;
      • Free running;
      • Watchpoint/breakpoint
    • Boundary scan register
      • IO pins: limited observabillity of the internal state;
      • Additional shift-register for each signal pin: path around device’s boundary  bypass of the IO and more visibility of the signals;
      • Boundary Scan Description Language: similar to netlists in CAD/EDA;
    • Example: ARM11 Debug TAP
      • ARM1136 core: extensive JTAG capabilities;
      • Similar capabilities found also in FPGAs and ASICs;
      • ARM11 core found inside many SoC:
      • OMAP2420 (from TI) includes a boundary scan TAP, the ARM1136 Debug TAP, an ETB11 trace buffer tap, a C55x DSP, and a tap for an ARM7TDMI-based imaging engine, with the boundary scan TAP ("ICEpick-B") having the ability to splice TAPs into and out of the JTAG scan chain.
    • Example: ARM11 Debug TAP (cont’d)
      • Debugging in low power modes;
      • Scan chain modification (IEEE1149.4)
      • Halt mode debugging:
      • Single threaded approach: (!!!) RT-systems
      • Monitor mode debugging:
      • Hardware exception: debug monitor routine
      • Core-specific extensions
      • Ie. ARM Core Sight, Infineon Nexus;
      • Usually over JTAG layer;
    • Widespread uses
      Almost all devices with enough pincount;
      • ARM and almost all 32bit CPU/MCU in the world;
      • Atmel 16 bit: when there are enough pins to spare;
      • FPGA and CPLDs: for programming and debugging;
      • Many MIPS and PowerPCs;
      • PCI and PCIx connectors have pins;
      • Most of the boards have JTAG connectors (or just pads) to support testing during the manufacturing;
      • JTAG is used for field update of debugging;
      • Adapters in the range form 50 to 5000 USD (!!!)
      • PC parallel port bit-banging: cheap and slow 
      • Eight hours to reflash a WRT54GL;
    • JTAG Connectors
      No official standard for the physical connector;
      • Production boards usually omit headers;
      • Some manufacturer use more than the standardized four signals:
      • reset: tap RST and system RST;
      • Board voltage: level shifting;
      • GPIO lines;
      • USB/Ethernet: second chanel used for high speed tracing;
      • Bed-of-nails testing and programming for production boards;
    • JTAG for Software Dev.
      • Most IDEs have JTAG debug support; (Keil, CodeVision AVR, Quartus, Xilinx ISE, etc.);
      • Chip Vendors: provide tools and custom adapters;
      • Tool Vendors: adapters for a broad range of chips;
      • OpenSource: GCC+GDB OpenOCD
      • Best support for ARM
      • Support for:
      • Stopping/halting;
      • Single step/instruction;
      • Breakpoint;
      • Data structure browsing;
      • Commercial tools: simulators and trace analyzers;
    • SoC Design and Test Considerations
      • Martin Schrader, Roderick McConnell;
      • Infineon Technologies AG;
      • Design and Test Automation Conference 2003;
    • Chip floorplan
      • Siemens C163, 16bit microcontroller;
      • Harddrive controller, ASIC, 250 kGates, 54mW;
      • Large SRAM: 80kB program SRAM, 8kB data SRAM;
      • Buffer DRAM: 8MBit for HDD data transfer; 20ns delay;
      • Specific elements:
      • PLL 400MHz;
      • PVT cell: analog;
      • Regulator: analog
      • 0.18 μm
    • DfT and DfM decisions
      • Test economics
      • Small and “simple” chip simple and cheap testing;
      • Cheap testing == short testing:
      Few seconds per chip
      • Logic vs. memory testing:
      • Small and fast vs. large and slow;
      • DRAM have most of the area  most DfT measures;
    • Test implementation
      • The chip has many test features which are activated on demand;
      • A single JTAG connector is the access point for all the tests;
      • Scan ATPG Test
      • Inputs are diagonal on the chip to allow parallel testing;
      • BIST capabilities: outsourced;
      • 98% coverage of the logic: excluding unwanted modules;
    • Test implementation (2)
      • SRAM Tests
      • Large area of the SoC is covered by the SRAM;
      • MCU SRAM: coupled with the CPU;
      • HDC SRAM: HDD controller logic;
      • SRAM testing done with memory testers;
      • Test program stored in ROM and accessible for the tester;
      • Mode selection via JTAG.
    • Test implementation (3)
      • Modules of the HDC: not accessible to the MCU;
      • Require external testing:
      • Also JTAG mode selection
    • Test implementation (4)
      • ATE device can build a Bit Fail Map (BFM) after testing;
      • The BIST logic is tested with ATPG
      • Quiscustodiet ipso custodes ? 
      • Much longer than logic:
      • Paralell testing;
      • Using a dedicated memory tester;
      • Mode select via JTAG
    • Special features
      • Ring oscilattor:
      • 2ns, devide by 32;
      • Measured by ATE;
      • Dense layoiut vs. distributed layout;
      • Results indicate silicon speed;
      • track manufacturing process
      • Eliminate devices too fast or too slow;
    • Conclusions
      • SoC are one of the hottest topic in the are of high density integration and manufacturing;
      • Almost all mobile and embedded devices feature some SoC components:
      • Apple A4 is a SoC chip (ARM Cortex-A8 + PowerVR GPU);
      • Designer must know about testing:
      • Choosing most appropriate … and cost effective testing solution is a more and more difficult decision.
    • Testing SoC Interconnects using JTAG
      • Article:
      • Testing SoC Interconnects for Signal Integrity Using Boundary Scan;
      • Tehranipor M.H., Ahmed N., Nourani M.
      • 21st. VLSI Test Symposium 2003
    • Testing SoC Interconnects using JTAG
      • 50nm and below;
      • Short signal paths, high speed;
      • Multi core (NoC) and lots of modules;
       noise and delay;
      • Impossible to test everything at design
      • Proposed solution:
      • Treating wires as modules
      Adding boundary scan to wires (!!!)
    • Testing SoCInterconects using JTAG
      • Interconects:
      • Stuck-at;
      • Open;
      • Short;
      • One new JTAG instruction for reading test results;
      • Previous attempts:
      • Crosstalk testing;
      • Deterministic tests for interconects;
    • Testing SoC Interconnects using JTAG
      • Two methods of testing:
      • Conventional serial boundary scan;
      • Compress-send-test-read-decompress;
      Minimum compacted test seq.;
      • Contribution of the authors:
      • Extending JTAG to support interconnect testing;
      • Observation boundary scan cell (OBSC);
    • Testing SoC Interconnects using JTAG
      • Integrity loss:
      • multigigaHertz systems;
      • Voltage distortion and delay violation;
      • Causes:
      • Technological process variations;
      • Transmission line effects;
      • Coupling effects;
      • “Ground bounce”
    • Testing SoC Interconnects using JTAG
      • Integrity fault model:
      • Maximum aggressor: crosstalk analysis on long lines;
      • Which pattern triggers the maximum effect ???
    • Testing SoCInterconects using JATG
      • Integrity Loss Sensor Cell (ILS-C):
      • Amplifier-based (Op-Amp);
      • Detecting voltage variations and delay thresholds;
      • Quite expensive;
      • Technological – less expensive – solutions do exist;
      • … or: “on chip oscilloscope” (!!!)
    • Testing SoC Interconnects using JTAG
      Proposed ILS
      TCK: builds the sampling window for the acceptable delay testing;
    • Testing SoC Interconnects using JTAG
      Test Architecture
    • Testing SoC Interconnects using JTAG
      Experimental results
      • Implemented with Synopsys synthesizer;
      • ILS cell are twice expensive as the conventional ones;
      • Method III is faster but less accurate; Method II can be considered a tradeoff;
    • Testing SoC Interconnects using JTAG
      • Compression rates depending on the patterns;
      • Pattern generation algorithms are not the subject of this paper;
    • Testing SoC Interconnects using JTAG
      • Conclusions:
      • An extension to IEEE1149;
      • SoC interconnect signal integrity loss;
      • Importance of the signall integrity justifies the investment in HW;
      • Authors propose a simple sensor but the method can be adapted for other sensors too;
      • Further research is needed for efficient compression patterns;