JTAG and System on Chip Testing<br />Alexandru IOVANOVICI<br />January 2011<br />
TDI (Test Data In)<br />TDO (Test Data Out)<br />TCK (Test Clock)<br />TMS (Test Mode Select)<br />TRST (Test Reset) optio...
Communication model<br /><ul><li>one or more test access ports (TAPs);
More TAPS  scan chain;
JTAG adapter: at least level shifting, galvanic isolation
Host manipulates TMS and TDI and reads TDO
On top of this primitives are some higher level protocols for specific tests:
state switch;
Register shifting;
Free running;
Watchpoint/breakpoint</li></li></ul><li>Boundary scan register<br /><ul><li>IO pins: limited observabillity of the interna...
Additional shift-register for each signal pin: path around device’s boundary  bypass of the IO and more visibility of the...
Boundary Scan Description Language: similar to netlists in CAD/EDA;</li></li></ul><li>Example: ARM11 Debug TAP<br /><ul><l...
Similar capabilities found also in FPGAs and ASICs;
ARM11 core found inside many SoC:
OMAP2420 (from TI) includes a boundary scan TAP, the ARM1136 Debug TAP, an ETB11 trace buffer tap, a C55x DSP, and a tap f...
Scan chain modification (IEEE1149.4)
Halt mode debugging:
Single threaded approach: (!!!) RT-systems
Monitor mode debugging:
Hardware exception: debug monitor routine
Core-specific extensions
Ie. ARM Core Sight, Infineon Nexus;
Usually over JTAG layer; </li></li></ul><li>Widespread uses<br />Almost all devices with enough pincount;<br /><ul><li>ARM...
Atmel 16 bit: when there are enough pins to spare;
FPGA and CPLDs: for programming and debugging;
Many MIPS and PowerPCs;
PCI and PCIx connectors have pins;
Most of the boards have JTAG connectors (or just pads) to support testing during the manufacturing;
JTAG is used for field update of debugging;
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Prezentare tcs2011

  1. 1. JTAG and System on Chip Testing<br />Alexandru IOVANOVICI<br />January 2011<br />
  2. 2. TDI (Test Data In)<br />TDO (Test Data Out)<br />TCK (Test Clock)<br />TMS (Test Mode Select)<br />TRST (Test Reset) optional.<br />The protocol is serial<br />
  3. 3. Communication model<br /><ul><li>one or more test access ports (TAPs);
  4. 4. More TAPS  scan chain;
  5. 5. JTAG adapter: at least level shifting, galvanic isolation
  6. 6. Host manipulates TMS and TDI and reads TDO
  7. 7. On top of this primitives are some higher level protocols for specific tests:
  8. 8. state switch;
  9. 9. Register shifting;
  10. 10. Free running;
  11. 11. Watchpoint/breakpoint</li></li></ul><li>Boundary scan register<br /><ul><li>IO pins: limited observabillity of the internal state;
  12. 12. Additional shift-register for each signal pin: path around device’s boundary  bypass of the IO and more visibility of the signals;
  13. 13. Boundary Scan Description Language: similar to netlists in CAD/EDA;</li></li></ul><li>Example: ARM11 Debug TAP<br /><ul><li>ARM1136 core: extensive JTAG capabilities;
  14. 14. Similar capabilities found also in FPGAs and ASICs;
  15. 15. ARM11 core found inside many SoC:
  16. 16. OMAP2420 (from TI) includes a boundary scan TAP, the ARM1136 Debug TAP, an ETB11 trace buffer tap, a C55x DSP, and a tap for an ARM7TDMI-based imaging engine, with the boundary scan TAP ("ICEpick-B") having the ability to splice TAPs into and out of the JTAG scan chain.</li></li></ul><li>Example: ARM11 Debug TAP (cont’d)<br /><ul><li>Debugging in low power modes;
  17. 17. Scan chain modification (IEEE1149.4)
  18. 18. Halt mode debugging:
  19. 19. Single threaded approach: (!!!) RT-systems
  20. 20. Monitor mode debugging:
  21. 21. Hardware exception: debug monitor routine
  22. 22. Core-specific extensions
  23. 23. Ie. ARM Core Sight, Infineon Nexus;
  24. 24. Usually over JTAG layer; </li></li></ul><li>Widespread uses<br />Almost all devices with enough pincount;<br /><ul><li>ARM and almost all 32bit CPU/MCU in the world;
  25. 25. Atmel 16 bit: when there are enough pins to spare;
  26. 26. FPGA and CPLDs: for programming and debugging;
  27. 27. Many MIPS and PowerPCs;
  28. 28. PCI and PCIx connectors have pins;
  29. 29. Most of the boards have JTAG connectors (or just pads) to support testing during the manufacturing;
  30. 30. JTAG is used for field update of debugging;
  31. 31. Adapters in the range form 50 to 5000 USD (!!!)
  32. 32. PC parallel port bit-banging: cheap and slow 
  33. 33. Eight hours to reflash a WRT54GL;</li></li></ul><li>JTAG Connectors<br />No official standard for the physical connector;<br /><ul><li>Production boards usually omit headers;
  34. 34. Some manufacturer use more than the standardized four signals:
  35. 35. reset: tap RST and system RST;
  36. 36. Board voltage: level shifting;
  37. 37. GPIO lines;
  38. 38. USB/Ethernet: second chanel used for high speed tracing;
  39. 39. Bed-of-nails testing and programming for production boards;</li></li></ul><li>JTAG for Software Dev.<br /><ul><li>Most IDEs have JTAG debug support; (Keil, CodeVision AVR, Quartus, Xilinx ISE, etc.);
  40. 40. Chip Vendors: provide tools and custom adapters;
  41. 41. Tool Vendors: adapters for a broad range of chips;
  42. 42. OpenSource: GCC+GDB OpenOCD
  43. 43. Best support for ARM
  44. 44. Support for:
  45. 45. Stopping/halting;
  46. 46. Single step/instruction;
  47. 47. Breakpoint;
  48. 48. Data structure browsing;
  49. 49. Commercial tools: simulators and trace analyzers; </li></li></ul><li>SoC Design and Test Considerations<br /><ul><li> Martin Schrader, Roderick McConnell;
  50. 50. Infineon Technologies AG;
  51. 51. Design and Test Automation Conference 2003; </li></li></ul><li>Chip floorplan<br /><ul><li>Siemens C163, 16bit microcontroller;
  52. 52. Harddrive controller, ASIC, 250 kGates, 54mW;
  53. 53. Large SRAM: 80kB program SRAM, 8kB data SRAM;
  54. 54. Buffer DRAM: 8MBit for HDD data transfer; 20ns delay;
  55. 55. Specific elements:
  56. 56. PLL 400MHz;
  57. 57. PVT cell: analog;
  58. 58. Regulator: analog
  59. 59. 0.18 μm</li></li></ul><li>DfT and DfM decisions<br /><ul><li>Test economics
  60. 60. Small and “simple” chip simple and cheap testing;
  61. 61. Cheap testing == short testing:</li></ul>Few seconds per chip<br /><ul><li>Logic vs. memory testing:
  62. 62. Small and fast vs. large and slow;
  63. 63. DRAM have most of the area  most DfT measures;</li></li></ul><li>Test implementation<br /><ul><li> The chip has many test features which are activated on demand;
  64. 64. A single JTAG connector is the access point for all the tests;
  65. 65. Scan ATPG Test
  66. 66. Inputs are diagonal on the chip to allow parallel testing;
  67. 67. BIST capabilities: outsourced;
  68. 68. 98% coverage of the logic: excluding unwanted modules;</li></li></ul><li>Test implementation (2)<br /><ul><li>SRAM Tests
  69. 69. Large area of the SoC is covered by the SRAM;
  70. 70. MCU SRAM: coupled with the CPU;
  71. 71. HDC SRAM: HDD controller logic;
  72. 72. SRAM testing done with memory testers;
  73. 73. Test program stored in ROM and accessible for the tester;
  74. 74. Mode selection via JTAG.</li></li></ul><li>Test implementation (3)<br /><ul><li>Modules of the HDC: not accessible to the MCU;
  75. 75. Require external testing:
  76. 76. Also JTAG mode selection</li></li></ul><li>Test implementation (4)<br /><ul><li>ATE device can build a Bit Fail Map (BFM) after testing;
  77. 77. The BIST logic is tested with ATPG
  78. 78. Quiscustodiet ipso custodes ? 
  79. 79. Much longer than logic:
  80. 80. Paralell testing;
  81. 81. Using a dedicated memory tester;
  82. 82. Mode select via JTAG</li></li></ul><li>Special features<br /><ul><li>Ring oscilattor:
  83. 83. 2ns, devide by 32;
  84. 84. Measured by ATE;
  85. 85. Dense layoiut vs. distributed layout;
  86. 86. Results indicate silicon speed;
  87. 87. track manufacturing process
  88. 88. Eliminate devices too fast or too slow;</li></li></ul><li>Conclusions<br /><ul><li>SoC are one of the hottest topic in the are of high density integration and manufacturing;
  89. 89. Almost all mobile and embedded devices feature some SoC components:
  90. 90. Apple A4 is a SoC chip (ARM Cortex-A8 + PowerVR GPU);
  91. 91. Designer must know about testing:
  92. 92. Choosing most appropriate … and cost effective testing solution is a more and more difficult decision.</li></li></ul><li>Testing SoC Interconnects using JTAG<br /><ul><li>Article:
  93. 93. Testing SoC Interconnects for Signal Integrity Using Boundary Scan;
  94. 94. Tehranipor M.H., Ahmed N., Nourani M.
  95. 95. 21st. VLSI Test Symposium 2003</li></li></ul><li>Testing SoC Interconnects using JTAG<br /><ul><li>50nm and below;
  96. 96. Short signal paths, high speed;
  97. 97. Multi core (NoC) and lots of modules;</li></ul> noise and delay;<br /><ul><li>Impossible to test everything at design
  98. 98. Proposed solution:
  99. 99. Treating wires as modules</li></ul>Adding boundary scan to wires (!!!)<br />
  100. 100. Testing SoCInterconects using JTAG<br /><ul><li>Interconects:
  101. 101. Stuck-at;
  102. 102. Open;
  103. 103. Short;
  104. 104. One new JTAG instruction for reading test results;
  105. 105. Previous attempts:
  106. 106. Crosstalk testing;
  107. 107. Deterministic tests for interconects;</li></li></ul><li>Testing SoC Interconnects using JTAG<br /><ul><li>Two methods of testing:
  108. 108. Conventional serial boundary scan;
  109. 109. Compress-send-test-read-decompress;</li></ul>Minimum compacted test seq.;<br /><ul><li>Contribution of the authors:
  110. 110. Extending JTAG to support interconnect testing;
  111. 111. Observation boundary scan cell (OBSC);</li></li></ul><li>Testing SoC Interconnects using JTAG<br /><ul><li>Integrity loss:
  112. 112. multigigaHertz systems;
  113. 113. Voltage distortion and delay violation;
  114. 114. Causes:
  115. 115. Technological process variations;
  116. 116. Transmission line effects;
  117. 117. Coupling effects;
  118. 118. “Ground bounce”</li></li></ul><li>Testing SoC Interconnects using JTAG<br /><ul><li>Integrity fault model:
  119. 119. Maximum aggressor: crosstalk analysis on long lines;
  120. 120. Which pattern triggers the maximum effect ???</li></li></ul><li>Testing SoCInterconects using JATG<br /><ul><li>Integrity Loss Sensor Cell (ILS-C):
  121. 121. Amplifier-based (Op-Amp);
  122. 122. Detecting voltage variations and delay thresholds;
  123. 123. Quite expensive;
  124. 124. Technological – less expensive – solutions do exist;
  125. 125. … or: “on chip oscilloscope” (!!!)</li></li></ul><li>Testing SoC Interconnects using JTAG<br />Proposed ILS<br />TCK: builds the sampling window for the acceptable delay testing;<br />
  126. 126. Testing SoC Interconnects using JTAG<br />Test Architecture<br />
  127. 127. Testing SoC Interconnects using JTAG<br />Experimental results<br /><ul><li>Implemented with Synopsys synthesizer;
  128. 128. ILS cell are twice expensive as the conventional ones;
  129. 129. Method III is faster but less accurate; Method II can be considered a tradeoff;</li></li></ul><li>Testing SoC Interconnects using JTAG<br /><ul><li>Compression rates depending on the patterns;
  130. 130. Pattern generation algorithms are not the subject of this paper;</li></li></ul><li>Testing SoC Interconnects using JTAG<br /><ul><li>Conclusions:
  131. 131. An extension to IEEE1149;
  132. 132. SoC interconnect signal integrity loss;
  133. 133. Importance of the signall integrity justifies the investment in HW;
  134. 134. Authors propose a simple sensor but the method can be adapted for other sensors too;
  135. 135. Further research is needed for efficient compression patterns;</li>

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