Managing SMIs for optimal RTOS
performance with the Intel® Atom™
processor
Insyde Software

© 2013 Insyde Software

1
Insyde Software is a Proud Member of
the Intel® Intelligent Systems Alliance

© 2013 Insyde Software

2
Agenda
• Overview of SMIs
• SMIs and RTOS performance
• Managing SMIs
• Summary

© 2013 Insyde Software
Intel x86 processors and SMI
• What is an SMI?
• SMI is a special interrupt, known as a System Management Interrupt
• When...
Intel x86 processors and SMI
• What is the SMI environment?
• An SMI places the processor(s) into System Management Mode
(...
Intel x86 processors and SMI
• What is the SMI environment? (continued)
• SMI code is only visible to a processor in the S...
Intel x86 processors and SMI
• How do SMIs happen? 3 common methods:
1. Write to the 0B2h I/O port (Software initiated SMI...
Intel x86 processors and SMI
• Why are SMIs used? Common examples:
• CPU over-temperature fail-safe shutdown (thermal SMI)...
Intel x86 processors and SMI
• Intel® Atom™ handles SMIs very efficiently
• SMI code is fully cached
• SMI SMRR (SMI Range...
Intel x86 processors and SMI
• Real Time OS (RTOS) requirements
• RTOS guarantees an application request will be serviced ...
Intel x86 processors and SMI
• How do you manage SMI activity?
• Classify the SMIs to determine their purpose.
• SMIs can ...
Intel x86 processors and SMI
• Class 0

Critical

• This class of SMI must occur to protect system hardware from
damage, o...
Intel x86 processors and SMI
• Class 1

Instability

• This class of SMIs manage events that could cause system instabilit...
Intel x86 processors and SMI
• Class 2

Workarounds

• This class of SMIs provide support for deficient hardware or missin...
Intel x86 processors and SMI
• How can you disable the Class 1 and Class 2 SMIs?
• The SMI configuration registers will be...
Intel x86 processors and SMI: Summary
• Managing SMIs for optimal RTOS performance:
• Actions:
• Use an Intel Atom process...
Intel x86 processors and SMI: Summary
• Managing SMIs for optimal RTOS performance:
• Actions:
• Use an Intel Atom process...
Questions?
• If you would like to learn more about working with Insyde
Software for your next project, contact:
• Ed Brohm...
Thank You!

© 2013 Insyde Software

19
Insyde and Ready for the Next are registered trademarks of Insyde Software.
Intel and Intel Atom are trademarks or registe...
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BIOS Customizations for Optimized RTOS Performance

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Learn about BIOS customizations you can do to optimize RTOS performance on your next Intel Atom embedded platform. Presented by Insyde Software.

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BIOS Customizations for Optimized RTOS Performance

  1. 1. Managing SMIs for optimal RTOS performance with the Intel® Atom™ processor Insyde Software © 2013 Insyde Software 1
  2. 2. Insyde Software is a Proud Member of the Intel® Intelligent Systems Alliance © 2013 Insyde Software 2
  3. 3. Agenda • Overview of SMIs • SMIs and RTOS performance • Managing SMIs • Summary © 2013 Insyde Software
  4. 4. Intel x86 processors and SMI • What is an SMI? • SMI is a special interrupt, known as a System Management Interrupt • When an SMI happens the Intel x86 processor performs a complete context switch to a new execution thread • The new SMI execution thread contains code that performs special functions at the highest privilege levels • After completion of those special functions, the processor switches the context back to the original code. Application or OS Context Save SMI SMI Code Application or OS Context Restore © 2013 Insyde Software
  5. 5. Intel x86 processors and SMI • What is the SMI environment? • An SMI places the processor(s) into System Management Mode (SMM) • SMI has higher priority for the processor than any other interrupt • All processors and all cores are placed into SMM on any SMI • The processor performs a full Context Save automatically • The Resume instruction in SMM restores the saved Context Context Save SMI Code Context Restore © 2013 Insyde Software
  6. 6. Intel x86 processors and SMI • What is the SMI environment? (continued) • SMI code is only visible to a processor in the SMM state • SMI code can modify System Management RAM (SMRAM) • SMRAM is only visible to a processor in SMM state • BIOS firmware traditionally has responsibility to initialize SMI interrupt vectors to BIOS code, to initialize SMRAM, and to lock SMI configuration registers Context Save SMI Code Context Restore © 2013 Insyde Software
  7. 7. Intel x86 processors and SMI • How do SMIs happen? 3 common methods: 1. Write to the 0B2h I/O port (Software initiated SMI) 2. The hardware generates SMI on a certain state occurring such as timer expiration, read or write of a pre-defined IO port 3. Processor receives interrupt on SMI# pin Context Save SMI Code Context Restore © 2013 Insyde Software
  8. 8. Intel x86 processors and SMI • Why are SMIs used? Common examples: • CPU over-temperature fail-safe shutdown (thermal SMI) • Supplement ACPI functions that may need BIOS support • Hardware based RAS functions • Security functions that want exclusive control of system • Emulation of a legacy device when USB is not supported by RTOS • Hot-plug events not handled by RTOS Context Save SMI Code Context Restore © 2013 Insyde Software
  9. 9. Intel x86 processors and SMI • Intel® Atom™ handles SMIs very efficiently • SMI code is fully cached • SMI SMRR (SMI Range Registers) dedicated to the SMI cacheable region • Context switching is very fast since processor data is saved to cached SMRAM • Intel Atom E6xxx series processors have full control of SMI behavior • http://download.intel.com/embedded/processor/datasheet/324208.pdf • Review sections on SMI/SCI generation Context Save SMI Code Context Restore © 2013 Insyde Software
  10. 10. Intel x86 processors and SMI • Real Time OS (RTOS) requirements • RTOS guarantees an application request will be serviced within a fixed timeframe • Consistent, deterministic, and predictable response times, regardless of work load, are required for many time-sensitive applications • Competent RTOS schedulers are finely tuned and optimized for the hardware • RTOS response times are a critical feature in selecting the right RTOS • SMIs “steal” time from the RTOS • Can be as long as 7 milliseconds (2 SMIs) per second • RTOS may fail to service requests and be unable to “catch up” under heavy work loads Context Context SMI Code Save Restore 3.5 milliseconds (ms) © 2013 Insyde Software
  11. 11. Intel x86 processors and SMI • How do you manage SMI activity? • Classify the SMIs to determine their purpose. • SMIs can be broadly identified into 3 classes: Critical, Instability, and Workarounds 3 Classes for SMI: Critical Instability Workarounds © 2013 Insyde Software
  12. 12. Intel x86 processors and SMI • Class 0 Critical • This class of SMI must occur to protect system hardware from damage, or for unrecoverable catastrophic events. A processor in an over-temperature condition will cause a Class 0 SMI. • Usually one time event that has no effect on normal RTOS performance. • Recommendation: Ignore this class of SMIs since they will not happen during normal operations © 2013 Insyde Software
  13. 13. Intel x86 processors and SMI • Class 1 Instability • This class of SMIs manage events that could cause system instability if ignored. Examples include writes to PCI Reset registers, DMA requests to compromising addresses, security violations by defective applications and viruses. • A competent RTOS should be able to control system events that could cause instability or affect system integrity. • Recommendation: Use a competent RTOS and disable this class of SMIs for optimal performance © 2013 Insyde Software
  14. 14. Intel x86 processors and SMI • Class 2 Workarounds • This class of SMIs provide support for deficient hardware or missing legacy hardware. SMI will trap on IO to hardware and emulate desired values for OS driver and applications. Examples include emulating PS2 keyboard when USB keyboard is not supported by OS, or simulating correct hardware behavior when hardware is out of spec. • A competent RTOS should be able to directly manage hardware and support all necessary workarounds. • Recommendation: Use a competent RTOS and disable this class of SMIs under all circumstances. © 2013 Insyde Software
  15. 15. Intel x86 processors and SMI • How can you disable the Class 1 and Class 2 SMIs? • The SMI configuration registers will be locked before RTOS gains control, so it’s too late to disable these SMIs in RTOS • Modify the startup firmware to disable these SMIs before passing control to the RTOS, or • Request BIOS vendor to disable Class 1 and 2 SMIs • A simple change in a build switch will turn them off © 2013 Insyde Software
  16. 16. Intel x86 processors and SMI: Summary • Managing SMIs for optimal RTOS performance: • Actions: • Use an Intel Atom processor for optimal SMI performance • Select a competent RTOS that requires no or few SMIs • Configure BIOS to disable Class 1 and Class 2 SMIs • Enjoy the new level of predictable performance in your RTOS and platform © 2013 Insyde Software
  17. 17. Intel x86 processors and SMI: Summary • Managing SMIs for optimal RTOS performance: • Actions: • Use an Intel Atom processor for optimal SMI performance • Select a competent RTOS that requires no or few SMIs • Configure BIOS to disable Class 1 and Class 2 SMIs • Enjoy the new level of predictable performance in your RTOS and platform © 2013 Insyde Software
  18. 18. Questions? • If you would like to learn more about working with Insyde Software for your next project, contact: • Ed Brohm, Director of Sales ed.brohm@insydesw.com • For questions regarding this presentation, contact: • Trevor Western, VP of Engineering, Server & Embedded trevor.western@insydesw.com © 2013 Insyde Software
  19. 19. Thank You! © 2013 Insyde Software 19
  20. 20. Insyde and Ready for the Next are registered trademarks of Insyde Software. Intel and Intel Atom are trademarks or registered trademarks of Intel Corporation in the United States and other countries. © 2013 Insyde Software

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