9-Oct-13 1CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 2CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 3CMP ARCHITECTURE K.INIYA CSE DEPT
CMP ARCHITECTURE K.INIYA CSE DEPT
Core 0 Core 1 Core 2 Core 3
Local
Memory
Local
Memory
Local
Memory
Local
Memory
Shared M...
CMP ARCHITECTURE K.INIYA CSE DEPT
ALU
Bus interface
I/O
bridge
Main
Memory
Register file
USB
controller
Graphics
adapter
D...
ALU
Bus interface
Register file
System bus
CPU chip
The Single Core
9-Oct-13 6CMP ARCHITECTURE K.INIYA CSE DEPT
Bus interface
ALU
Register file
ALU
Register file
ALU
Register file
ALU
Register file
Core 1 Core 2 Core 3 Core 4
9-Oct-13...
9-Oct-13 8CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 9CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 10CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 11CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 12CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 13CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 14CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 15CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 16CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 17CMP ARCHITECTURE K.INIYA CSE DEPT
9-Oct-13 18CMP ARCHITECTURE K.INIYA CSE DEPT
CMP ARCHITECTURE K.INIYA CSE DEPT
31 33
44 24
22 32
42 11
43 14
21 42
ISSUE SLOTS
Time(ProcessorCycles)
1 3 42
9-Oct-13 19
CMP ARCHITECTURE K.INIYA CSE DEPT
1
22
2
4 4
2 2
ISSUE SLOTS
Time(ProcessorCycles)
1 3 42
1
1
1 1
1 1
22
2 3 3
3 3
3
3
4 4...
9-Oct-13 21CMP ARCHITECTURE K.INIYA CSE DEPT
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Cmp

  1. 1. 9-Oct-13 1CMP ARCHITECTURE K.INIYA CSE DEPT
  2. 2. 9-Oct-13 2CMP ARCHITECTURE K.INIYA CSE DEPT
  3. 3. 9-Oct-13 3CMP ARCHITECTURE K.INIYA CSE DEPT
  4. 4. CMP ARCHITECTURE K.INIYA CSE DEPT Core 0 Core 1 Core 2 Core 3 Local Memory Local Memory Local Memory Local Memory Shared Memory Disk Main Memory 9-Oct-13 4
  5. 5. CMP ARCHITECTURE K.INIYA CSE DEPT ALU Bus interface I/O bridge Main Memory Register file USB controller Graphics adapter Disk Controller Disk System bus Memory bus CPU chip Expansion slots for other devices such as network adapters Mouse Keyboard Monitor I/O Bus 9-Oct-13 5
  6. 6. ALU Bus interface Register file System bus CPU chip The Single Core 9-Oct-13 6CMP ARCHITECTURE K.INIYA CSE DEPT
  7. 7. Bus interface ALU Register file ALU Register file ALU Register file ALU Register file Core 1 Core 2 Core 3 Core 4 9-Oct-13 7CMP ARCHITECTURE K.INIYA CSE DEPT
  8. 8. 9-Oct-13 8CMP ARCHITECTURE K.INIYA CSE DEPT
  9. 9. 9-Oct-13 9CMP ARCHITECTURE K.INIYA CSE DEPT
  10. 10. 9-Oct-13 10CMP ARCHITECTURE K.INIYA CSE DEPT
  11. 11. 9-Oct-13 11CMP ARCHITECTURE K.INIYA CSE DEPT
  12. 12. 9-Oct-13 12CMP ARCHITECTURE K.INIYA CSE DEPT
  13. 13. 9-Oct-13 13CMP ARCHITECTURE K.INIYA CSE DEPT
  14. 14. 9-Oct-13 14CMP ARCHITECTURE K.INIYA CSE DEPT
  15. 15. 9-Oct-13 15CMP ARCHITECTURE K.INIYA CSE DEPT
  16. 16. 9-Oct-13 16CMP ARCHITECTURE K.INIYA CSE DEPT
  17. 17. 9-Oct-13 17CMP ARCHITECTURE K.INIYA CSE DEPT
  18. 18. 9-Oct-13 18CMP ARCHITECTURE K.INIYA CSE DEPT
  19. 19. CMP ARCHITECTURE K.INIYA CSE DEPT 31 33 44 24 22 32 42 11 43 14 21 42 ISSUE SLOTS Time(ProcessorCycles) 1 3 42 9-Oct-13 19
  20. 20. CMP ARCHITECTURE K.INIYA CSE DEPT 1 22 2 4 4 2 2 ISSUE SLOTS Time(ProcessorCycles) 1 3 42 1 1 1 1 1 1 22 2 3 3 3 3 3 3 4 4 4 4 4 9-Oct-13 20
  21. 21. 9-Oct-13 21CMP ARCHITECTURE K.INIYA CSE DEPT

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