Unit2 control unit
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Unit2 control unit

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Unit2 control unit Unit2 control unit Presentation Transcript

  • Computer organization
  • Organization of control units
  • Basic concepts
    • To execute a program, the will fetch the contents of memory location pointed to by the PC and they are loaded to IR
    • Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered
    • After loading instruction to IR, PC is incremented.
    • Carry out actions specified by instruction in IR
    • The above phases can be considered as fetch phase and execution phase
  • Basic concepts
    • An instruction can be executed by performing one or more of the following operations
      • Transfer a word of data from one processor register to another or to the ALU
      • Perform an arithmetic or a logic operation and store the result in a processor register
      • Fetch the contents of a given memory location and load them into a processor register
      • Store a word of data from a processor register into a given memory location
  • Basic concepts
    • The registers, the ALU and interconnecting bus are collectively referred to as the datapath
    • There are certain registers which are used by the processor for temporary storage during execution for some instructions
  • Basic concepts
    • Transferring data between registers
    • The input and output of the a register are connected to the bus through switches controlled by the signals R in and R out .
    • In order to transfer contents of R1 to R4,
      • Enable output of register R1 by setting R1 out to 1.This places contents of R1 on the processor bus
      • Enable the input of register R4 by setting R4 in to 1.This loads data from the processor bus into register R4
  • Basic concepts
    • Performing arithmetic instruction
    • E.g. add contents of register R1 to those of register R2 and store the result to R3
      • R1 out ,Y in
      • R2 out ,SelectY,Add,Z in
      • Z out ,R3 in
  • Performing arithmetic and logic operation Ri Y mux A B ALU z Processor bus select Constant 4
  • Basic concepts
    • Fetching a word from memory ; move (R1),R2
      • MAR  [ R1]
      • Start a read operation on the memory bus
      • Wait for MFC response from the memory
      • Load MDR from the memory bus
      • R2  [MDR ]
    • To accommodate the variability in response time, the processor waits until it receives an indication that the requested read operation is completed ,such a signal is the MFC signal
  • Basic concepts
    • R1 out , MAR in , Read
    • MDR inE , WMFC
    • MDR out , R2 in
  • Basic concepts
    • Storing a word in memory ;move R2,(R1)
      • The desired address is loaded into MAR
      • Data to be written is loaded into MDR
      • Write signal is initiated
      • R1 out , MAR in
      • R2 out , MDR in , Write
      • MDR outE , WMFC
  • Execution of a complete instruction
    • Various steps are involved in executing a complete instruction (e.g. Add (R3),R1
    • Fetch the instruction
    • Fetch the first operand
    • Perform the action
    • Load the result
  • Execution of a complete instruction
    • Add (R3),R1
    Z out ,R1 in , End 7 MDR out , Select Y , Add, Z in 6 R1 out , Y in , WMFC 5 R3 out , MAR in , Read 4 MDR out , IR in 3 Z out , PC in , Y in , WFMC 2 PC out , MAR in ,Read, Select 4, Add, Z in 1 Action Step
  • Execution of a complete instruction
    • In step 1 , the contents of PC are loaded to MAR and a read request is send. The select signal is set to select 4.
    • This value is added to operand at input B, which is the contents of the PC and the result is stored in Z.
    • The updated value is moved from register Z to PC during step 2, while waiting for the memory to respond
    • In step 3, the word fetched from the memory is loaded into IR
    • Step 1 to 3 is the instruction fetch phase
  • Execution of a complete instruction
    • The instruction decoding circuit interprets the contents of the IR at the beginning of step4
    • Step4 to 7 is the execution phase
    • The contents of register R3 are transferred to the MAR in step 4 and a memory read operation is initiated
  • Execution of a complete instruction
    • The contents of R1 are transferred to register Y in step 5,when read operation is completed, the memory operand is available in register MDR
    • The addition is performed in step 6
    • The result is stored in step 7
  • Execution of a complete instruction
    • The end signal causes a new instruction fetch cycle to begin by returning to step1
    • In step 2 , it is not necessary to transfer contents of PC to register Y
    • But if any branching occurs, the updated value of PC is required to calculate the branch target address
  • Execution of a complete instruction
    • Branch instructions
    • Branch instruction replaces the contents of the PC with target address
    • This address is usually obtained by adding an offset X, which is given in the branch instruction to the updated value of PC
    • If the branch instruction is at location 2000 ,if the branch target address is 2050 offset must be 46
    • If it is a conditional branch , the status must be checked before branching
  • Execution of a complete instruction
    • branching
    Z out ,PC in , End 5 Offset of IR out , Add, Z in 4 MDR out , IR in 3 Z out , PC in , Y in , WMFC 2 PC out , MAR in ,Read, Select 4, Add, Z in 1 Action Step
  • Control
    • Two main approaches used for implementing the control unit of a processor are
    • Hardwired control and
    • Micro programmed control
  • Hardwired control
    • Each step in a sequence of control signal is completed in one clock period
    • A counter may be used to keep track of the control steps
    • Each state or count of this counter corresponds to one control step
  • Hardwired control
    • Each state or count of this counter correspond to one control step
    • The required control signals are determined by
      • Contents of the control step counter
      • Contents of the Instruction register
      • Contents of the condition code flags
      • External input signals, such as MFC and interrupt requests
  • Hardwired control Control step counter Step counter External inputs Condition codes Encoder Instruction decoder IR clock End Run INS1 INS n T1
  • Hardwired control
    • The step decoder provides a separate signal line for each step or time slot, in the control sequence
    • The output of the instruction decoder consists of a separate line for each machine instruction
    • For any instruction loaded in IR, one of the output lines INS1 is set to 1and all other lines are set to 0
    • The input signals to the encoder block are combined to generate the individual control signals
  • Hardwired control
    • E.g. Z in = T1+T6.Add+T4.Br+………
    • The end signal starts a new instruction fetch cycle by resetting the control step counter to its starting values
    • When Run signal is set to 1 the counter is incremented at the end of every clock cycle
  • Hardwired control
    • The sequence of operations carried out by the wiring of the logic elements ,hence the name hardwired
    • A controller that uses this approach can operate at high speed
    • It has limited flexibility and complexity of the instruction set it can implement is limited
  • Micro programmed control
    • Here the control signals are generated using program similar to machine language programs
    • A control word is a word whose individual bits represent various control signals
    • Each of the control steps in the control sequence of an instruction defines a unique combination of 1’s and 0 s.
  • Micro programmed control
    • A sequence of CW s corresponding to the control sequence of a machine constitutes the micro routine or micro program for the instruction
    • The individual control words in the micro routine are referred to as microinstructions
  • Micro programmed control
    • The micro routines for all instructions in the instruction set of a computer are stored in a special memory called the control store
    • The control unit can generate the control signals for any instruction by sequentially reading the CW’s of the corresponding microroutine from the control store
  • Microprogrammed control 3. 1. PC out, MAR in, Read,Select,Add,Zin 2. 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 1. E nd WMFC R3 out R1 in R1 out Z out Z in Add select Y in IR in MDR out Read MAR in PC out PC in Micro instruction
  • Basic organization of a Micro programmed control unit Starting address generator IR μ PC Control store Clock CW
  • Micro programmed control
    • To read the control words sequentially from the control store, a micro program counter is used
    • Every time a new instruction is loaded into the IR, the output of the block labeled “starting address generator’ is loaded into the microPC
    • The microPC is then automatically incremented by the clock, causing successive microinstructions to be read from the control store
  • Micro programmed control
    • Sometimes the control unit has to check the external signals or condition codes
    • So branching may be necessary
    • In order to incorporate branching, the circuit is modified
  • Micro programmed control Starting address generator IR μ PC Control store Clock CW External inputs Condition codes
  • Micro programmed control
    • When a new instruction is loaded into the IR , the micro PC is loaded with the starting address of the micro routine for that instruction
    • When a branch micro instruction is encountered , and the branch condition is satisfied, the micro PC is loaded with the branch address
  • Micro programmed control
    • When an End microinstruction is encountered, the micro PC is loaded with the address of the first CW in the micro routine for the instruction fetch cycle
  • Micro programmed control – address sequencing –micro instruction sequencing
    • Incrementing of the control address register
    • Unconditional branch or conditional branch , depending on status bit conditions
    • A mapping process from the bits of the instruction to an address of the control memory
    • A facility for sub routine and return
  • Microinstructions with next address field
    • The increase in branch instruction may create problems if we are using incrementable μ PC
    • An alternative is to use an additional address field which indicate the address of next instruction to be fetched
    • So separate branch instruction is not necessary
    • So there is no need to use a counter for sequencing
  • Micro instruction sequencing organization μ AR Control store Next address OR gate μ IR Microinstruction decoder Decoding circuit IR Condition codes External inputs Control signals
  • Microinstructions with next address field
    • So μ PC is replaced with micro instruction address register μ AR
    • The next address bits are fed through the OR gates to the μ AR
    • Any modification required for the address can be done on the basis of data in the IR , external inputs and condition codes
    • The decoding circuits generate the starting address on the basis of the output code in IR