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India: A Fab-Less Wonder: Case of SMDP
 

India: A Fab-Less Wonder: Case of SMDP

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This paper was presented in the Forum for Knowledge Sharing annual meeting held at SIU, Pune on 30th November. Download the paper from http://ssrn.com/abstract=2155540

This paper was presented in the Forum for Knowledge Sharing annual meeting held at SIU, Pune on 30th November. Download the paper from http://ssrn.com/abstract=2155540

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    India: A Fab-Less Wonder: Case of SMDP India: A Fab-Less Wonder: Case of SMDP Presentation Transcript

    • INDIA: a fab-less wonder: case of SMDP A.S.Rao indiainvents@hotmail.com ( This paper is based on project `Impact of SMDP-II’ sponsored by Department of Information Technology (DIT) on CIIE-IIMA)
    • Techno-Nationalism on slippery ground• "Chinese President Hu Jintao had dinner at the White House with President Obama and first lady Michelle. They were going to exchange gifts from the two countries, but unfortunately everything in our country is now made in their country, so they couldnt do any exchanging." –Jay Leno• India to showcase Aakash tablet at United Nations on November 28th. The initiative would highlight the countrys innovation. Media reports the computer was a cheap Chinese import and not an Indian innovation as was claimed. 2
    • SEMICONDUCTOR CAPABILITIES- STATE OF NATIONS• The development and manufacturing of chips involve three primary activities in the value chain: design, fabrication, test and assembly.• Prior to 1980s, the semiconductor industry was vertically integrated. Semiconductor companies owned and operated their own silicon wafer fabrication facilities and developed their own process technology for manufacturing their chips. These companies also carried out the fabrication, assembly and testing of their chips. 3
    • Value Chain Design Fabrication Assembly Huge fixed investment (currently on the order Requires expensive of $2 billion) to build a equipment Skill intensive plant (called a fab) Plant holds a wide Lower overall costs of variety of expensive plant and equipment equipmentRequires expensive EDA (electronic design Plant has to meet automation) software, Low average skill extreme requirements requirements of cleanliness. 4
    • Emergence of independent Fabs• Investment in Fabs (1995-2006) in USD billions:• USA- 74• Japan- 66• Taiwan- 72 (Foundry production is the largest segment of Taiwan’s domestic industry; in 1999, foundry related business accounted for almost 60 percent of Taiwan’s total industrial revenue.)• China-26• India- nil 5
    • Fabless IC suppliers• Total Fabless: $62.50 billion (2010)• U.S. companies occupy eight of the top ten slots by sales volume. Qualcomm tops the list of Fabless suppliers.Indian score on:• Integrated Fabs: NIL• Independent Fab : Nil• Fabless IC production: NIL 6
    • Emergence of fabless semi- conductor design firms 7
    • Special Manpower Development Program in VLSI Design and Related Software ,Phase-II (SMDP-II) Establishing State-of-the- art VLSI Design Labs Generation of SMDP-II VLSI Manpower at Website & 7 various levels sites at RCs in the VLSI Design Area Major Elements of the Program Instruction Enhancement India Chip Program (IEP) Program for faculties of PIs Workshops with International Guest Faculties 8
    • Primary ObjectiveTo train special manpower in the area of VLSIDesign and related software at M.E./M.Techlevel (Type-II manpower). In addition to this,generation of Type-III manpower i.e.M.E./M.Tech in other areas of electronics etc.with at least two courses on VLSI design willalso be undertaken. 9
    • Secondary ObjectiveTo train Type-IV manpower i.e. B.E./B.Tech inelectronics etc. with graduate level courses onVLSI Design. However, the program will notonly be limited to generation of Type-II, III &IV manpower but would endeavour togenerate Ph.D in various aspects of VLSIdesign/microelectronics (Type-I manpower)manpower as well. The establishment of VLSIdesign laboratories at RCs would alsostrengthen their academic program. 10
    • Implementing Organizations• 7 Resource Centers : 5 IITs, IISc Bangalore, CEERI Pilani• 25 Participating Institutes : 16 NITs, 9 other institutions.• Total Outlay - Rs.49.98 Crores 11
    • Achievements• Establishing State–of-the art VLSI Design Laboratories at 32 institutes.• Generation of manpower in VLSI Design area at various levels :a total of 20,114 engineering graduates in Electronics/ Communication/ Computer Science/ Instrumentation etc had taken a graduate level course in VLSI design. At PG level, 4,395 students had taken at least two courses in various aspects of VLSI Design and CAD. An addition 2,701 PG students had their specialization at ME/MTech in VLSI design & CAD. Further PhDs were awarded to 255 researchers in various aspects of VLSI design & CAD. 12
    • Chip Layout views of integrated designs under India Chip Programme 13
    • India Design Centers• Top 18 of 20 Top US semiconductor firms established Design Centers in India.• List includes:• Intel, TI, Freescale, AMD, IBM, QUALCOMM, Broadcom, Analog Devices, SanDisk, National, Agilent, ATI, etc 14
    • Why India matters in Chip design• Skilled manpower: Credit goes to a large extent to SMDP initiative.• Preference to work with MNCs:• Fear of Chinese clones: 15
    • The future: System on ChipChallenges:• Getting our hands dirty in IP Trading• Move from R&L ( Research and learning) to R&D ( Research and Development) 16
    • Thanks 17