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All Digital Phase Lock Loop 03 12 09

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Fundamentals of All-Digital Phase Lock Loop Used in Digital Radio Processor

Fundamentals of All-Digital Phase Lock Loop Used in Digital Radio Processor

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  • 1. All-Digital Phase Lock Loop Imran Bashir “The Lab Guy” March 10 th , 2009
  • 2. Outline
    • All-Digital PLL (ADPLL)
    • Noise Modeling in ADPLL
    • How to tune the ADPLL for GSM?
    • Impairments
    • Calibration & Compensation
    • Built-In Self Test
    • Summary
  • 3. All-Digital PLL (ADPLL) References [1], [3] - Bogdan Staszewski, John Wallberg 1 3 4 2 ADPLL operates in phase domain.
  • 4. Digitally-Controlled Oscillator Core
    • Cross coupled NMOS pair
    • Three banks of capacitors: PB(MIM), AB(MOS), TB(MOS)
      • Coarse Tuning: PB, AB
      • Fine Tuning/Modulation: TB, TB operated by ΣΔ
    • Operates on current limiting scheme.
    OSCM OSCP
  • 5. Digitally-Controlled Oscillator Core The C-V curve of the MOS can have a large linear range which is function of the DCO swing.
  • 6. DCO: Design Considerations
    • Given:
    • f = 4 GHz, C = 1pF, δ C = 1.5 fF
    • Then: δ f = 3 MHz -> PB Step Size
    • If total number of PB capacitors = 128
    • Tuning Range (DCO)= 128 x 3 MHz = 384 MHz
    • Tuning Range (div-2)= 384 /2 = 192 MHz
    • Tuning Range (div-4)= 384 /4 = 96 MHz
    • Low Band: f min =824.2 MHz, f max =958.8 MHz, Δ f LB =134.6 MHz
    • High Band: f min =1710.2 MHz, f max =1989.8 MHz, Δ f HB =279.6 MHz
    -> Not enough for GSM } Need to have control on inductance to increase tuning range. TB is designed with enough capacitors to support FM in presence of DCO drift.
  • 7. DCO ΣΔ
    • MASH-3 structure
    • Order: 1 st (N=1), 2 nd (N=2)
    • Configurable clock, Div-1/2/4/8
    • Critical parameters: M, CLK, N, δ C
    N=1, WFrac = 0.5 Duty Cycle = 50% C eff = δ C/2
  • 8. DCO ΣΔ : Design Considerations Composite ΣΔ Noise ↑, N ↑ , M ↓ , TB size ↑, f CLK ↓ Critical parameters: M, CLK, N, δ C -> Δ f Due to resolution of digital input (M) Due to size of capacitor Δ f Reference [3] - Bogdan Staszewski, Chih-Ming Hung
  • 9. DCO ΣΔ : Design Considerations Effect of SD order (N) M = 10, Δ f = 30kHz, f CLK = 450MHz N = 1 N = 2 N ↑ , L SD,M Х , L SD, Δ f lower between 1-10M & higher @ 100MHz Composite response (solid black line) DOES NOT include natural DCO phase noise!
  • 10. DCO ΣΔ : Design Considerations Effect of Fractional Word Length (M) N = 2, Δ f = 30kHz, f CLK = 450MHz M = 2 M = 10 Composite response (solid black line) DOES NOT include natural DCO phase noise! M ↑ , L SD,M ↑ , L SD, Δ f X, Current consumption ↑
  • 11. DCO ΣΔ : Design Considerations Effect of Capacitor Size ( Δ f) M = 10, N = 2, f CLK = 450MHz Δ f = 10kHz Δ f = 30kHz Δ f ↑ , L SD,M ↑ , L SD, Δ f ↑ Composite response (solid black line) DOES NOT include natural DCO phase noise!
  • 12. DCO ΣΔ : Design Considerations Effect of ΣΔ Clock ( f CLK ) M = 10, N = 2, Δ f = 30kHz f CLK = 225MHz f CLK = 450MHz f CLK ↑ , L SD,M X , L SD, Δ f ↑ Composite response (solid black line) DOES NOT include natural DCO phase noise!
  • 13. DCO ΣΔ : Final Design M = 10, N = 2, Δ f = 30kHz, f CLK = 450MHz (Div-4) Simulation Measurement
    • Root cause of discrepancies -> ideal assumptions in model
    • Skew b/w SD output pins
    • SD capacitors not similar
    • Malfunction @ high speeds
    1.80GHz 900MHz 450MHz 225MHz
  • 14. Phase Detector CKR = Re-timed FREF CKV = DCO clock
  • 15. Phase Detector Integer Error Correction Reference [6] - Bogdan Staszewski Φ = 3 Φ = 0 Modulo-16 N = 10 Error Resolution of Integer Correction = ±0.5 · DCO Cycle
  • 16. Time-to-digital Converter (TDC)
    • Quantized phase detector with resolution of 20 ps
    • DCO clock passes through the inverter chain
    • Delayed outputs are sampled by FREF
  • 17. Time-to-digital Converter (TDC)
  • 18. Time-to-digital Converter (TDC)
  • 19. TDC: Important Concepts
    • ε = Φ E for –ve phase error
    • ε ≠ Φ E for +ve phase error
    • ε = 1 – TR/TV
      • TV is the number of inverters covering 1 full CKV cycle
      • TV has to be know -> Requires compensation
  • 20. TDC: Important Concepts Effect of DCO Frequency ADPLL Frequency ↓ # of Inverters ↑ Current consumption ↑
  • 21. TDC: Important Concepts Effect of Inverter Delay Δ t inv ↓ TDC Quantization Noise ↓ # of Inverters (L) ↑ Current consumption ↑
  • 22. Digital Phase Error Signal: PHE
    • The phase error signal PHE is the output of the loop’s phase detector
    • Computed and captured digitally
    • The processing (rms calculation) is software based.
    PHE serves as a ‘noise meter’ in DRP.
  • 23. Outline
    • All-Digital PLL (ADPLL)
    • Noise Modeling in ADPLL
    • How to tune the ADPLL for GSM?
    • Impairments
    • Calibration & Compensation
    • Built-In Self Test
    • Summary
  • 24. Noise Modeling in ADPLL References [1], [3] - Bogdan Staszewski, John Wallberg Loop parameters  1-4
  • 25. Noise Modeling in ADPLL
    • Only three noise sources
      • Frequency reference – low pass
      • TDC quantization – low pass
      • DCO oscillator – high pass
    References [1], [3] - Bogdan Staszewski, John Wallberg
  • 26. Noise Modeling in ADPLL
    • Type-II 6 th -order PLL
    • Settings:  = 2 -7 ,  = 2 -15 ,  = 2 -[3 3 3 4]
    • Provides 33 dB of attenuation at 400 kHz
    • Provides 40 dB/dec filtering of 1/f DCO noise
    FREF / TDC path DCO path References [1], [3] - Bogdan Staszewski, John Wallberg f BW ↑ corner moves f BW ↑ corner moves
  • 27. Noise Modeling in ADPLL Tip: When even debugging spur source, study the effect of loop bandwidth on spur level. FREF harmonic spur Blue Trace = Yellow Trace = DCO Supply spur Blue Trace = Yellow Trace = Wide Loop Narrow Loop Wide Loop Narrow Loop
  • 28. Outline
    • All-Digital PLL (ADPLL)
    • Noise Modeling in ADPLL
    • How to tune the ADPLL for GSM?
    • Impairments
    • Calibration & Compensation
    • Built-In Self Test
    • Summary
  • 29. Tuning the ADPLL
    • Scenario:
      • Part is in the lab. Customer is waiting on 1 st pass software in order to make a phone call. All TX blocks are functional but before running the first round of regression, the loop parameters α , ρ , and λ need to be finalized.
    • Given:
      • All system and design guys are busy making press releases and working on journal publications and upcoming conferences. So its all up to “The Lab Guy.”
  • 30. Tuning the ADPLL: Step 1
    • Define two most important parameters.
    • For GSM:
      • Phase Trajectory Error
      • Modulated spectrum @ 400kHz
  • 31. Tuning the ADPLL: Step 2
    • Validate the ADPLL model.
    ADPLL MATLAB Model Inverter Delay Δ t inv 1. FREF 2. TDC 3. DCO + Composite Simulated ADPLL spectrum Measure noise sources Simulated vs. Measured GMSK Filter Composite Simulated Modulated spectrum X 3 L FREF (dBc/Hz) f 3 L DCO (dBc/Hz) f 2
  • 32. Tuning the ADPLL: Step 2 -119dBc/Hz -119dBc/Hz PN @ 400kHz - 64-kHz 0-dB CL BW - 13.7dB Gain Margin 0.9 ° 1.1 ° PTE - -36dB CL gain @ 400kHz -67dB -67.5dB MODSPEC @ 400kHz - 44 ° Phase Margin Measured Simulated Parameter 0.1 ° -74 DCXO 1.1 ° -49.7 Composite 1.1 ° -50 DCO 0.3 ° -62 TDC RMS PE dB Noise Source
  • 33. Tuning the ADPLL: Step 3
    • Using the validated model, determine possible settings of α , ρ , and λ with a comparable phase margin but wide range of 0-dB close loop (CL) bandwidth
    PM is comparable between all settings.
  • 34. Loop Setting 1
    • α =6, ρ =14, λ =0x2344
    • 0-dB close loop BW = 120-kHz, PM=47°, GM=15dB, CL @ 400kHz=-17dB
    RMS PE is low since composite close in noise is low. ADPLL 400-kHz phase noise is dominated by the TDC and DCO @ 400kHz.
  • 35. Loop Setting 1
    • α =6, ρ =14, λ =0x2344
    • 0-dB close loop BW = 120-kHz, PM=47°, GM=15dB, CL @ 400kHz=-17dB
    ADPLL 400-kHz phase noise is dominated by the TDC and DCO @ 400kHz. Open Loop Close Loop Modulated Open Loop Close Loop Modulated
  • 36. Loop Setting 2
    • α =7, ρ =16, λ =0x3555
    • 0-dB close loop BW = 64-kHz, PM=44°, GM=14dB, CL @ 400kHz=-36dB
    RMS PE is moderate since composite close in noise is moderate. ADPLL 400-kHz phase noise is dominated by the DCO @ 400kHz.
  • 37. Loop Setting 2
    • α =7, ρ =16, λ =0x3555
    • 0-dB close loop BW = 64-kHz, PM=44°, GM=14dB, CL @ 400kHz=-36dB
    ADPLL 400-kHz phase noise is dominated by the DCO @ 400kHz. Open Loop Close Loop Modulated Open Loop Close Loop Modulated
  • 38. Loop Setting 3
    • α =8, ρ =17, λ =0x3335
    • 0-dB close loop BW = 32-kHz, PM=43°, GM=20dB, CL @ 400kHz=-42dB
    RMS PE is high since composite close in noise is high. ADPLL 400-kHz phase noise is dominated by the DCO @ 400kHz.
  • 39. Loop Setting 3
    • α =8, ρ =17, λ =0x3335
    • 0-dB close loop BW = 32-kHz, PM=43°, GM=20dB, CL @ 400kHz=-42dB
    ADPLL 400-kHz phase noise is dominated by the DCO @ 400kHz. Open Loop Close Loop Modulated Open Loop Close Loop Modulated
  • 40. Tuning the ADPLL: Step 4
    • Set the ADPLL bandwidth
      • Narrow enough such that 400-kHz offset is dominated by DCO exclusively.
      • Wide enough such that DCO noise does not start degrading PTE.
    This number is not close to -70dB due to presence of impairment DCO capacitor mismatch. Set the ADPLL bandwidth in this region. PM is comparable between all settings. 400kHz MODSPEC [dB] DCO Dominant Contributor DCO + TDC 0-dB Loop Bandwidth [kHz] RMS Phase Error [deg]
  • 41. Tuning the ADPLL: Step 5
    • Check loop stability: Apply step in FREF
    DFT features in ADPLL allows to look at ADPLL output OTW or digital phase error PHE.
  • 42. Outline
    • All-Digital PLL (ADPLL)
    • Noise Modeling in ADPLL
    • How to tune the ADPLL for GSM?
    • Impairments
    • Calibration & Compensation
    • Built-In Self Test
    • Summary
  • 43. DCO Capacitor Mismatch
    • Purpose:
      • Natural mismatches = variability within the unit-weighted varactors
      • As capacitors are turned on and off, distortion will be evident in the resultant frequency
    • Solution:
      • Dynamic element matching (DEM) employed to improve digital-to-frequency conversion linearity
    Progression of time (8 cycles shown ) 8x8 varactor encoding matrix:
  • 44. DCO Capacitor Mismatch Compensation
    • Each experiment consists of 1500 trials.
    • Each trial is a measurement over 200 bursts.
    Digital activity in DEM results in spurs.
  • 45. ΣΔ Noise on DCO
    • Spectral growth at offsets between 300kHz – 5MHz from the carrier -> Marginal or failing spectrum performance
    • The extent of degradation is a function of the phase of ΣΔ clock adjusted by flyback delay circuit.
  • 46. ΣΔ Noise on DCO
    • Periodic behavior of RMS phase error and 400kHz modulated spectrum with delay.
    • Solution
      • Flyback delay calibration and compensation -> Reference [7]
      • Reduce ΣΔ clock
  • 47. RF to FREF Interference
    • ADPLL’s F ref clock jittered when F TX = N  F ref ( “integer channel”): Transmitter often fails its phase-error spec (3  RMS)
      • Severity changes when ADPLL is relocked (‘state’ dependent)
      • Does not depend much on output power, but is impacted by the CKV divider and by the TX divider (resetting it affects the performance)
      • More than one aggressor involved (challenging debugging…)
    References [8] - Oren Eliezer
  • 48. DCO Pulling
    • Issue: GSM Peak PE > 10 ˚
    • Root Cause:
      • There is excessive drift in DCO before and during TX burst (payload).
      • Due to Narrow loop BW, the ADPLL is not able to track the DCO and therefore a maximum peak phase error is experienced at the beginning of the burst.
    OTW Over TX Burst DCO drift is experienced even before TX payload
  • 49. DCO Pulling: Solution α =7, ρ =16, λ =0x3555 Loop Bandwidth = 64-kHz Phase margin = 44 ˚ Gain margin = 13.7 dB α =5, ρ =14, λ =0x2334 Loop Bandwidth = 233-kHz Phase margin = 49 ˚ Gain margin = 11.1 dB Dynamic adjustment of ADPLL bandwidth between 64-kHz and 233-kHz.
  • 50. DCO Pulling: Measurement Results
  • 51. DCO Pulling: Measurement Results
    • Max RMS PE & Peak PE improvement
    Default Worst case DOE part @ 1880MHz Bandwidth Adjustment Worst case DOE part @ 1880MHz
  • 52. Outline
    • All-Digital PLL (ADPLL)
    • Noise Modeling in ADPLL
    • How to tune the ADPLL for GSM?
    • Impairments
    • Calibration & Compensation
    • Built-In Self Test
    • Summary
  • 53. Characteristics of Calibration & Compensation Processes
    • Calibration:
      • Sometimes performed in factory after assembly (when external measurements needed)
      • Certain calibrations are done at power-up (internal measurements)
      • Typically performed using on-chip digital logic and/or software
      • Primary purpose is to account for process variations
      • Sometimes done only once in a lifetime of the system
      • Results are stored in memory to be used for compensation
    • Compensation:
      • Performed before or while signal is transmitted or received
      • Performed using hardware and/or software
      • Primary focus is to account for environmental variations such as temperature changes etc.
      • Process is invoked for each packet transmitted/received or periodically
  • 54. DCO Gain Calibration & Compensation
    • Estimation of oscillator modulation gain ( K DCO ) is critical
      • RX: sets the loop bandwidth and affects noise performance
      • TX: sets transfer function of the direct frequency modulation path
      • Tolerated gain estimation error: several % (GSM, Bluetooth)
      • Calibration routine for K DCO runs before each packet
  • 55. DCO Gain Calibration & Compensation 40% Variation over Process & 15% Variation over Temperature
  • 56. DCO Gain Calibration & Compensation
  • 57. DCO Gain Calibration & Compensation Without calibration and compensation, the phase error of the transmitter will fail 3GPP GSM specification. GSM 3GPP limit (5 degrees) Measured Simulated Target specification (3 degrees)
  • 58. DCO Gain Calibration & Compensation Data Packet DCO Gain Estimation
  • 59. TDC Calibration & Compensation
    • Purpose:
      • TDC inverter delay varies over voltage, temperature, and process.
      • The large variations can degrade system performance.
      • Calibration must be accurate within ±2% to comply with GSM spec.
    9% Variation over Temperature 50% Variation over Process Weak Process Nominal Process Strong Process
    • Solution:
      • Internal digital measurements of inverter delay
  • 60. TDC Calibration & Compensation Error needs to be within ±2% to meet 3  RMS phase-error spec.
  • 61. Calibration of DCO Current Problem Statement
    • The oscillator noise performance varies over process and temperature.
    • These variations can be compensated by adjusting the bias setting.
    • Strong process -> ibias ↓
    • Temperature ↑ -> ibias ↑
    • Need a sensor for estimating DCO noise in order to calibrate bias setting
  • 62. Calibration of DCO Current Variation of DCO Phase Noise Operating beyond optimum bias setting effects the DCO reliability. 400kHz Offset
  • 63. Calibration of DCO Current Proposed Solution
    • Digital processing of ADPLL’s phase error signal
    • Noise of DCO is digitized
    • ADPLL operation in closed loop with narrow loop bandwidth.
  • 64. Calibration of DCO Current Validation of Proposed Solution Optimum DCO current using PHE based estimation PHE based estimation of DCO noise correlates with the measured DCO integrated noise.
  • 65. DCO Frequency Calibration & Compensation
    • Purpose:
      • Ensure that the ADPLL will lock reliably over all process corners and temperatures.
    • Solution:
      • Store capacitor code in memory and retrieve before locking to a channel.
    Variation in DCO center frequency over process can be as high as 2% at 1.8GHz operation.
  • 66. DCO Frequency Calibration & Compensation The allocated time for ADPLL lock may not be adequate given DCO center frequency variation.
  • 67. Outline
    • All-Digital PLL (ADPLL)
    • Noise Modeling in ADPLL
    • How to tune the ADPLL for GSM?
    • Impairments
    • Calibration & Compensation
    • Built-In Self Test
    • Summary
  • 68. Motivation
    • Cellular phone market volumes and competitiveness drive cost reduction
    • Test costs, as part of the production costs, must be minimized
      • Use very low cost testers (VLCT)
      • Test many devices in parallel: massive multi-site testing (MMST)
      • Implement built-in self-testing (BIST)
    • The system-on-chip (SoC) has resources available for BIST at massproduction (processor, memory, data converters…)
    • BIST allows for concurrency  reduction in test time
    • BIST can increase coverage “at probe” (before packaging)  increase in yield
    • DRP architecture allows for simple digital signal processing based BIST
  • 69. Noisy/Defective vs. Normal DCO PTE is determined based on PHE based estimation of DCO noise. References [5] - Oren Eliezer, Imran Bashir
  • 70. Block Diagram for Cap. Test DCO phase capacitor toggling time domain PHE waveform H(S) References [5] - Oren Eliezer, Imran Bashir
  • 71. Outline
    • All-Digital PLL (ADPLL)
    • Noise Modeling in ADPLL
    • How to tune the ADPLL for GSM?
    • Impairments
    • Calibration & Compensation
    • Built-In Self Test
    • Summary
  • 72. Summary From a Wireless SoC Perspective
    • Pro’s:
      • Configurability
      • Size
      • Design for Test (DFT)
      • Fast lock time 10 μ s-20 μ s
      • No over-head
    • Con’s:
      • High Risk:
        • DCO ΣΔ Dithering of capacitor
        • Quantization noise of PPA
      • Low Risk:
        • Spurious Emissions
        • Current consumption
    For EDGE/WCDMA
  • 73. References
    • Robert Bogdan Staszewski. IWSOC-2005 Tutorial #4 – Wireless SoC: Digital Radio Processor Alternative to Conventional RF
    • C. M. Hung, R. B. Staszewski, N. Barton, M. C. Lee, and D. Leipold,``A digitally controlled oscillator system for SAW-less transmitters in cellular handsets,'' IEEE Journal of Solid-State Circuits , vol. 41, no. 5, pp. 1160--1170, May 2006.
    • R. B. Staszewski, C. M. Hung, N. Barton, M. C. Lee, and D. Leipold,``A Digitally Controlled Oscillator in a 90nm Digital CMOS Process for Mobile Phones,'' IEEE Journal of Solid-State Circuits , vol. 40, no. 11, pp. 2203-2211, Nov. 2005.
    • R. B. Staszewski, J. L. Wallberg, S. Rezeq, C. M. Hung, O. E. Eliezer, S. K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M. C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “All-Digital PLL and Transmitter for Mobile Phones” , IEEE Journal of Solid-State Circuits , vol. 40, no. 12, December 2005.
    • O. Eliezer, I. Bashir, R. B. Staszewski, and P. T. Balsara, ``Built-in Self Testing of a DRP-Based GSM Transmitter'', Proc. of IEEE RFIC Symposium pp. 339-342, June 2007.
    • R. B. Staszewski, All Digital Frequency Synthesizers in Deep-Submicron CMOS, Wiley, NJ, 2006.
    • I. Bashir, ON-CHIP CALIBRATION AND COMPENSATION TECHNIQUES FOR WIRELESS SoCs, MS. Thesis, University of Texas at Dallas, 2008.
    • O. Eliezer, R. B. Staszewski, S. Bhatara, I. Bashir, and P. T. Balsara,`` Active Mitigation of Induced Phase Distortion in a GSM SoC,'' Proc. of IEEE RFIC Symposium, pp. 17-20, June 2008.
    • O. Eliezer, I. Bashir, “Digital Hardware and Software Based Mechanisms for Compensation and Calibration in Wireless SoCs,” Proc. of IEEE RFIC Symposium, “On-Chip Calibration, Compensation, and Filtering Techniques for Wireless SoCs,” Workshop, Session WSL-2, June 2008.