Y25124127

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Y25124127

  1. 1. D.Rahul Varma, A. Uday Kumar, B. Vijaya Bhaskar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.124-127 Reconfigurable Viterbi Decoder D.RAHUL VARMA, A.UDAY KUMAR, B. VIJAYA BHASKAR Department of ECE, St.Theresa College of Engg. and Tech., Andhra Pradesh, India Assistant Professor, Department of ECE, St. Theresa College of Engg. and Tech., Andhra Pradesh, India Associate Professor, Department of ECE, St. Theresa College of Engg. and Tech., Andhra Pradesh, IndiaABSTRACT Forward Error Correction (FEC) bit information symbol (each m-bit string) to beschemes are an essential component of wireless encoded is transformed into an n-bit symbol,communication systems. Convolutional codes are where m/n is the code rate (n ≥ m) andemployed to implement FEC but the complexity of  The transformation is a function of thecorresponding decoders increases exponentially last k information symbols, where k is theaccording to the constraint length. Present constraint length of the code.wireless standards such as Third generation (3G) Convolution codes are used extensively insystems, GSM, 802.11A, 802.16 utilize some numerous applications in order to achieve reliableconfiguration of convolutional coding. data transfer, Including, digital, video, radio, mobileConvolutional encoding with Viterbi decoding is a communication and satellite communication.powerful method for forward error correction. convolutional encoder is used to obtain convolutionThe Viterbi algorithm, which is the most codes .It take a single or multi-bit input and generateextensively employed decoding algorithm for a matrix of encoded outputs. In digital modulationconvolutional codes. The main aim of this project communications systems (such as wirelessis to design FPGA based viterbi algorithm which communication systems, etc.) noise and otherencrypts / decrypts the data . In this project the external factors can alter bit sequences. By addingencryption / decryption algorithm is designed and additional bits we make bit error checking moreprogrammed in to the FPGA. successful and allow for more accurate transfers. By transmitting a greater number of bits than the originalI. INTRODUCTION signal we introduce a certain redundancy that can be In telecommunication and information used to determine the original signal in the presencetheory, forward error correction (FEC) (also of an error.called channel coding]) is a system of error Several algorithms exist for decodingcontrol for data transmission, whereby the sender convolutional codes. For relatively small values of k,adds systematically generated redundant data to its the Viterbi algorithm is universally used .messages, also known as an error-correcting A Viterbi decoder uses the Viterbi algorithm forcode (ECC). The carefully designed redundancy decoding a bitstream that has been encodedallows the receiver to detect and correct a limited using forward error correction based onnumber of errors occurring anywhere in the message a convolutional code.There are other algorithms forwithout the need to ask the sender for additional data. decoding a convolutionally encoded stream (forFEC gives the receiver an ability to correct errors example, the Fano algorithm). The Viterbi algorithmwithout needing a reverse channel to request is the most resource-consuming, but it doesretransmission of data, but this advantage is at the the maximum likelihood decoding. .cost of a fixed higher forward channel bandwidth. Here we designed the two stage convolutionalFEC is therefore applied in situations where encoder and viterbi decoder and will implement inretransmissions are relatively costly, or impossible FPGA.such as when broadcasting to multiple receivers. The For our illustration we will assume a 4-bitprocess of adding this redundant information is and give as an input to the convolutional encoderknown as channel coding. Convolutional coding and rate-1/2 code (two output bits for every input bit).block coding are the two major forms of channel This will yield a 2x4 output matrix, with the extracoding. Convolutional codes operate on serial data, bits allowing for the correction. This 8 bit output isone or a few bits at a time. Block codes operate on given as the input to the viterbi decoder whichrelatively large (typically, up to a couple of hundred decodes the convolutional codes into original data.bytes) message blocks. There are a variety of usefulconvolutional and block codes, and a variety of II. REVIEW OF PREVIOUSalgorithms for decoding the received coded ARCHITECTURESinformation sequences to recover the original data. In wireless communication AWGNConvolutional codes are employed to implement (Additive White Gaussian Noise) properties of mostFEC. In telecommunication, a convolutional code is a of the communication media introduce noise in realtype of error-correcting code in which each m- data during transmission.Channel Coding is a 124 | P a g e
  2. 2. D.Rahul Varma, A. Uday Kumar, B. Vijaya Bhaskar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.124-127technique to introduce redundant code in real code toremove interference and error during transmission.Coded data in sender side thus increased by volumeand error effect becomes less compare with uncodeddata. Receiver end receives this data and decodes thedata using some techniques. Viterbi decoding is oneof the popular techniques to decode data effectively. Fig 5: Block Diagram of viterbi decoderViterbi algorithm (VA) is an optimum decoding BMU: Branch metric unit ACS:algorithm for the convolutional code. Convolutional Add , compare and select TBU: Traceencoding and Viterbi Decoding are widely used for back unit d in: Inputreliable data transmission. data d out: Output data There are different approaches ofimplementation for Convolutional Encoder andViterbi Decoder in the literatures. previously the IV.VITERBI ALGORITHMimplementation of Convolutional Encoder and The algorithm for Viterbi decoder can beViterbi Decoder in the DSP Platform. It is a flexible explained by using the example below. Let usplatform but slow in speed. Using μC Platform consider the input 11010001.implementation of Convolutional Encoder and Mininum value and minimum path calculationViterbi Decoder is also Slow. The input is taken in the form of four sets each,comprising of 2 bits starting from the MSB. The To overcome the performance issue of first two bits from the MSB are taken and are XOR-Convolutional Encoder and Viterbi Decoder, FPGA ed with the values predetermined for the encoder asbased implementation has been proposed. These STATE 0 and the values are obtained.Similarly theyImplementations have Fixed Constraint Length and are also EXOR-ed with the values of STATE 1 andCode Rate or with Partial Configuration Facility. the values are also noted down. Thus we obtain 2 setsComplexity of Viterbi decoding algorithm increases of 4 values each , for state 0 and state 1. Thein terms of convolutionally encoded trellis length. corresponding values are compared and the minimumIncreasing the trellis length causes the algorithm to of each of the 2 values is noted down for all the 4take more time to decode. This will cause values. Also corresponding position values aretransmission speed lower but make the transmission marked as 00,01,10,11 respectively. For themore reliable. Lowering the trellis length will minimum path calculation, the value correspondingincrease the transmission speed . A highly complex to that particular minimum path is taken and its stateViterbi Decoder someway loses its advantages, when value (state 0 or state 1) is assigned to the minimumit is adopted to decode sequences transmitted on a path in decimal notation. This is the function of thelow-noise channel. In this case, low minimum BMU.distance codes are more suitable for achieving a goodperformance, and a higher bit rate can be transmittedby lowering the coding rate.III. VITERBI DECODER Viterbi decoder is most commonly used toresolve convolution codes. This is essential for thepurpose of secure transmission of data and itscorresponding retrieval during reception. Viterbidecoders also have the property of compressing thenumber of bits of the data input to half. As a resultredundancy in the codes is also reduced. Henceviterbi decoding is more effective and efficient. TheViterbi decoder designed here is an 8:4 decoder. Thesame logic and concept can also be extended tofurther number of bits also. Viterbi decoders arebased on the basic algorithm which comprises ofminimum path and value calculation and retracing thepath. This minimum values calculation is determinedby EX-OR operation and then comparing .This canbe briefed by means of the block diagram . 125 | P a g e
  3. 3. D.Rahul Varma, A. Uday Kumar, B. Vijaya Bhaskar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.124-127 Once the 1st row is resolved, the second setof two bits starting from the MSB (01 in our case) isEXOR-ed as explained for the first set. Now thecorresponding states of the respective values(value 0or value 1) are obtained and their correspondingSTATE VALUES are noted down(in binary). Thesestate values denote the minimum distance positions ,obtained in the previous row resolution. Thecorresponding value of the minimum distance ischosen and is added to the EXOR-ed outputs of thepresent row(both in binary) for both value 0 andvalue 1. They are then compared and minimumdistance is once again obtained and correspondingpositions are assigned. This is the function of theACS unit. The path calculation is the same as the firstrow. The above procedure is repeated for rows 3and 4 also and their corresponding values areobtained.Path trace back procedure The final step is the trace back procedure,wherein the all the values are consolidated to obtainthe final output. If the position of minimum value is00 or 01, a 0 is obtained in the output. For any othervalues, a 1 is obtained at the output. In thiscalculation, the minimum value of the last row is Fig 9: Synthesis Report of viterbi decodertaken and based on its position a 1 or 0 is assigned as VI. CONCLUSIONone of the output bits. The corresponding path is In our project, a Viterbi algorithm based onnoted and converted to binary. The minimum value the strongly connected trellis decoding of binarycorresponding to that particular path ,is noted and convolutional codes has been implemented in FPGA.once again a position based output bit assignment is The use of error-correcting codes has proven to be anmade as explained previously, for the row 3. This is effective way to overcome data corruption in digitalrepeated for all the remaining rows . Thus,4 output communication channels. The adaptive Viterbibits are obtained. These bits are then concatenated decoders are modelled using Verilog, and postand a process of bit reversal is made .thus a 4 bit synthesized by Xilinx FPGA logic. We canoutput is derived from an 8 bits input that was given implement a higher performance Viterbi decoderto the viterbi decoder with such as pipelining or interleaving. So in theThe output for the 8 to 4 viterbi decoder is shown future, with Pipeline or interleave the ACS and thebelow. The encoded bit is given as input and the 4 trace-back and output decode block, we can make itbit original message bit is decoded and got as the better.output. REFERENCEV. RESULT [1]. Shannon, C. “A mathematical theory of Model simwaveform & Synthesis Report of Communication”, Bell Sys.Tech .J., vol. 27viterbi decoder: ,pp. 379-423 and 23-656, 1948 [2]. Hamming, R. “Error detecting and correcting codes”, Bell Sys.Tech .J., vol. 29 ,pp.147-160 , 1960. [3]. Golay, M. “Notes on digital coding”, Proc. IEEE, Vol. 37, p. 657 , 1949 . [4]. Azim, C., Monir, M. “Implementation of Viterbi Decoder for WCDMA System”, Proceedings of IEEE International Conference (NMIC 2005), pp. 1-3, 2005. [5]. Wong, Y., Jian, W., HuiChong, O., Kyun, C., Noordi, N. “Implementation of Convolutional Encoder and Viterbi DecoderFig 8: Modelsim waveform of viterbi decoder using VHDL”, Proceedings of IEEE 126 | P a g e
  4. 4. D.Rahul Varma, A. Uday Kumar, B. Vijaya Bhaskar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.124-127 International conference on Research and Development Malaysia, November 2009.[6]. Bissi, L., Placidi. P., Baruffa, G., Scorzoni, A. “A Multi- Standard Reconfigurable Viterbi Decoder using Embedded FPGA blocks”, Proceedings of the 9th EUROMICRO Conference on Digital System Design(DSD’06),pp. 146-153 , 2006.[7]. Shaker, S., Elramly. S., Shehata. K. “FPGA Implementation of a reconfigurable Viterbi Decoder for WiMax Receiver”, IEEE International conference on Microelectronics, pp. 246-267,2009. 127 | P a g e

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