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Santosh A, Shivashankar Tallada / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.2043-2050 Simulation Of High-Efficiency AC/DC Converter For Power Factor Correction Santosh A and Shivashankar TalladaAbstract This paper presents a novel input current Harmonics drawn by the off-line equipment, severalshaper based on a quasi-active power factor international regulations, such as the IEC 61000-3-2correction (PFC) scheme. The PFC cell is formed and its corresponding Japanese regulation, have beenby connecting the energy buffer (LB) and an proposed and just enforced.auxiliary winding (L3 ) coupled to the transformer To comply with the line harmonicsof the dc/dc cell, between the input rectifier and standards, a variety of passive and active PFCthe low-frequency filter capacitor used in techniques have been proposed. The passiveconventional power converter. Since the dc/dc cell techniques normally use a simple line-is operated at high frequency, the auxiliary frequency LC filter to both extend the currentwinding produces a high frequency pulsating conduction angle and reduce the THD of the inputsource such that the input current conduction current of the diode-capacitor rectifier. Due to itsangle is significantly lengthened and the input simplicity, the passive LC filter could be the high-current harmonics is reduced. The input inductor efficiency and low-cost PFC solution to meet the IECLB operates in discontinuous current mode such 61000-3-2 class D specifications in the low powerthat a lower total harmonic distortion of the input range. However, the passive LC filter has a majorcurrent can be achieved. It eliminates the use of drawback, which is its heavy and bulky low-active switch and control circuit for PFC, which frequency filter inductor.results in lower cost and higher efficiency.Operating principles, analysis, and experimentalresults of the proposed method are presented.Keywords---AC/DC converters, power factorcorrection (PFC), single stage, Flyback converter.I. INTRODUCTION Fig.1. Circuit diagram of the conventional diode- Most electronic equipment is supplied by capacitor rectifier50/60 Hz utility power, and more than 50% of poweris processed through some kind of power converters. To reduce the size and weight of the filterConventionally, most of the power conversion inductor, the active PFC techniques have beenequipment employs either diode rectifier or thyristor introduced. In an active PFC converter, the filterrectifier with a bulk capacitor to converter AC inductor “sees” the switching frequency, which isvoltage to DC voltage before processing it. Such normally in the 10 kHz to hundreds of kHz range.rectifiers produce input current with rich harmonic Therefore, the size and weight of the power convertercontent, which pollute the power system and the can be significantly reduced by using a high-utility lines. Power quality is becoming a major frequency inductor. The cost of the active PFCconcern for many electrical users. approach can also be lower than that of the passive To measure the quality of input power of filter approach if the conversion power increases. Theelectrical equipment, power factor is a widely used most popular implementation of active PFC is toterm. The power factor of an off-line equipment is insert a PFC power stage into the existing equipmentdefined as the product of two components: the to satisfy the regulation. This is referred as the two-displacement factor cosϕ, which is caused by the stage PFC approach. However, the converter cost andphase difference between the fundamental component complexity increases with the increased componentof the input current and the sinusoidal input voltage, count.and the distortion factor, which can be presented bythe total-harmonic-distortion (THD) of the inputcurrent. In fact, the greatest concern of the off-linerectifier’s impact on the power system is not thedisplacement between the voltage and current, but theinput current distortion and current harmonics, sincethey pollute the power system and causes interferenceamong off-line utilities. To limit the input current Fig.2.Functional block diagram of two stage 2043 | P a g e
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Santosh A, Shivashankar Tallada / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.2043-2050The two-stage scheme results in high power factor scheme is especially attractive in low cost and lowand fast response output voltage by using two power applications due to its simplified power stageindependent controllers and optimized power stages. and control circuit, major issues still exist, such asThe main drawbacks of this scheme are its relatively low efficiency and high as well as wide-rangehigher cost and larger size resulted from its intermediate dc bus voltage stress .complicated power stage topology and control To solve the input current harmonicscircuits, particularly in low power applications. In problem in a single-stage, the “dither-rectifier”order to reduce the cost, the single-stage approach, concept was introduced with the conceptual Singlewhich integrates the PFC stage with a dc/dc converter Stage PFC structure in Fig. 3, in which, a highinto one stage, is developed. These integrated single- frequency “dither source” is between the input booststage power factor correction (PFC) converters - inductor LB and the bulk energy-storage capacitor CB.usually use a boost converter to achieve PFC with As shown in Fig. 3, the dither source introduces high-discontinuous current mode (DCM) operation. frequency pulsating voltage on LB during line cycle;Usually, the DCM operation gives a lower total therefore, the rectifier diode can conduct current evenharmonic distortion (THD) of the input current while the instantaneous input line voltage is muchcompared to the continuous current mode (CCM). lower than the capacitor voltage VB. As a result, theHowever, the CCM operation yields slightly higher input current conduction angle is significantlyefficiency compared to the DCM operation. enlarged and the input current harmonics are reduced. However, the harmonic content can meet the regulatory standard by a small margin and also the “dither” concept does not specify the switch duty- cycle to be constant. In this, a new concept of quasi-active PFC is proposed to improve the efficiency of a single-stage converter by preventing the input current or voltageFig.3. General Circuit diagram of single stage stress due the PFC cell from being added to the activeconversion. switch. In this circuit, the dc/dc cell operates in DCM so that a series of discontinuous pulses is used to Generally, single-stage PFC converters meet shape the input inductor current and the PFC isthe regulatory requirements regarding the input achieved. As the circuit uses resonance of circuitcurrent harmonics, but they do not improve the power parameters to achieve PFC, the control of the powerfactor and reduce the THD as much as their factor will be very sensitive to the variation ofconventional two-stage counterpart. The power factor components values.could be as low as 0.8, however, they still meet theregulation. In addition, although the single-stageII. PROPOSED QUASI-ACTIVE PFC CIRCUITFig.4.Proposed single stage PFC circuit diagram current power load, such as flyback converter. The flyback transformer (T) has three windings N1,N2 , The proposed quasi-active PFC circuit is and N3 . The secondary winding N2 = 1 isanalyzed in this section. As shown in Fig. 4, the assumed. In the proposed PFC scheme, the dc/dccircuit comprised of a bridge rectifier, a boost converter section offers a driving power with high-inductor LB , a bulk capacitor Ca in series with the frequency pulsating source. The quasi active PFCauxiliary windings L3 , an intermediate dc-bus cell can be considered one power stage but withoutvoltage capacitor CB , and a discontinuous input an active switch. 2044 | P a g e
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Santosh A, Shivashankar Tallada / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.2043-2050To simplify the analysis, the following assumptions transformer is assumed ideal, based on Ampere’shave been made. law, it has1) All semiconductors components are ideal.According to this assumption, the primary switchand the rectifiers do not have parasitic capacitances Where i2 = 0 at this stage therefore,and represent ideal short and open circuits in theirON and OFF states, respectively.2) The power transformer does not have the (3)leakage inductances because of the ideal coupling. Thus3) All the capacitors are high enough so that thevoltage across them is considered constant.4) Finally, the input voltage of the converter is (4)considered constant during a switching cyclebecause the switching frequency is much higherthan the line frequency.A. Principles of Operation of the ProposedCircuit To facilitate the analysis of operation, Fig.5(a) and (b) shows the topological stages and thekey waveforms of the proposed circuit. It isassumed that both the input inductor LB and themagnetizing inductance of the flyback converteroperate in DCM. Therefore, currents iLB , im, and i2are zero at the beginning of each switching period.It is also assumed that the average capacitor voltageVCa is greater than the average rectified inputvoltage |vin |. To ensure proper operation of theconverter, the transformer’s turns ratio should be(N1/N3 ) ≥ 2 and the boost inductor LB < Lm. Insteady-state operation, the topology can be dividedinto four operating stages. Fig. 5. (a) Key switching waveforms of the1) Stage 1 (to − t1 ): When the switch (SW) is proposed PFC.turned on at t = to , diodes D1 and Do are OFF,therefore, the dc-bus voltage VCB is applied to themagnetizing inductor Lm, which causes themagnetizing current to linearly increases. Thiscurrent can be expressed as (1) And since diode D1 is OFF, the inputinductor LB is charged by input voltage, therefore,the inductor current iLB is linearly increased fromzero since it is assumed that the PFC cell operatesin DCM. This current can be expressed as(2) Where, Vin = Vm| sin θ| is the rectifiedinput voltage, (to − t1) = dTS is the ON-time of theswitch (SW), LB is the boost inductor and N1 , N3are the primary and auxiliary turns ratio,respectively. At this stage, iLB = −i3 and thecapacitor Ca is in the charging mode. On the otherhand, Do is reversed biased and there is no current Fig. 5. (b) Equivalent circuit operation stages of theflow through the secondary winding. Since the proposed PFC circuit during one switching period 2045 | P a g e
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Santosh A, Shivashankar Tallada / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.2043-2050 Therefore, from (4) it can be seen that the B. Steady-State Analysismagnetizing current im is supplied by the The voltage conversion ratio of thedischarging current from the dc bus capacitor CB proposed converter can be estimated from the volt-and the current i3 which is equal to input current iLB second balance on the inductors and the input–at this stage. The current through the main switch output power balance as explained in the following.(SW) is given by From the volt-second balance on LB (9)(5) Where d1 is the OFF-time of the switch (SW). Therefore, the current stress of the switch Therefore, d1 could be given bycan be reduced by selecting the turns ratio (N3/N1), which is designed to be less than 1 to ensureproper operation of the transformer. Compared to (10)the single-stage BIFRED converter, the switch From Fig. 4(a), the average current of the boostcurrent is given by inductor in a switching cycle is given by (6) Obviously, the proposed circuit has less (11) Substituting for iLB,peak given in (2) and usingswitch current stress, therefore, the conduction loss (10), the average input current is given byand switching losses are reduced, and the efficiencyis improved correspondingly. This stage ends whenthe switch is turned off at t = t1 .2) Stage 2 (t1 − t2 ): When the switch is turned OFFat t = t1 , output diode Do begins to be forward (12)biased. Therefore, the energy stored in thetransformer magnetizing inductor is delivered to Based on (12) for a given input voltage,the load through the secondary winding. Similarly, Fig. 6(a) shows the normalized input currentthe diode D1 is also forward biased and the voltage waveform in a half cycle for a change in the turnsacross LB now Vin − VCB. Therefore, the current ILB ratio N3/N1. It can be seen that to reduce the deadis linearly decreased to zero at t = t2 (DCM time and improve the power factor of the inputoperation), and the energy stored in LB is delivered current the turn’s ratio must be ≥0.5. Similarly, Fig.to the dc bus capacitor CB . Therefore 6(b) shows the normalized input current waveform for a change in dc bus capacitor voltage VCB. As it can be seen that the higher the VCB the better quality of the input current waveform (lower (7) THD). However, higher VCB means higher voltage The capacitor (Ca ) is also discharging its stress on the power switch (SW), which can reduceenergy to the dc bus capacitor CB and the current i3 the efficiency of the converter. Therefore, areverse its direction. Therefore, the capacitor tradeoff between THD and efficiency must becurrent is given by made. The energy absorbed by the circuit from the source during a half switching cycle is given by (8)3) Stage 3 (t2 − t3 ): At this stage, the input inductorcurrent iLB reaches zero and the capacitor Cacontinues to discharge its energy to the dc buscapacitor CB . Therefore, iD1 = iCB = i3 . At t = t3 ,the magnetizing inductor releases all its energy to Substitution for Iin in given (12) yieldsthe load and the currents im and i2 reach to zerolevel because a DCM operation is assumed.4) Stage 4 (t3 − t4 ): This stage starts when thecurrents im and i2 reach to zero. Diode D1 still (13)forward biased, therefore, the capacitor Ca still Wherereleasing its energy to the dc bus capacitor CB .This stage ends when the capacitor Ca is completelydischarged and current i3 reaches zero. At t = t5, theswitch is turned on again to repeat the switchingcycle. 2046 | P a g e
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Santosh A, Shivashankar Tallada / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.2043-2050Fig. 6. Normalized input current waveform in half cycle for a change in (a) turns ratio N3/N1 and (b) buscapacitor voltage VCBThe average output power for a DCM flybackconverter is given by (15) Equation (15) shows that the dc bus capacitor is (14) independent of load variation; VCB is determined by the input voltage and circuit parametersAssume 100% efficiency, Pin = Po , yields Lm/LB,N3/N1 . Note that, (15) is transcendental and can only be solved by numerical method using specific circuit parameters.III. SIMULATION RESULTS AND EXPERIMENTAL VERIFICATIONFig. 7. Simulation of proposed circuit 2047 | P a g e
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Santosh A, Shivashankar Tallada / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.2043-2050 In order to verify the proposed concept, a Fig. 9 shows the measured harmonic content of theprototype of the converter shown in Fig. 4 was input current compared to the Classes A and Dconstructed as fig 7 by using MATLAB Simulation regulation standards. Note that, in order to improveand experimentally tested. To ensure proper the visibility of the higher order harmonics, class Aoperation of the converter, the dc bus voltage limits are scaled down by a factor of 5 (class A(VCB) must be higher than the input voltage, such limits/5). The measured THD = 7% and the powerthat the diode D1 is OFF and the inductor LB stores factor is 0.997. Obviously, the input current isenergy when the switch (SW) is ON. Therefore, much closer to the sinusoidal waveform and itfrom (15) the inductor Lm must be higher than the meets the regulation standards. Fig. 10 shows theinput inductor LB. The DCM fly back converter was transient response of the converter for a stepdesigned and implemented for 50 V/80 W output, change of load between 50% and 100%. It may beVin,rms (100–240 V) universal line voltage, and seen that a fast dynamic response has beenoverall efficiency of 86% is assumed. The obtained.switching frequency is selected to be 100 kHz andthe maximum duty cycle of is 0.45. The majorcomponents of the circuit are follows: transformerturns ratio (N1 = 30,N2 = 10,N3 = 15) with coreETD34, Lm = 200 μH, LB = 80 μH, CB = 47 μF, Ca= 22 μF, Co = 470 μF, the switch SW (SPW22N60),the bridge rectifier and diodes D1,Do usingMUR1560. Fig. 8 shows the measured inputvoltage and filtered input current waveforms for a100 Vac input voltage at full load. As it may be seenfrom Figs. 6 (a),(b) and 8, that selecting the turnsratio N3/N1 and the dc bus voltage VCB can beoptimized in order to reduce the dead time andimprove the quality of the input current. Fig. 10. The transient response of the converter for a step change of load between 50% and 100%.Fig. 8. Measured input voltage and filtered inputcurrent at full load (THD = 8.2%). Fig. 11. Measured dc bus capacitor voltage andFig. 9.Measured harmonics content of the input efficiency versus load power for a range of inputcurrent. voltage. 2048 | P a g e
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Santosh A, Shivashankar Tallada / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.2043-2050Fig. 11 shows the measured dc bus voltage VCB and between conventional single-stage boost-flybackefficiency of the converter for range of load and converter and the proposed converter in terms ofinput voltage variation. It may be seen that the circuit construction and performance. It may becapacitor voltage can be maintained below 450 V seen, that the proposed converter presents a highby properly designing the turns ratio N3/N1 and the quality input current with THD <10% and highinductors ratio Lm/LB. efficiency. However, the proposed converter has Furthermore, the proposed converter can additional winding N3 in series with capacitor (Camaintains 90% efficiency or above at high load. ), but they are small in size since N3 operate at theFinally, Table I summarizes the comparison converter switching frequency.TABLE I :COMPARISON BETWEEN THE CONVENTIONAL BOOST + FLYBACK AND THE PROPOSED PFCCIRCUIT [2] R. Redle, L. Balogh, and N. O. Sokal, “AIV. CONCLUSIONS new family of single-stage isolated power factor correctors with fast regulation of the The proposed method shapes the input output voltage,” in Proc. IEEE PESCcurrent based on a quasi-active power factor 1994 Conf., pp. 1137–1144.correction (PFC) scheme. In this method, high [3] C. Qian and K. Smedley, “A topologypower factor and low harmonic content are survey of single-stage power factor with aachieved by providing an auxiliary PFC circuit boost type input-current-shaper,” IEEEwith a driving voltage which is derived from a third Trans. Power Electron., vol. 16, no. 3, pp.winding of the transformer of a cascaded dc/dc 360–368, May 2001.flyback converter. It eliminates the use of active [4] T.-F. Wu, T.-H. Yu, and Y.-C. Liu, “Answitch and control circuit for PFC. The auxiliary alternative approach to synthesizingwinding provides a controlled voltage-boost single-stage converters with power factorfunction for bulk capacitor without inducing a dead correction feature,” IEEE Trans. Ind.angle in the line current. The input inductor can Electron., vol. 46, no. 4, pp. 734–748,operates in DCM to achieve lower THD and high Aug. 1999.power factor. By properly designing the converter [5] L. Huber, J. Zhang, M. Jovanovic, andcomponents, a tradeoff between efficiency and F.C. Lee, “Generalized topologies ofharmonic content can be established to obtain single-stage input-current-shapingcompliance with the regulation and efficiency as circuits,” IEEE Trans. Power Electron.,high as possible vol. 16, no. 4, pp. 508–513, Jul. 2001. [6] H. Wei, I. Batarseh, G. Zhu, and K. Peter,REFERENCES “A single-switch AC-DC converter with [1] O. Gracia, J. A. Cobos, R. Prieto, and J. power factor correction,” IEEE Trans. Uceda, “Single-phase power factor Power Electron., vol. 15, no. 3, pp. 421– correction: A survey,” IEEE Trans. Power 430, May 2000. Electron., vol. 18, no. 3, pp. 749–755, [7] L. K. Chang and H. F. Liu, “A novel May 2003. forward AC/DC converter with input 2049 | P a g e
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Santosh A, Shivashankar Tallada / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.2043-2050 current shaping and fast output voltage BIOGRAPHY regulation via reset winding,” IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 125–131, Feb. 2005.[8] H. L. Do, “Single-stage single-switch power factor correction AC/DC Santosh A, II-M.Tech P.E, Department converter,” Inst. Electr. Eng. Proc. Electr. of EEE, SV Engineering College, Suryapet. Power Appl., vol. 152, no. 6, pp. 1578– 1584, Nov. 2005.[9] J. Qian, Q. Zhao, and F. C. Lee, “Single- stage single-switch power factor correction ac/dc converters with dc-bus voltage feedback for universal line Shivashankar Tallada, II-M.Tech P.E, applications,” IEEE Trans. Power Department of EEE, Annamacharya institute of Electron., vol. 13, no. 6, pp. 1079–1088, technology & sciences, Bata Singaram(V), Hayath Nov. 1998. Nagar(M)[10] S. Luo,W. Qiu,W.Wu, and I. Batarseh, “Flyboost power factor correction cell and a new family of single-stage AC/DC converters,” IEEE Trans. Power Electron., vol. 20, no. 1, pp. 24–33, Jan. 2005.[11] M. M. Jovanovic, D. M. Tsang, and F. C. Lee, “Reduction of voltage stress in integrated high-quality rectifiers- regulators by variablefrequency control,” in Proc. IEEE APEC 1994 Conf., pp. 569– 575.[12] J. Sebastian, A. Femandez, P. Villegas, M. Hemando, and J. Prieto, “New topologies of active input current shapers to allow AC-to-DC converterswith asymmetrically driven transformers to comply with the IEC-1000- 3-2,” IEEE Trans. Power Electron., vol. 17, no. 4, pp. 493–501, Jul. 2002.[13] N. Vazquez, J. Lopez, J. Arau, C. Hernandez, and Elias Rodriguez, “A different approach to implement an active input current shaper,” IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 132–138, Feb. 2005.[14] K. Zhou, J. G. Zhang, S. Yuvarajan, and D. F. Weng, “Quasiactive power factor correction circuit for switching power supply,” IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1410–1414, May 2008. 2050 | P a g e
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