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P. Ashok Kumar, B. Vijaya Bhaskhar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.1867-1870Design Of Adiabatic Logic Based Low Power Carry Select Adder P. ASHOK KUMAR, B. VIJAYA BHASKHAR Department of ECE, St. Theresa College of Engg. and Tech., Andhra Pradesh, India Associate Professor, Department of ECE, St. Theresa College of Engg. and Tech., Andhra Pradesh, IndiaABSTRACT Adders are of fundamental importance in In both Lynch-Swartzlander’s and Kantabutra’sa wide variety of digital systems. Many fast adders adders the sum bits are computed by means of carry-exist, but adding fast using low area and power is select blocks, which are able to perform theirstill challenging. This paper presents a new bit operations in parallel with the carry-tree.block structure that computes propagate signals This paper presents two new families ofcalled “carry strength” in a ripple fashion. Several adders, both based on a new bit carry Select &new adders based on the new carry select Adder adiabatic structure that computes propagate signalsstructure are proposed. Comparison with well- called “carry-strength” in a ripple fashion. The firstknown conventional adders demonstrates that the family of adders is a family of new carry-selectusage of carry-strength signals allows high-speed adders that are significantly faster than traditionaladders to be realised at significantly lower cost carry-select adders while not much larger. Theand consuming lower power than previously second family of adders is a family of hybrid look-possible. As well as in this paper we are ahead adders similar to those presented in [5, 6] butconcentrating on the heat dissipation & we are significantly smaller and still comparable in speed.reducing the current using adiabatic logic. II. EVALUATION METHODOLOGYKeywords – Adiabatic, Application Specific In our new type of carry-select adder, theIntegrated Circuit (ASIC), Area Efficient, CSLA, new block structure eliminates the delay due to theLow Power. rippling at the end of the life of a long-range carry signal. The main idea is that for each bit position k in a block Bj we compute whether the carry-in to position k comes from the carry-in to block Bj, orI. INTRODUCTION whether this carry is internally generated in block Bj. The importance of a fast, low-cost binary To this purpose we will use a new type of bit block,adder in a digital system is difficult to overestimate. in which we will compute propagate signals that startNot only are adders used in every arithmetic at the LSB of the block and end at every bit position.operation, they are also needed for computing the We find it helpful to call the complements of thesephysical address in virtually every memory fetch “carry-strength” signals, because they indicate foroperation in most modern CPUs. Adders are also each bit position whether the carry-in to that positionused in many other digital systems including originates within the same bit block.telecommunications systems in places where a full- In basic arithmetic computation, adder stillfledged CPU would be superfluous. Many styles of plays an important role though many people focus onadders exist. Ripple adders are the smallest but also more complex computation such as multiplier,the slowest. More recently, carry-skip adders [1, 2, 3] divider, cordic circuits. Although several algorithmsare gaining popularity due to their high speed and and architectures are implemented in literature, thererelatively small size. Normally, in an N-bit carry-skip is not a general architecture for measuringadder divided into a proper number of M-bit blocks performance equally. Much architecture is tested[1, 4], a long-range carry signal starts at a generic under different conditions which possibly result inblock Bi, rippling through some bits in that block, variant performance even implemented with the samethen skips some blocks, and ends in a block Bj. If the algorithm.carry does not end at the LSB of Bj then rippling CLA is proved to have good performanceoccurs in that block and an additional delay is needed using in high speed adder, so in many papers thisto compute the valid sum bits. Carry-look-ahead and architecture are used commonly. STCLA – Spanningcarry-select adders [1] are very fast but far larger and Tree Using CLA uses a tree of 4-bit Manchesterconsume much more power than ripple or carry-skip Carry-Look ahead chains (MCC) to generate carryadders. Two of the fastest known addition circuits are for different bit position. RCLCSA – Recursivethe Lynch-Swartzlander’s [5] and Kantabutra’s [6] CLA/CSA Adder uses the same conception ashybrid carry-look-ahead adders. They are based on STCLA except the lengths of its carry chains arethe usage of a carry tree that produces carries into variant, not fixed. HSAC – High Speed Adder Usingappropriate bit positions without back propagation. In CLA uses Ling’s adder which solves the transition oforder to obtain the valid sum bits as soon as possible, carry propagation delay. 1867 | P a g e
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P. Ashok Kumar, B. Vijaya Bhaskhar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.1867-1870 Adder using different implementation is the increasing with the clock frequency. The adiabaticmost critical issue. For example, STCLA and technique prevents such losses: the charge does notRCLCSA use dynamic CMOS while HSAC uses owe from the supply voltage to the load capacitancestatic CMOS. Here, we want to implement a general and then to ground, but it owes back to a trapezoidalarchitecture for measuring this three different or sinusoidal supply voltage and can be reused. Justalgorithm which means we can use both dynamic losses due to the resistance of the switches needed forCMOS and static CMOS to implement these the logic operation still occur. In order to keep thesealgorithms for equal comparison. At last, I will offer losses small, the clock frequency has to be muchmy new architecture improved from the original lower than the technological limit. In the literature, apaper. multitude of adiabatic logic families are proposed. Let me talk about the original Each different implementation shows some particularimplementation. It’s based on the Adiabatic adder. advantages, but there are also some basic drawbacksBut it takes advantage of the characteristics of CMOS for these circuits. The goal of this paper is to comparecircuit. Generally, we don’t use “bar” (inverted) as different adiabatic logic families and to investigatewe conduct every equation . But in reality, “bar” is their robustness against technological parameterautomated added at the output of logic circuits. So, variations. For this purpose three adiabatic logicthey use this special characteristic to reduce the carry families are evaluated and the impact of parameterpropagation time variations on the power dissipation is determined. Both intertie (and global) and intra-die (or local)III. POSITIVE FEEDBACK ADIABATIC LOGIC parameter variations of different components in the The structure of PFAL logic is shown in Fig. same sub-circuit are considered. The most important1. Two n-trees realize the logic functions. This logic factor is the threshold voltage variation, especiallyfamily also generates both positive and negative for sub-micrometer processes with reduced supplyoutputs. The two major differences with respect to voltage. This was also found for low voltage CMOSECRL are that the latch is made by two pMOSFETs circuits, cf., where the fundamental yield factor wasand two nMOSFETs, rather than by only two the gate delay variation (in CMOS the powerpMOSFETs as in ECRL, and that the functional dissipation is not significantly dependent on theblocks are in parallel with the transmission threshold voltage). For adiabatic circuits the timingpMOSFETs. Thus the equivalent resistance is smaller conditions are not critical, because the clockwhen the capacitance needs to be charged. The ratio frequency is particularly low, and therefore thebetween the energy needed in a cycle and the outputs can always follow the clocked supplydissipated one can be seen in Fig.3. During the voltage. Here the yield critical requirement is therecovery phase, the loaded capacitance gives back power dissipation that has a very low nominal value.energy to the power supply and the supplied energy Hence it exhibits large relative deviations due todecreases. parameter variations that can lead to the violation of the specifications. The general PFAL gate consists of a two cross coupled inverters and two functional blocks F and F’ (complement of F) driven by normal and complemented inputs which realizes both normal and complemented outputs. Both the functional blocks implemented with n channel MOS transistors. The equations used to implement PFAL adder and the corresponding sum and carry implementations. The logical organization of conventional and adiabatic adders is constructed by the replication of 2 and 4, 4bit blocks for %bit and 16-bit adder, respectively. Each 4bit block may be viewed asFig. 1 Basic Schematic of PFAL consisting of a carry unit, a sum generation unit, and a sum selection unit. (In practice, the three parts are of course not necessarily so distinctly separated.) TheIV. POWER DISSIPATION IN ADIABATIC carries and both types of sum bits are produced usingLOGIC GATES look-ahead functions as much as possible. The A limiting factor for the exponentially adiabatic adder results after the substitution of theincreasing integration of microelectronics is conventional CMOS adder’s blocks with therepresented by the power dissipation. Though CMOS corresponding adiabatic. Regarding the delay for antechnology provides circuits with very low static n-bit adiabatic carry select adder, which ispower dissipation, during the switching operation constructed by mbit blocks (m<n), we obtain:currents are generated, due to the discharge of loadcapacitances that cause a power dissipation tdelay = 2t+N(2tinv+t) 1868 | P a g e
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P. Ashok Kumar, B. Vijaya Bhaskhar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.1867-1870where 2t, is the delay from the computation of the Fig.3 PFAL Carry Blockpartial sum P, and Gi and, N(t+2tinv) with N=n/m,the delay of carry propagation through the m-bitblocks. The design of this adder involved rethinkingof the circuit according to the principle of theadiabatic switching and no changes were held in theabove equations. Also, to best of our knowledge asimilar adiabatic conditional sum adder hasn’t beenintroduced until now. Finally, following similarsubstitutions, for the conditional sum adder whosestructure resembles that of carry select adder, we canresult in another low power adiabatic adder. The schematic and simulated waveform ofthe carry select adder is shown. The energy stored atoutput can be retrieved by the reversing the currentsource direction during discharging process. Henceadiabatic switching technique offers the less energydissipation in PMOS network and reuses the storedenergy in the output load capacitance by reversingthe current source direction. Fig.4 Proposed Adiabatic CSAFig.2 PFAL Sum Block Fig.5 Proposed PFAL CSA Layout with area Fig.6 Proposed Circuit Power Results 1869 | P a g e
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P. Ashok Kumar, B. Vijaya Bhaskhar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.1867-1870V. Conclusion and block carry-look-ahead adders”, Proc. The new implementation is based on the of Int’l Symposium on Computeroriginal architecture, so it can be used in both static Arithmetic,1991, pp.154-164.CMOS and dynamic CMOS circuits. And through [4]. NAGENDRA, C., IRWIN, M.J., OWENS, R.M.:this architecture, we can reduce power and area “Area-time-power tradeoffs in parallelconsumption but sacrifice some timing (which can be adders”, IEEE Trans. CAS-II, 43, (10), pp.neglected). By this implementation, we prove that the 689-702.new architecture is really better than the traditional [5]. T. LYNCH, E.E. SWARTZLANDER, “AHSAC. After a brief review of the literature, we spanning-tree carry-look-ahead adder”,realize that improving adder is very difficult because IEEE Trans. on Comp., Vol. 41, n°8, Aug.of the transistor level. If we want to get higher 1992.performance we must reduce the complexity in [6]. KANTABUTRA, “A RECURSIVE CARRY-LOOKtransistor level. AHEAD/CARRY-SELECT HYBRID ADDER”, IEEE TRANS. ON COMP., VOL. 42, N°12, DEC.REFERENCES 1993. [1]. OREN, I.: “Computer arithmetic algorithms”, [7]. R. Zimmermann and H. Kaeslin, “Cell- Prentice-Hall, 1993 Based multilevel Carry-Increment Adders [2]. KANTABUTRA, V.: “Designing optimum with Minimal AT- and PT-Products, one-level carry-skip adders”, IEEE Trans. unpublished manuscript. on Comp., 1993, Vol. 42, n°6, pp.759-764. http://www.iis.ee.ethz.ch/~zimmi/ [3]. CHAN, P.K., SCHLAG, M.D.F., [8]. Tyagi, “ A reduced-area scheme for carry- THOMBORSON, C.D., OKLOBDZIJA, V.G.: select adders” IEEE Trans. on Comp., Vol. “Delay optimization of carry-skip adders 42, n°10, Oct. 1993. 1870 | P a g e
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