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Jv2416961699

  1. 1. Rashmi K Patil, M.A.Gaikwad, V.G.Nasre / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.1696-1699Area Efficient Wide Frequency Range CMOS Voltage Controlled Oscillator For PLL In 0.18μm CMOS Process 1 Rashmi K Patil, 2M.A.Gaikwad 3V.G.Nasre 1 Dept.of EXTC, B.D.C.E., Sevagram, Wardha, India 2 Professor & Dean(R &D), B.D.C.E., Sevagram, Wardha, India 3 P.G.Dept of Electronics, B.D.C.E., Sevagram, Wardha, IndiaABSTRACT Current starved VCO is simple ring their output frequency be a function of a control input,oscillator consisting of cascaded inverters. usually a voltage.Differential ring oscillator has a differential output There are two different types of voltageto reject common-mode noise, power supply noise controlled oscillators used in PLL, Current starvedand so on. In this paper we have designed and VCO and Differential VCO [1].In recent years LCsimulated Current Starved VCO and Differential tank oscillators have shown good phase-noiseVCO for PLL in Tanner 13.0v 0.18μm digital performance with low power consumption. However,CMOS process. Performance comparison is done there are some disadvantages. First, the tuning rangein terms of high oscillation frequency, low power of an LC-oscillator (around 10 - 20%) is relativelyconsumption, and low area. It is observed that low when compared to ring oscillators (>50%). So themaximum oscillation frequency about 2GHz is output frequency may fall out of the desired range inachieved in three stage differential VCO. But area the presence of process variation. Second, the phase-has been reduced to 688µm2 with low power noise performance of the oscillators highly dependsconsumption of 359.08µW with large tuning range on the quality factor of on-chip spiral inductors. Forin three stage current starved VCO for a most digital CMOS processes, it is difficult to obtain afrequency of 1.1GHz at 1.8 VDD. quality factor of the inductor larger than three.[2] Therefore, some extra processing steps may beKeywords: Current starved VCO, Three stage required. Finally, on-chip spiral inductors occupy a lot of chip area, typically around 200 ×200-300 ×300 m2,Differential VCO which is undesirable for cost and yield consideration [3].1 Introduction The ring oscillators, however, do not have A CMOS Voltage controlled oscillator the complication of the on-chip inductors required for(VCO) is a critical building block in PLL which the LC oscillators. Thus the chip area is reduced. Indecides the power consumed by the PLL and area addition to a wide tuning range; ring oscillators withoccupied by the PLL. VCO constitute a critical even number of delay cells can produce quadrature-component in many RF transceivers and are phase outputs [4]. The phase noise performance ofcommonly associated with signal processing tasks like ring oscillators is much poorer in general [4], [5].frequency selection and signal generation. RF Also, at high oscillation frequencies, the powertransceivers of today require programmable carrier consumption of the ring oscillators may not be lowfrequencies and rely on phase locked loops (PLL) to which is a key requirement for battery operatedaccomplish the same. These PLLs embed a less devices [6]. To overcome these problems, we workedaccurate RF oscillator in a feedback loop, whose on Three stage current starved Oscillator andfrequency can be controlled with a control signal. Differential voltage controlled oscillator without anTransceivers for wireless communication system LC tank. Finally their performances are comparedcontain low-noise amplifiers, power amplifiers, based on their simulation results.mixers, digital signal-processing chips, filters, andphase-locked loops. 2 Circuit Description Voltage controlled oscillators play a critical 2.1. Three stage Current Starved VCOrole in communication systems, providing periodicsignals required for timing in digital circuits andfrequency translation in radio frequency Circuits.Their output frequency is a function of a control inputusually a voltage. An ideal voltage-controlled voltage oscillatoris a circuit whose output frequency is a linear functionof its control voltage. Most application required thatoscillator be tunable, i.e. Fig 1 Designed current starved VCO 1696 | P a g e
  2. 2. Rashmi K Patil, M.A.Gaikwad, V.G.Nasre / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.1696-1699 2.2. Differential VCO Fig 3 Designed Differential VCO Fig 3 shows designed differential VCO consisting ofFig 2 Inverter schematic three delay cells. In the delay cells proposed in this work, we The operation of current starved VCO is provide the necessary bias condition for the circuit tosimilar to the ring oscillator. Fig1. Shows designed oscillate by means of using the positive partialthree stage Current-Starved VCO [7].Each delay cell feedback [10] Fig 4 shows the delay cell used inconsist of one PMOS and NMOS which operate as differential VCO.inverter, while upper PMOS and lower NMOSoperate as current sources. The current sources limitthe current available to the inverter. In other words,the inverter is starved for current. The current in thefirst NMOS and PMOS are mirrored in each invertercurrent source stage. PMOS and NMOS drain currentsare the same and are set by the input control voltage[8],[9].Fig 2 shows the inverter schematic.The total capacitance Ctot is given by, 𝟓∗𝐂𝐨𝐱(𝐖𝐩𝐋𝐩+𝐖𝐧𝐋𝐧) 𝐂𝐭𝐨𝐭 = (1) 𝟐where Cox is the oxide capacitance. The number of stages of the oscillator isselected; there are 3 stages. The centre drain current is Fig 4 Delay cell used in Differential VCO.calculated as:IDcentre = N ∗ VDD ∗ Ctot ∗ Fcen (2) To achieve maximum frequency the biaswhere N is the number of stages of inverter. scheme has been improved further. The bias schemeThe sizes of PMOS and NMOS of inverter stage are composed by transistors PMOS1 to PMOS6 anddetermined as: NMOS1 to NMOS5 provides a controlled bias current β Vgs −Vthn 2 and a controlled voltage Vc in such a way that theDcentre = (3) transistors of delay cell stay in saturation region for 2 Kp ∗WWhere, β = the entire control voltage range[11],[12]. LIt can be shown that the oscillation frequency is: Fig 5 shows the necessary bias scheme used in differential VCO.Fosc = 1/N ∗ Td (4) ID = (5) N∗Ctot ∗VDD where Td is the time delay.Above equation gives the centre frequency of theVCO whenID=IDcentre.The VCO stops oscillating, neglecting subthresholdcurrents,When, VinVCO<Vthn.Thus, Vmin=Vthn and Fmin=0The max VCO oscillation frequency Fmax isdetermined by finding ID when VinVCO=VDD Fig 5 Bias scheme used in Differential VCO. 1697 | P a g e
  3. 3. Rashmi K Patil, M.A.Gaikwad, V.G.Nasre / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.1696-16993 Simulation Result3.1Output waveforms Fig 8 Output waveforms of Differential VCO Fig 8.shows the output waveforms of differentialFig 6 Output waveforms of current starved VCO VCO. It is noted that at a constant control voltage of 0.26V the output frequency of current starved VCO isFig 6.shows the output waveforms of current starved 2GHz.Simulation results reported that the powerVCO. It is noted that at a constant control voltage of consumption is 0.91mW at 2GHz.1.15V the output frequency of current starved VCO is When the control voltage is varied from 0.26V to1.153GHz.Simulation results reported that the power 0.7V, the Oscillation frequency of the designedconsumption is 359.08µW at 1.1GHz differential VCO ranges from 2GHz to 60MHz.Due toWhen the control voltage is varied from 0.4V to PMOS based differential VCO, frequency decreases1.15V,the oscillation frequency of the designed with an increase in supply voltage. Table 2 gives thecurrent starved VCO ranges from 426.80 MHz- characteristics of the differential VCO between1.153GHz Table I. shows the characteristics of the control voltage (V) and frequency (GHz). Thecurrent starved VCO between control voltage (V) and relationship between frequency and control voltage isfrequency (MHz). The relationship between frequency predicted using curve hitting algorithm by polynomialand control voltage is shown in fig 7.The relationship y = -0.209x+2.120 (7)between frequency and control voltage is predicted with coefficient of correlation of ,R2=0.980using curve hitting algorithm by polynomial y=62.10x+594.1 (6) Table 2 Control Voltage (V) Vs Frequency (GHz)with coefficient of correlation of ,R2=0.864 of Differential VCOTable 1 Control Voltage (V) Vs Frequency (MHz) Voltage(V) Frequency(GHz)of Current Starved VCO 0.26 2 Voltage(V) Frequency(MHz) 0.3 1.78 0.35 1.51 0.4 426.80 0.4 1.21 0.55 805.15 0.45 0.92 0.65 813.00 0.5 0.79 0.75 861.32 0.55 0.59 0.85 893.65 0.6 0.49 0.95 908.26 0.65 0.36 1.05 977.51 0.7 0.06 1.15 1153.40 2.5 Frequency (GHz) 2 Frequency(GHz) 1400 1200 1.5 1000 Frequency(MHz) 1 y = -0.209x + 2.120 800 600 R² = 0.980 0.5 400 y = 62.10x + 594.1 0 200 R² = 0.864 0 0.26 0.35 0.45 0.55 0.65 0.45 0.55 0.65 0.75 0.85 0.95 1.05 1.15 Control Voltage (V) Control Voltage(V) Fig 9 Control Voltage (V) Vs Frequency (GHz)Fig 7 Control Voltage (V) VS Frequency (MHz) 1698 | P a g e
  4. 4. Rashmi K Patil, M.A.Gaikwad, V.G.Nasre / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue4, July-August 2012, pp.1696-16993.2. Performance comparison Differential Ring VCO” Ninth International The results of current starved VCO and Conference on Electronic Measurement &Differential VCO are compared in table 3. Instruments ICEMI’2009 [4] William Shing, Tak Yan, and Howard Cam From comparison table it has been observed Luong, ―A 900-MHz CMOS low-phase-that as the number of delay cells and number of noise voltage-controlled ring oscillator,transistor in delay cell are less in current starved VCO IEEE Transactions on Circuits and Systemarea and power consumption has been reduced in II:Analog and Digital Signal Processing,,current starved VCO than differential VCO.But vol. 48, pp. 216-221, Feb. 2001.maximum oscillation frequency about 2GHz has been [5] T. H. Lee and A. Hajimiri and, ―Oscillatorachieved in differential VCO due to improved bias Phase noise: A tutorial, IEEE J. Solid-Statescheme. Circuits, vol. 35, pp. 326–336,March 2000. [6] T. C. Weigandt, B. Kim, and P. R. Gray,Table 3 Comparison Table ―Analysis of timing jitters in cmos ringParameters Diff VCO Three Stage oscillators, In Proc. ISCAS, pp. 27-30, June Current Starved 1994. VCO [7] Haripriya Janardhan, Mahmoud FawzyTool Tanner 13.0v Tanner 13.0v Wagdy,” Design of a 1GHz Digital PLLTechnology 0.18µm 0.18µm Using 0.18μm CMOS Technology” ThirdSupply 1V 1.8V International Conference on InformationVoltage Technology: New Generations (ITNG06),2006 IEEEI/P Tuning 0.26-0.7V 0.45 -1.15 V [8] R. Jacob Baker, Harry W. Li & David E.Range Boyce, CMOS Circuit Design Layout, andRange of 60MHz- 426.80 MHz- Simulation, IEEE Press, 2002Oscillation 2GHz 1.153GHz [9] D. P. Bautista and M.L. Aranda, “A lowFrequency 2 2 power and high speed CMOS Voltage-Area 1648µm 688µm Controlled Ring Oscillator”, Circuits andPower 0.91mW 359.08µW Systems, 2004. ISCAS 04. Proceedings ofConsumption the 2004 International Symposium onGate Length 0.18µm 0.18µm Volume 4, 23-26 May 2004 Page(s):IV - 752-5 Vol.4..# no of delay 03 03 [10] Luciano Severino de Paula, Eric Fabris,cells Sergio Bampi, Altamiro Amadeu Susin,” ANo of 05 02 High Swing Low Power CMOS Differentialtransistors in Voltage-Controlled Ringdelay cell Oscillator” IEEE Computer Society Annual Symposium on VLSI(ISVLSI07) 20074 Conclusion IEEE. This paper compares the performance of a [11] W. Xin, Y. Dunshan and S. Sheng, ”A Fullcurrent starved VCO and differential VCO with the Swing And Low Power Voltage-Controlleddesign experiment and with the quantitative Ring Oscillator”, Electron Devices andevaluation. Simulation results shows that area wise, Solid-State Circuits, 2005 IEEE Conferencepower consumption and tunable frequency range, on 19-21 Dec. 2005 Page(s):141 – 143Current starved VCO is superior to a differential [12] E. Wang and R. Harjani, “Partial PositiveVCO. Power consumption and area of both VCO will Feedback for gain Enhancement of Low-decrease proportional to the technology node. Power CMOS OTAs”, Analog IntegratedHowever, noise characteristics will get worse Circuits and Signal Processing, 8, pp21-35,inversely proportional to the technology node. 1995Designed VCO is used as frequency synthesizer, [13] Kuo-Hsing Cheng ,Ching- Wen Lai and Yu-frequency multiplier and for clock systems design Lung Lo ,”A CMOS VCO for lV, lGHz PLL Applications”, 2004 IEEE Asia-PacificReferences Conference on Advanced System Integrated [1] B .Razvi, Design of ANALOG CMOS Circuits(AF-ASIC2004)/ Aug. 4-5,2004 Integrated Circuits, McGraw- Hill, 2001. [14] Jun Zhao and Yong-Bin Kim,” A Low- [2] Tianwang Li*, Bo Ye and Jinguang Jiang,” Power Digitally Controlled Oscillator for All 0.5 V 1.3 GHz voltage controlled ring Digital Phase-Locked Loops Hindawi oscillator” 2009 IEEE Publishing Corporation VLSI Design [3] Honghui Deng Yongsheng Yin Gaoming Du, Volume 2010, Article ID 946710” Phase Noise Analysis and Design of CMOS 1699 | P a g e

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