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IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com

IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com

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  • S.MohammedInthiyaz, B.Sumithra / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.1032-10391032 | P a g eFPGA Implementation of Radio Navigation Based onMicroBlazeS.MohammedInthiyaz*, B.Sumithra,M.Tech***(ECE Department,G.Pulla Reddy Engineering College Kurnool,A.P,)**(ECE Department,Assistant Processor of G.Pulla Reddy Engineering College ,Kurnool,A.P,India)ABSTRACTIn moderm aviation, navigation is animportant technology. So far, equipped inalmost all the military and civil airports,radio navigation system is the most widelyused navigation devices in aviation. Atpresent, radio navigation still has priority inshort-range navigation of civilian and militaryaviation in our country. Also, due to theimperfect landing system device in the existingaircraft, radio navigation system is of vitalimportance in ensuring safety in Plane’s homingand approaching.In the actual navigation test, tosimulate the RF signal of combined antennain radio navigation, various signal generatorsare often designed to satisfy performance ofnavigation system and meet technicalrequirements. Meanwhile, the signal generatormust adjust signal types, parameters andwork modes timely according to thenavigation system requirements. Therefore,signal generator must have the feature thatsignal can be generated flexibly, parameterschange quickly, signal spectrum staystabilized, and the system is reliable, etc.The proposed system adopts MicroBlaze soft processor as the control core ofgenerator to communicating command withPC. which can satisfy each requirement inactual application of testing and debugging onnavigation.The important role in navigation test,radio navigation generator is widely used inthe people/military plane. But traditionalequipment composed of analog circuit Presentslow accuracy and poor reliability. A new kind ofdigital navigation signal generator is designed. Itreceives data and commands from PC byMicroBlaze embedded soft processor of XilinxCompany and demodulates information tocontrol FPGA load different softwares togenerate various navigation signals, which fullymeets general radio navigation system testtechnical requirements by giving full play to thesystem hardware and software advantagesand fulfilling design targets such as theaccuracy, flexibility and expansibility.Therefore, providing a new idea for radionavigation system. this generator can be widelyapplied to debugging use on people/militaryplane radio navigation.Using FPGA instead of an ASIC givesalso flexibility for reconfiguration, which is aneed for the Software Defined Radio (SDR)concept. Modelsim Xilinx edition will be used forsimulation. The Xilinx ISE will be used forsynthesis; place & route and bit file generation.Xilnix Spartan 3E family FPGA board will beused testing the logic. The chipscope pro analyzeris used to display the captured set of results.Keywords-DDS signal generation, UART,FPGA,Micro blaze.1. INTRODUCTIONIn modem aviation, navigation is animportant technology. So far, equipped in almostall the military and civil airports, radionavigation system is the most widely usednavigation devices in aviation. At present, radionavigation still has priority in short-rangenavigation of civilian and military aviation in ourcountry. Also, due to the imperfect landing systemdevice in the existing aircraft, radio navigationsystem is of vital importance in ensuring safety inplane‟s homing and approaching.In the actual navigation test, to simulatethe RF signal of combined antenna in radionavigation, various signal generators are oftendesigned to satisfy performance of navigationsystem and meet technical requirements.Meanwhile, the signal generator must adjustsignal types, parameters and work modes timelyaccording to the navigation system requirements.Therefore, signal generator must have the featurethat signal can be generated flexibly, parameterschange quickly, signal spectrum stay stabilized,and the system is reliable.The proposed system adopts Micro Blazesoft processor as the control core of generator tocommunicating command with PC. which cansatisfy each requirement in actual application oftesting and debugging on navigation.The important role in navigation test,radio navigation generator is widely used in thepeople/military plane. But traditional equipmentcomposed of analog circuit Presents low accuracyand poor reliability. A new kind of digital
  • S.MohammedInthiyaz, B.Sumithra / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.1032-10391033 | P a g enavigation signal generator is designed. It receivesdata and commands from PC by MicroBlazeembedded soft processor of Xilinx company anddemodulates information to control FPGA loaddifferent softwares to generate various navigationsignals, which fully meets general radio navigationsystem test technical requirements by giving fullplay to the system hardware and softwareadvantages and fulfilling design targets such asthe accuracy, flexibility and expansibility.Therefore, providing a new idea for radio navigationsystem. this generator can be widely applied todebugging use on people/military plane radionavigation.2.BLOCK DIAGRAM OFIMPLEMENTING MODULESFig.1: Processing modules of FPGA2.1 DESIGN SCHEME OF DIGITAL SIGNALGENERATOROFRADIO NAVIGATIONAccording to different technicalrequirements of navigation, the generated signal isbasically formed by the carrier signal, lowfrequency modulated signal and audio modulatedsignal. Therefore, in this scheme, the signalgenerator adopts direct digital frequency synthesizer(DDS) technology to design precise clock referencesource, word length of frequency and phaseaccumulator and sine function table to generate themodulated sine signal whose frequency variationscope, step length change and precision meet theacquirements in overall design. Large-scaled FPGAis used in this system to realize accurate DDS ,ADC converter is used to convert theexternal signal to be modulated by carrier signal,and the soft embedded processor MicroBlazecommunicates with PC by RS422/232 as the controlcore, figure is the overall scheme of digital signalgenerator of radio navigation. The control softwareof PC wrote in VC6.0 communicates with thegenerator through RS422/232 is in charge oftransmitting control command to set frequency,azimuth angle, channel, working mode and otherparameters of navigation signal and receiving statusand data of the generator after every change. In thissystem, as a master unit MicroBlaze sendsparameters to FPGA after demodulating data fromPC while FPGA generates accurate navigationsignal to high-speed DAC converter as the groundfloor synthesis unit. Meanwhile, multiple clocksignals used in the system are generated in phaselock logic part of FPGA from external oscillator.2.2 DIRECT DIGITAL SYTHESIZERFig.2Playing an important role in navigationtest, radio navigation generator is widely used in thepeople/military plane. But traditional equipmentcomposed of analog circuit presents low accuracyand poor reliability. A new kind of digitalnavigation signal generator is designed in this paper.It receives data and commands from PC byMicroBlaze embedded soft processor of Xilinxcompany and demodulates information to controlFPGA load different softwares to generate variousnavigation signals, which fully meets general radionavigation system test technical requirements bygiving full play to the system hardware and softwareadvantages and fulfilling design targets such as theaccuracy, flexibility and expansibility. Therefore,providing a new idea for radio navigation systemdesign and test, this generator can be widely appliedto debugging use on people/military plane radionavigation.A Direct Digital frequency Synthesizer(DDS) design and prototype suitable for space-borne applications is presented. The design istargeted for use in the uplink section of the RFsubsystem of the New Horizons Pluto spacecraftcurrently under design at APL. Design and analysisof the digital portion of the DDS is presented alongwith experimental data from the prototype system,which was implemented using an FPGA and adiscrete digital to analog converter.Direct Digital frequency Synthesizers(DDS) are a common component in a variety ofcommunication systems, especially those requiringfast frequency hopping, low power dissipation, andsmall form factor.A DDS at its simplest is a clock-dividingcounter, termed the phase accumulator, whichgenerates a digitized ramp waveform. This ramp isconverted to a sine-wave representation andsubsequently translated to the analog domain by adigital to analog converter (DAC). Subsequentfiltering of the DAC output can be used to removethe high frequency components that arise from thedata conversion process. Fig. illustrates the
  • S.MohammedInthiyaz, B.Sumithra / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.1032-10391034 | P a g econceptual system with a j-bit accumulator outputtruncated to a k-bit ROM address space and a m-bitDAC.DDS performance is measured in a number ofways. Some are fairly generic, including powerdissipation and maximum nput clock rate and outputfrequency. Others are more specific, relating tominimum frequency step size and to the spectralpurity of the DDS output. The DDS output spectrumreflects the fact that a DDS effectively samples asine wave output. As a result, inaccuracies due tofinite word length effects as well as Nyquistsampling considerations cause the output spectrumto contain energy at frequencies other than thefundamental. These peaks, termed spurs, determinethe signal to noise level of the DDS, which isdefined as the Spurious Free Dynamic Range(SFDR). Non-idealities in the DAC can furtherdegrade the SFDR as well. In general, peaks whichare closer in frequency to the fundamentalpresentmore problems than peaks further out, simplybecause they are more difficult to attenuate with anoutput low pass filter.2.3 IMPLEMENTATION OF DDSIn this project we are using Direct DigitalSynthesizer for generation of the carrier signal. Allwe know about that by using DDS we can generatea carrier signal in the form of sine or cosine orsinecosine.Xilinx itself generate the core for DDSthat is ip core generation. In that we should selectoptions about the carrier or signal frequency inMHZ and phase off set and data width and the phaseincrement register data width depends on the datawidth or we can have a option like programmablethen we can give the phase of set and frequencylevels through the program. And we are taking thecarrier signal from the DDS and we do themodulation like AM,FM,QPSK,BPSK.And in FMtechnique we are taking DDS signal as the messagesignal and we are generating the carrier by usingthe Hardware Description Language.The Analog to Digital Module ConverterBoard (the AD1™) converts signals at a maximumsampling rate of one million samples per second,fast enough for the most demanding audioapplications. The AD1 uses a 6-pin headerconnector, and at less than one square inch is smallenough to be located at the signal source.The AD1converts an analog input signal ranging from 0-3.3volts to a 12-bit digital value in the range 0 to 4095.The AD1 has two simultaneous A/D conversionchannels, each with a 12-bit converter and filter.Each channel can sample a separate stream ofanalog signals. The AD1 can also convert a singlestream of analog signals using only one channel.Each channel has two 2-pole Sallen-Key antialiasfilters with poles set to 500 KHz. The filters limitthe analog signal bandwidth to a frequency rangesuitable to the sample rate of the converter. TheAD1 uses the SPI/MICROWIRE™ serial busstandard to send converted data to the host system.The serial bus can run at up to 20 MHz. The AD1has a 6-pin header and a 6-pin connector for easyconnection to a Digilent system board or otherDigilent products. Some system boards, like theDigilent Pegasus board, have a 6-pin header that canconnect to the AD1 with a 6-pin cable. To connectthe AD1 to other Digilent system boards, a DigilentModular Interface Board (MIB) and a 6-pin cablemay be needed. The MIB plugs into the systemboard, and the cable connects the MIB to the AD1.The AD1 can be powered by voltage from either aDigilent system board or an outside device. Damagecan result if power is supplied from both sources orif the outside device supplies more than 3V.Rst isused to reset module or clear previous data, clk isused for the synchronization, when the raising edgeof clk is „1‟ then count is a counter, go on countingfrom „0‟ to „15‟ if count is „0‟ then data present inshift resisters (signal‟s) will be forced on to theoutput‟s pdata1, if count is above „3‟ then inputswill be forced on to shift register‟s (signal‟s) fromLSB to MSB till the count „15‟ by shifting 1 bit foreach count. CS will „1‟ for the count of “15”. Pclkwill be „1‟ for 0 to 8 counts and „0‟ for the rest ofcount‟s i.e it is clk /16As we know that the analog to digitalconverter is used to convert the analog signal intothe digital samples. And we are using the 12 bit A/Dconverter means at the ADC output we get the 12 bitsample values of the analog signal. Here we aregiving a message signal (Modulating signal) throughADC. It is 2-channel ADC means we can give 2inputs at a time and here we are connecting the inputto the ADC from the Function Generator by givingthe frequency levels and selecting a wave(sine orsawtooth,Square..etc) and constant voltage levels3. BLOCK DIAGRAM OF UARTThe UART block diagram for the fpgaimplementation is shown in Fig. It consists of 4blocks namely transmitter, receiver, enablegenerator and baud generator. The uart transmitterand receiver are deigned in the same block which isshown in below. The UART is a serial interfacewith a frame format of start bit of active low „0‟atthe beginning and 8 bit of information with a stopbit of active high„1‟ signal at the end. The operationof UART is controlled by Clock signal which is fedfrom external crystal.Baud generation section is aclock divider ckt, FPGA board clock runs at50MHz, but UART transfer data at predefinedstandards that hade to be maintained, in presentsystem is designed for a rate of 9600/sec(i.e 50x106is scaled down for 9600). Generates a 9600 plusesfor a sec, this implies the speed of UART is 9600bits per sec. another clock with a 16 times faster isrequired to the receiver section so that the data willnot be corrupted, baud out is given to the enablegenerator section.Enable Generator this section
  • S.MohammedInthiyaz, B.Sumithra / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.1032-10391035 | P a g ereceives baud_clock signal as a enable signal andgives enable out signal to the transmitter section as aenable input signal.This signal is used tosynchronize the transmitter section when ever thedata is to transferred. The transmitter block isresponsible for the transmission of serial data fromUART. It takes 8-bit data from the receiver sectionin parallel andsend data in serial form. Data insertedbetween start and stop bits. An optional parity bitalso may be usedfor error detection. state machinefor transmitter is shown in Fig.Fig.3Transmitter stays in IDLE state unlesstransmit enable (tx_enable) is made as „1‟.The datatransmission starts with tx_enable = 1. As mandatedby the protocol, a „0‟ is transmitted to indicate startof transmission or start bit. This is done in STARTstate. Then data bits 0 to 7 are transmitted in statesDATA0 to DATA7. If parity is enabled inconfiguration register, the data is attached withparity in PARITY state. Then transmitter entersSTOP state and sends a „1‟. This indicates thecompletion of transmission. Then the transmitterenters the IDLE state and waits for next datatransmission.UART receiver handles reception ofdata from RS232 port. main functions of receiverblock are to convert the serial data to parallel data,check the correctness of data from parity and storethe received data.UART receiver state machine isshown in Fig. The receiver is in IDLE state bydefault. When the serial data pin goes low,indicating the start bit, the state machine entersDATA0 state. The data is received, one bit at a timefrom LSB to MSB in states DATA0 to DATA7. Ifparity is enabled, the state machine checks the paritybit received against the parity obtained fromreceived data. If the data received is fine, thedata_rx (data_rx_done) bit is set to „1‟ and thereceiver goes back to IDLE state again.top moduleis a combination of uart and a selected imageprocessing applications. Type of operation isselected by slider switches on the FPGA board eachand every block is explained in detail below.4. REALIZATION OF DIGITAL SIGNALGENERATOR OF RADIO NAVIGATIONBASED ON MICROBLAZE4.1HARDWARE PLATFORM:Xilinx XC2VlOOO of Virtex - II platformis adopted in this system which has 40 dedicatedmultiplier blocks, up to 93,184 look-uptables(LUTs) or cascadable l6-bit shift registers, 3Mb of dual-port RAM in 18 kbit block SelectRAMresources and up to l.5 Mb of distributedSelectRAM resources and clocks up to 420MHzinternal, presenting a strong computing ability andhigh speed data throughput capacity[9]. Also an in-system programmable configuration PROMXCF04SV020C is used for FPGA configuration inthis system. The MicroBlaze embedded processorsoft core is a reduced instruction set computer(RISC) optimized for implementation in XilinxFPGAs. It is highly configurable, allowing users toselect a specific set of functionality required bydesigns to build their own hardware platform [10].Fast Simplex Link (FSL) bus is a uni-directionalpointto- point channel bus used to perform fastcommunication between any two design elementson the FPGA when implementing an interface to theFSL bus. First create a hardware system whose coreis MicroBlaze under the integrated environment ofXPS using Base System Builder (BSB) wizard, thenfollow the guide of EDK to add a peripheral ofsystem with UART IP core connected byMicroBlaze F SL bus, use the Platform Generator togenerate embedded systems netlist document(.NGC) based on Microprocessor HardwareSpecification (.MHS), and finally use thesynthesized tool XST to constitute the wholehardware platform of the system [11 ]-[12]. ADCconverter is mainly used for acquiring external lowfrequency signal. AD9218 with dual lO-bit channelsof ADI company is selected in this system whichworks under 2.7V�3.6V and operates up to105MSPS conversion rate [13]. DAC converter ismainly used for generating rf modulated signal.AD9760 with single lO-bit channel of ADI companysupporting update rates up to l25MSPS is chosen inthis system, whose single supply ranges from 2.7Vto 5.5V.Design of PC Software Main task of PCsoftware is to generate control command forfrequency, azimuth angle, work mode, channelselection andother information which can bedistinguished by command head and transmitted byRS422/232 to signal generator for the correspondingdigital navigation signal. 2.2.2 Design of FPGAprocessing modules Main task of FPGA hardware isto produce precise modulatedrf modulated signal.The tasks are included as follows: 1) receiving
  • S.MohammedInthiyaz, B.Sumithra / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.1032-10391036 | P a g ecarrier frequency, azimuth angle and other Relevantcontrol commands from MicroBlaze; 2) generatingaudio signal, carrier signal andazimuth angle signal;3) receiving two channel low frequency signal fromADC converter; 4) synthesizing navigation signaland transmitting it to DAC converter according tothe command from PC. T he processing modules ofFPGA is shown in figure. Design of MicroBlazeprocessing First define software systems usingMicroprocessor Software Specification (.MSS)readable text files which describe driver informationof all peripherals. Once the system software isdefined, use the Library Generator to build system-specific library C functions that map basic Cfunctions to peripherals and to configure the Clibraries. Then write the corresponding receivingprogram code to 380 achieve MicroBlaze controlfunction using the function libraries in SDKintegrated environment. In the end, package thehardware structure and application software ofUART controller based on MicroBlaze into ISE as asub-module and complete software design ofMicroBlaze controller. The software process flow isshown in figure.4.2IMPLEMENTATION OF MICROBLAZEIn our project the Microblaze place a mainimportant role. It is a soft core processor. and weknow about the two type processors, those areMicrblaze and the Power Pc. The main differencebetween the microblaze and power pc is ,microblazeis a soft core processor and the power pc is a hardcore processor.Microblaze: Which is a soft core processor, thesome part of the fpga will acts as a microblazeprocessor by implementing the hardware descriptionlanguage means by the vhdl code we are making actof some part of fpga as microblaze. So it is called assoft core processor. No need of any externalhardware circuitry.Power Pc: It is hard core processor, means it isdifferent than microblaze. In this we should requirethe external hardware by connecting this externalhardware of the power pc to the fpga we can use theprocessor. Then the circuit complexity mayincrease.So in this project we are implementingMicroblaze soft core processor only. And thisprocessor will take the information from the Pc byusing UART. So from the we receive the commandsin hexa,ascii format. By using these commands onlywe can change our parameters of modulationtechniques like setting frequency ,setting azimuthangle, changing work mode, self testing and outputRF signal. This function we will implementing bycoding. Acoording to these commands themodulation techniques are select in the synthesizedunit.5. NUMERICAL TEST ANDSIMULATIONDue to the diversity of techniquerequirement ofnavigation signal, the main task ofgenerator is to generatedifferent kinds of rfmodulated signal. Take AutomaticDirection Finder(ADF) signal for example, it is in form ofV=E{m+Mcos(Qt+8)+v:,}cosC/{tE is the signalamplitude, m is a constant, M ismodulation index, Qis frequency of low frequencymodulated signal, e isthe azimuth angle, Va is the audiomodulated signaland We is the carrier frequency [1].AssumeE=�m=�M=o.3,Q=2.7zx<X),e=o,cq=2m<lXYc,the frequency of audio signal is 1020Hzand the samplefrequency is 40MHz and simulate theADF signal inMA TLLAB software, the result isshown in Fig.Take another signal for example, thesignal of Very highfrequencyOmnidirectional Range(VOR) can be expressedasV =URm [1 +mA cos(Qt-e) +mcos( n.t+mfcosQt) JcosatU Rm is theamplitude of reference phase signal, e is theazimuthangle , Q is the angular frequency at 30Hz, Qs istheangular frequency at 9960Hz, m A is the modifiedfactorof variable phase signals, m f is themodulation index, m ismodulation of referencephase signal and W is the angularfrequency ofcarrier signal. [1 ]Due to that the frequency of VORsignal is too high andthe hardware is limited inperformance, we assume URm = 1,m = 1 m = 03 m= 1 e = 60 w = 271x20M , the sample A . f cfrequency is 40MHz, VOR signal is simulatedinMATLLAB software and the result is shown inFig..Use the PC software to control the system togenerate theADF signal in the same condition withthe MA TLABsimulation and connect the generatedADF signal to theoscillator. The real ADF signalwaveform is shown in Fig.which is almost the samewith the simulated signal in Fig..Then connect thereal ADF signal to the spectrum analyzer,theminimum resolution of the signal is up toO.OlHz.Similarly, generate the VOR signal in thesame conditionof simulation in MA TLAB andconnect it to the oscillator.The real VOR signalwaveform is shown is Fig. which isalmost the samewith the simulated signal in Fig.. Thenconnect thereal VOR signal to the frequency analyzer,theminimum resolution of the real signal is up toO.OlHz.
  • S.MohammedInthiyaz, B.Sumithra / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.1032-10391037 | P a g e6. FINAL SIMULATION RESULTSFig.4.A.MFig.5.F.M
  • S.MohammedInthiyaz, B.Sumithra / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.1032-10391038 | P a g eFig.6.QPSK7. APPLICATIONS Aviation, navigation and other equipment. Software defined radios for militaryapplications.8. ADVANTAGES Full digital techniques can give room forfull reconfigurability of the MODEM fordifferent specifications. DDS based carrier synthesis has nolimitation for tracking the signal of evenwideband signal. FPGA based implantation will result inextremely high speed and also can provideroom for adding additional hardwareblocks.9. TOOLS AND HARDWARE Simulation software - Modelsim XilinxEdition (MXE) Synthesis, P&R - Xilinx ISE On chip verificaiton- Xilinx Chipscope Hardware - Xilinx Spartan 3 FamilyFPGA board10. CONCLUSIONIn this paper, the digital signal generatorof radio navigation is implemented by softprocessor MicroBlaze whose key portion isachieved in a single FPGA chip, which overcomesthe disadvantage of low accuracy and flat tuning intraditional methods. Simultaneously, various kindsof signals can be loaded in this system, obtainingmore flexibility and better expandability. Throughthe numerical test and simulation results, theveracity and precision is confirmed. Favorableresult has been acquired in practical application.REFERENCES[1] M.Cunbao, Z.Tianwei and L.Hongjuan,"Communication Navigation and Radar ofCivil Aircrft," Civil Avitation EngineeringCollege, NPU, 2000.[2] X.Song, "Reasearch on software radiocompass technology," University ofElectronic Science and Technology ofChina, 2007.[3] L.QIN, D.Liebo and W.Peng, "Design ofSimulative Satellite Image ResourceSystem Based on FPGA," Journal of Testand Measurement Technology, vol. 23,Mar.2009, pp. 261-265, doi: CNKI: SUN:CSJS.0.2009-03-015.[4] Z.Mingjie, G.Wei, "Design of GPS IFsignal generator in FPGA," InformationTechnology, NO.8, Aug.2008, pp. 56-58,doi: CNKI: SUN:HDZJ.0.2008-08-021.F1GA XilUlX V2 Interface of power
  • S.MohammedInthiyaz, B.Sumithra / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.1032-10391039 | P a g eCache CacheLblJ Indicator Rf signalOutput PC .[5] L.Xiaoming and Q.xiujie, "Application ofDDSIFPGA in Signal Generator Systems,"Modem Electronics Technique, vol. 29,Sep.2006, NO.9, pp.78-79, doi:CNKI:ISSN:I004-373X.0.2006-09- 027.[6] Y. Yong and Z.xiaolin, "Design andImplementation of Direct DigitalFrequency Synthesis Sine Wave GeneratorBased on FPGA," Journal of ElectronDevices, vo1.28, NO.1, Mar.2005, pp:596-599, doi:cnki:ISSN: 1 00 5-9490.0.200 5-03-034.[7] A.Grama and G.Muntean. "Direct digitalfrequency synthesis implemented on aFPGA chip," the 29thInternational SpringSeminar on Electronics Technology: NanoTechnologies for Electronics Packaging,May.2006, pp. 92-97, doi:10.1109/ISSE.2006.365365.[8] D.J.Betowski and V.Beiu, Considerationsfor phase accumulator design for DirectDigital Frequency Synthesizers, IEEEInternational Conference on NeuralNetworks and Signal Processing,Dec.2003, pp: 176-179, doi:10.ll09/ICNNSP.2003.1279240.