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IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com

IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com

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    • Ganesh L K M, LopamudraPattanayak / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.957-960957 | P a g eVLSI Testing Technique for BIST:Using Priority BasedAlgorithmGanesh L K M*, LopamudraPattanayak**(*AsstProfessor,,School of Electronics Engineering,KIIT University, Bhubaneswar,Odisha, INDIA)(**M. Tech. VLSI Design and Embedded System ,,School of Electronics Engineering,KIIT University,Bhubaneswar,Odisha, INDIA)ABSTRACTThe paper presents a low test time BISTbased on Priority Algorithm (PA) is applied forthe 32-bit Carry Look-Ahead Adder. Thismethod assigns priority to the test patterns basedon faulty coverage and independent faultydetecting test patterns. Experiment conducted onCadences’ RTL Compiler Tool and Cadences’Encounter Tool demonstrate that proposedscheme gives better performance with largereduction in test time and power dissipationduring testing.Keywords- BIST, LFSR, Priority Test Patterns,Test TimeI. INTRODUCTIONBuilt-In Self-test (BIST) is the ability of anintegrated circuit (IC) to examine its own functionalhealth, in order to detect and report faults that mayjeopardize the reliability of the application whereinit is deployed. The test time of a chip depends on thetypes of tests conducted [1]. These may includeparametric tests (leakage, contact, voltage levels,etc.) applied at a slow speed, and vector tests (alsocalled “functional tests” in the ATE environment)applied at high speed. The time of parametric tests isproportional to the number of pins since these testsmust be applied to all active pins of the chip. Thevector test time depends on the number of vectorsand the clock rate. The total test time for digitalchips ranges between 3 to 8 seconds. The vectorsmay not cover all possible functions and datapatterns but must have a high coverage of modeledfaults. The main driver is cost, since every devicemust be tested. Test time (and therefore cost) mustbe absolutely minimized. During Test mode, powerconsumption will double than normal mode [2].This Priority Test Pattern method saves significanttest time and power consumption by shortening thepattern sequence.II. BIST STRUCTUREBlock Diagram of BIST is shown infigure.1. BI is enable pin for BIST operation and BOis output of BIST operation, based on BO only cansay whether given CUT is working properly arenot.When BI = 0, Test Pattern Generator and IdealResponse Block are in OFF state. MUX will acceptInput and applied to CUT and outputs are taken atOutput pin. When BI = 1, Test Pattern Generator andIdeal Response Block are in ON state. MUX willaccept Test Pattern Generator output and applied toCUT and outputs are taken at BO pin. When BO is1,indicates IC is working properly otherwisemalfunction is there in IC.Fig 1.Block Diagram of BISTIII. PRIORITY ALGORITHMIf “n” is number of input present in digitalcircuit and “M = 2n”input vector is present. For ninput digital circuit, “F” is number of fault.TABLE 1. LIST OF FAULT COVEREDSl.No Input VectorNo ofFault Covered1 1stInput Vector X12 2ndInput Vector X2.. …….. ………M M Input Vector XMPriorities are assigning as follows 1stPriority Y1 = max (X1, X2, X3,……..XM ) 2ndPriority Y2 must select such that Y2must cover maximum remaining fault (F – Y1). Forexample, 100 faults are present in digital circuits andfirst input pattern is covering maximum of 42 faults.Second input patterns must select such that it mustcover maximum remaining fault (100 – 42 = 58). 3rdPriority Y2 must select such that Y2 mustcover maximum remaining fault (F – Y1 – Y2) andsoon.
    • Ganesh L K M, LopamudraPattanayak / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.957-960958 | P a g eFig 2. Flow chart of Priority AlgorithmFor example CLA is taken as CUT• CLA is used in most ALU designs.• It is faster compared to ripple carry logicadders or full adders especially when adding a largenumber of bits.• The Carry Look Ahead Adder is able togenerate carries before the sum is produced using thepropagate and generate logic to make addition muchfaster.When BI is 1 and it will represented in a verilogcode with test timing insertion and after that it willbe simulated in Xilinx 9.2 version and the RTLdiagram of 32 bit CLA is show in figureFig 3. Test bench of 32 bit CLAFig 4.RTL diagram of 32 bit CLAFour test patterns are sending to CLA (CUT) whichis independent to each other for fault detecting.Total no of faults is 258(64*2+33*2+32*2)1. No of fault coverage =66/258=25%(Input A=8’h00000000, Input B=8’hFFFFFFFFand Input Cin= 1’b0) stuck_at_1 at port A and portCin can be detected2. No of fault coverage =66/258=25%(Input A=8’hFFFFFFFF, Input B=8’h00000000and Input Cin= 1’b0) stuck_at_1 at port B and portCin can be detected3. No of fault coverage =66/258=25%(Input A=8’h00000000, Input B= 8’hFFFFFFFFand Input Cin = 1’b1)stuck_at_0 at port B and port Cin can be detected4. No of fault coverage =66/258=25%(Input A=8’hFFFFFFFF, Input B= 8’h00000000and Input Cin=1’b1)stuck_at_0 at port A and port Cin can be detected.Fig 5. Test bench of 32bit CLA using BISTIV. SIMULATION RESULTSVerilog codes were used to simulate thetest generation process performed using Cadences’RTL complier Tool and Layout analysis isperformed using Cadences’ Encounter Tool.1. Leakage power, dynamic power and totalpower calculations in nW for 32-bit CLA, LSFR-BIST and PA-BIST are shown in figure 6,7 and 8respectively.
    • Ganesh L K M, LopamudraPattanayak / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.957-960959 | P a g eFig 6.Power Calculation of 32-bit CLAFig 7.Power Calculation of LSFR-BISTFig 8.Power Calculation of PA-BIST2. No of Gates used to design of 32-bit CLA,LSFR-BIST and PA-BIST are calculated and shownin figure 9, 10 and 11 respectively.Fig 9.Gates Calculation of 32-bit CLAFig 10. Gates Calculation of LFSR-BISTFig11.Gates Calculation of PA-BIST3. Area of 32-bit CLA, LSFR-BIST and PA-BIST are calculated and shown in figure12,13 and14 respectively.Fig 12. Area Calculation of 32-bit CLAFig 13.Area Calculation of LFSR-BISTFig 14.Area Calculation of PA-BIST4. Layouts of LFSR-BIST and PA-BISTwithout negative slacks are shown in figure 15 and16 respectively.
    • Ganesh L K M, LopamudraPattanayak / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.957-960960 | P a g eFig 15.Layout of LFSR-BISTFig16.Layout of PA-BISTLFSR-BIST and PA-BIST with all parameters arecompared in Table-IITable 2. Comparison of LSFR-BIST and PA-BISTParametersCLAUsingLFSRPercentageUsingPA-BISTPercentageAREA(in µm)883118295.251%14390.00638%Power(innW)1191632242198250%182440634%No ofGates241 521 53% 325 34%V. CONCLUSIONAs showed in table 2, PA-BIST can highlyreduce the test time, during BIST application, thatis, all the total power, area and the no of gatesare highly reduced. Experimental results based onCadences’ RTL Complier tool and Encounter toolfor BIST applications show that about 51% to 38%reduction in area, 50% to 34% reduction in thepower and 53% to 34% reduction in no of gates usedand BIST achieved without losing the stuck-at faultcoverage.A comparison of reduction of powerconsumption between LFSR-BIST and PA-BISTwas reported, to demonstrate that PA-BIST is muchmore efficient in the reduction of peak powerconsumption when the pattern is applied to 32-bit Carry Look Ahead Adder.REFERENCE1. Michael L. Bushnell,Vishwani D. Agrawal“Essentials of ElectronicTesting fordigital,memory and mixed-signal vlsicircuits”Kluwer Academic Publishers,pp.11-12.2. Y Zorian, “A Distributed BIST controlscheme for Complex VLSIdevices.”. IEEEPZSITeslSymp. 1993, pp.4-9.3. Michael L. Bushnell,Vishwani D. Agrawal“Essentials of ElectronicTesting fordigital,memory and mixed-signal vlsicircuits”Kluwer Academic Publishers,pp.496-498.