DPV Bharathi, B. Sruthi Reddy / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.621-624621 | P a g eImplementation of Carrier Synthesis Technique Using DPLLDPV Bharathi B. Sruthi ReddyG. Pulla Reddy Engg. College, Kurnool G. Pulla Reddy Engg. College, KurnoolAbstractDPLLs are used widely incommunications systems like radio,telecommunications, computer and otherelectronic applications. Digital PLLs are a type ofPLL used to synchronize digital signals. WhileDPLLs input and outputs are typically all digital,they do have internal functions which aredependent on analog signals. The main blocks indemodulator are DDS core, Filters, Arc tanestimator, Loop filter. The area reduction for on-chip applications can be achieved throughoptimization of the number of micro rotations inproposed design. For better loop performance ofsecond order complex DPLL and to minimizequantization error, the numbers of iterations arealso optimized. Modelsim Xilinx Edition (MXE)and Xilinx ISE will be used simulation andsynthesis respectively. The Xilinx Chipscope toolwill be used to test the FPGA inside results whilethe logic running on FPGA. The Xilinx Spartan 3Family FPGA development board will be usedthis project.Keywords—Digital Signal Processing, DPLL,Micro-rotation, Loop performance, Arctanestimator.I. INTRODUCTIONThe progress in increasing theperformance, speed, reliability and the simultaneousreduction in size and cost of integrated circuits hasresulted in strong interest being shown in theimplementation of control and communicationsystems in the digital domain. Aside from thegeneral advantages associated with digital systems,a digital version of the phase-locked loop solvessome of the problems associated with its analoguecounterpart; namely sensitivity to DC drifts andcomponent saturations, difficulties encountered inbuilding higher order loops and the need for initialcalibration and periodic adjustments. In addition,with the ability to perform elaborate real-timeprocessing on the signal samples, the DPLLs can bemade more flexible and versatile, especially by theuse of microprocessors.The earliest efforts on DPLLs concentratedon partially replacing the analogue PLL (APLL)components with digital ones. The first all DPLLwas reported by Drogin in 1967.Since then, differentauthors have suggested many kinds of all digitalphase-locked loops and have discussed variousaspects of implementing them. All DPLLs arecategorized into two classes as follows:1. Uniform sampling DPLL, in which the inputsignal is sampled at a fixed rate (Nyquist rate).2. Non-uniform sampling DPLL in which thesampling rate is variable.DPLL is suitable for coherent (all digital)communications. This DPLL contains a purelydigital phase detector, loop filter and voltage-controlled oscillator, providing an extremely widetracking frequency range and a completely linearbehavior.DPLL is very popular in synthesizer applications.Frequency synthesis is currently a very importantPLL application area.In this project, we will recover the carrier signal.This carrier signal is high speed recovery signal andwe achieve area optimization, reprogrammable andlow power features.The remaining paper is organized as follows:Section-II deals with the background of the DPLLs,section-III describes the proposed design andsection-IV gives the simulation results and theanalysis of the proposed design.II. BACKGROUNDPLL Stands for phase-locked loop and isbasically a closed loop frequency control system,which functions based on the phase sensitivedetection of phase difference between the input andoutput signals of the controlled oscillator. The PLLmethod of frequency synthesis is now the mostcommonly used method of producing highfrequency oscillations in modern communicationsequipment. PLL circuits are now frequently beingused to demodulate FM signals, making obsolete theFoster-Seerly and radio detectors of the early years.Other applications for PLL circuits include AMdemodulators, FM demodulators, FSK demodulator,and other communication areas.The PLL technique has surprisingly beenaround for a long time. In the 1930’s the superheterodyne receiver was in its hayday, howeverattempts were made to simplify the number of tunedstages in the super heterodyne.In the early 1930’s the super heterodynereceiver was king. The super heterodyne eventuallyextended its domain far beyond commercialbroadcast receivers and for microwave radarreceivers developed during worldwar2.
DPV Bharathi, B. Sruthi Reddy / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.621-624622 | P a g eIn the 1940’s the first wide spread use of the phaselocked loop was in the synchronization of thehorizontal and vertical sweep oscillators intelevision receivers to the transmitted sync pulses.Such circuits carried the names synchro-lock andsynchro-guide. Since that time, the electronic phaselocked loop principle has been extended to otherapplications. For example, radio telemetry data fromsatellites used narrow band, phase-locked loopreceivers to recover low-level signals in thepresence of noise other applications now includeAM and FM demodulators, FSK decoders.Normally PLLs are classified into 4 classes.a. Analog or Linear PLL (APLL)b. Digital PLL (DPLL)c. All digital PLL (ADPLL)d. Software PLL (SPLL)In this, project we will discuss on DPLL. It consistsof all digital PLL blocks. Traditional DPLL blockdiagram consists of three major functional units.1. Phase detector2. Digital loop filter3. Voltage-controlled oscillator.III. PROPOSED SYSTEMMain objective of this project is high speed carrierrecovery using DPLL. We designs second ordercomplex DPLL which functions as a FMdemodulator.The proposed design consists of thereprogrammable, area optimized and low powerfeatures. The modulator and demodulator contain acompressed direct digital synthesizer (DDS) forgenerating the carrier frequency with spurious freedynamic range. The demodulator has beenimplemented based on the digital phase locked loop(DPLL) technique and it is shown on fig.1. Here wehad given the modulated signal to this block. Theproposed FM modem has been implemented andtested using Spartan 3e board as a target device.FM Demodulator:The main blocks of demodulator are1. DDS2. Filters3. Arc tan estimator4. Loop filterDDS: DDS is a type of frequency synthesizer usedfor creating arbitrary waveforms from a single,fixed-frequency reference clock. Applications ofDDS include: signal generation, local oscillators incommunication systems, function generators,mixers, modulators, sound synthesizers and as a partof a digital phase-locked loop.Fig1: Demodulation block diagram using DPLLA basic direct digital synthesizer consistsof a frequency reference, a numerically controlledoscillator and a digital-to-analog converter. A DDShas many advantages over its analog counterpart,the phase-locked loop including much betterfrequency agility, improved phase noise, andprecise control of the output phase acrossfrequency switching transitions.Filter: The carrier waves (cosine and sine) that aregenerated by DDS core is given as input to thefilter. The direct form of FIR filter is standardlinear convolution, which described the output asconvolution of input and impulse response of thefilter.𝑦 𝑛 = 𝑥 𝑛 ∗ 𝑐 𝑛= 𝜀 𝑥 𝑘 𝑐 𝑛 − 𝑘= 𝜀 𝑐 𝑘 𝑥[𝑛 − 𝑘]Where c[n] values represent filter coefficients, andx[n] represents the input samples.ATANFIR LPFFIR LPF+++=z-1z-1COSSINDDSƟr(n)x(n)y(n) PVkpkikd
DPV Bharathi, B. Sruthi Reddy / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.621-624623 | P a g eFinite impulse response (FIR) filters arethe most popular type of filters implemented insoftware. Filters are signal conditioners. Eachfunctions by accepting an input signal, blockingpre-specified frequency components, and passingthe original signal minus those components to theoutput. FIR filter is a filter structure that can beused to implement almost any sort of frequencyresponse digitally. An FIR filter is usuallyimplemented by using a series of delays,multipliers, and adders to create the filter’s output.Arc tan estimator as Phase detector: Theoutputs of filters are given to this module. Arctan(y/x) returns in radians. The result is between –piand pi. The phase detector is a device thatcompares two input frequencies, generating anoutput that is a measure oftheir phase difference. This module gives thefrequency.Loop filter as PID Controller: AProportional-integral-derivative controller is ageneric control loop feedback mechanism widelyused in industrial control systems, a PID is themost commonly used feedback controller. A PIDController calculates an error value as thedifference between a measured process variableand desired set point. The controller attempts tominimize the error by adjusting the process controlinputs. The PID controller calculation involvesthree separate constant parameters, and isaccordingly sometimes called three-term control:the proportional, the integral and derivative values,denoted P, I, and D. These values can beinterpreted in terms of time: P depends on thepresent error, I on the accumulation of past errors,and D is a prediction of future errors, based oncurrent rate of change.If a controller starts from a stable state atzero error (PV=SP), then further changes by thecontroller will be in response to changes in othermeasured or unmeasured inputs to the process thatimpact on the process, and hence on the PV.Variables that impact on the process other than theMV are known as disturbances. Generallycontrollers are used to reject disturbances and/orimplement set point changes.In theory, a controller can be used tocontrol any process which has a measurable output(PV), a known ideal value for that output (SP) andan input to the process (MV) that will affect therelevant PV. Controllers are used in industry toregulate temperature, pressure, flow rate, chemicalcomposition, speed and practically every othervariable for which a measurement exists.The loop filter/loop controller used is PIDController. The transfer function of the PIDController looks like the following:𝐾𝑃 +𝐾𝐼𝑆+ 𝐾 𝐷 𝑆 =𝐾 𝐷 𝑆2+ 𝐾𝑃 𝑆 + 𝐾𝐼𝑆Where KP = Proportional gain KI = Integral gain KD = Derivative gainTuning a control loop is the adjustment ofits control parameters to the optimum values for thedesired control response. Stability is a basicrequirement, but beyond that, difference systemshave different behavior, different applications havedifferent requirements, and requirements mayconflict with one another.If the PID controller parameters arechosen incorrectly, the controlled process input canbe unstable, i.e. its output diverges, with or withoutoscillation, and is limited only by saturation ormechanical breakage. Instability is caused byexcess gain, particularly in the presence ofsignificant lag. Generally, stability of response isrequired and the process must not oscillate for anycombination of process conditions and set points,though sometimes marginal stability is acceptable.The response from arctan estimator is given to loopfilter. This helps in minimizing the error.IV. SIMULATION RESULTS ANDANALYSISThe FM modem process and thearchitecture is developed. Here modelsim tool isused in order to simulate the design and to checkthe functionality of the design. Once the functionalverification is done, the design is taken to theXilinx tool for synthesis process and the netlistgeneration.This simulation is performed beforesynthesis process to verify RTL (behavioral) codeand to confirm that the design is functioning asintended. Behavioral simulation can be performedon VHDL design. In this process, signals andvariables are observed, procedures and functionsare traced and break points are set. This is a veryfast simulation and so allows the designer tochange the HDL code if the required functionalityis not met with in a short time period. Since thedesign is not yet synthesized to gate level, timingand resource usage properties are still unknown.In this project we recovered high speedcarrier signal, minimized the area and also achievedlow power features.V. REFERENCES1. Lindsey, W.C., and Chie,C.M: “A Surveyof digital phase-locked loos”,proc.IEEE,19812. Gardner, F.M.: Phase lock techniques3. Ulrich Rohde, “Digital PLL frequencysynthesizers”, prentice-hall,London, 1983.4. G.S.Moschytz, “Miniaturized RC filterusing phase-locked loop”, Bell systemTech.journal5. Dan wolaver, “phase-locked loop circuitsdesign”, prentice hall, New jersey.
DPV Bharathi, B. Sruthi Reddy / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.621-624624 | P a g e6. Vuori J, “Implementation of a digitalphase locked loop using cordicalgorithm” IEEE international symposiumon circuit and systems Atlanta.Fig1: Modulated signalFig2: Intermediate signalsFig3: Loop filter output