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IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com

IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com

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  • 1. Bala Rama Pavithra, Suresh Angadi / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.596-601596 | P a g eA Proposed Design of Five Transistor CMOS SRAM Cell forHigh Speed ApplicationsBala Rama Pavithra[1], Suresh Angadi[2][1]ECE Department, K L University[2]Assistant Professor , ECE Department ,K L UniversityAbstractStatic random access memories (SRAMs)is made up of very large scale integrated (VLSI)circuits. A SRAM cell to operate in the deep sub-micron ranges it should meet some stringentrequirements . This paper presents a new fivetransistor (5T) CMOS SRAM cell to accomplishimprovements in stability, power dissipation, andperformance over previous designs, for highspeed and high stability memory operation. Thiscircuit is simulated in a proprietary 180 nmCMOS process, using Cadence Spectre andBSIM3v3 models. Here we are comparing 5TSRAM cell with 6TSRAM cell and thus provinghow 5T SRAM cells are more beneficial throughvarious simulations.Keywords– CMOS, SRAM, VLSI, Static NoiseMargin (SNM).I. INTRODUCTIONColossal advances in CMOS technologyhave made it possible to design chips with highintegration density, better performance, and lowpower consumption. To attain these objectives, thefeature size of the CMOS devices has facedaggressive scaling down to very small features anddimensions. However, the leakage current hasincreased immensely with technology scaling, andhas become a major contributor to the total IC power[1]. In addition, as feature size of CMOS devicesscales down, the random variations in processparameters have emerged as a major designchallenge in circuit design [2]. These randomvariations of device parameters in nano-scale CMOStechnologies include random variations in channellength, channel width, oxide thickness, thresholdvoltage, etc [2]. These random parameter variationsresult in significant variation in the characteristic ofdigital circuits.Modern microprocessors employ on-chipcaches, which can effectively reduces the speed gapbetween the processor and main memory to boostsystem performance. These on-chip caches areusually implemented using arrays of SRAM cells. Asix transistor (6T) SRAM cell, shown in Fig. 1, isconventionally used as the memory cell. However,the mismatch in the strength between transistors of6T SRAM cell due to process variations can resultsin failure during read operation, i.e. flipping of thecell data while reading, especially at lower levels ofVDD[3]. Therefore, conventionalSRAM cell showspoor stabilityat verysmallfeature size. In addition, asCMOS technology scales down, an increase in totalleakage current of a chip is observed.Fig. 1. Conventional 6T SRAM CellMoreover, the total leakage current of achip is proportional to the number of transistors onthe chip. Since the SRAM includeslarge number oftransistors on a chip, the SRAM leakage has alsobecome a more significant component of total chipleakage in scaled CMOS technology. Hence,stability during read operation and leakage current ofSRAM cell are two most prominent parameters indesigning of SRAM cell in nano-scale CMOStechnologies.A novel 5T SRAM cell [4] has beenpreviously proposed as an improvement to thestandard six transistor (6T) SRAM cell model invarious aspects. This 5T SRAM cell, as shown inFig. 2, comprises two inverters, connected back-to-back and one additional transistor that is used toaccess the cell for read and write. Here both the bit-lines are precharged to VDD to retain the data duringstandby mode. However, the speed of a cell, whichcharacterizes the performance of the cell, is still tobe improved to reduce the speed gap further betweenprocessor and main memory.In response to these challenges in bothconventional 6T and novel 5T SRAM cells, a new5T SRAM cell has been proposed and itsperformance issues are discussed. The rest of the
  • 2. Bala Rama Pavithra, Suresh Angadi / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.596-601597 | P a g epaper is organized as follows.Section II discussesbasic structure, write, and read operationsof theproposed 5T SRAM cell.Section III exploresdetailed static noise margin (SNM) analysis of theproposed cell under various modes.Section IVpresents the simulation resultsperformedFig. 2. Novel 5T SRAM Cellin a proprietary 180 nm CMOS process.On the basisof results analyzed, section V concludes thesignificance of the proposed cell in various highspeed, high stability, and low power applications.II. PROPOSED 5T SRAM CELLFig. 3 shows the proposed five transistor(5T) SRAM cell. In this cell, Inverter NMOStransistors (M1, M3) are directly connected to the bitlines, PMOS transistors (M2, M4) are connected topower supply voltage (VDD), and thereis an additionaltransistor M5 coupling the inverters. Unlike standardcell, no word line transistors are needed to provideaccess during the read and write cycles. In contrast tonovel 5T cell, bit lines of the proposed cell areprecharged to ground.A. Standby ModeBefore discussing the operation of proposedSRAM cell, operations of the previously introducednovel 5T cell will be reviewed to clarify thedifference between former and later.In the novel 5Tcell, introduced earlier [4], when the cell is in a standby cycle, M5 is turned off by keeping wordline(WL)at ground, the bitlines are precharged to VDD, and thedata is preserved by the cross-coupled inverters.In theproposed 5T cell, as shown in Fig. 3, during stand byperiod (precharge stage) the wordline (WL) associatedwith M5 is set to low, which turns off M5, andbitlines are precharged to ground so that the datawhich was written during write operation is retainedby the cross-coupled inverters.B. Write OperationThe write operation is accomplished byeffectively asserting the wordline(WL).Simultaneously, depending onFig. 3. Proposed 5T SRAM Cellthe state already stored in the cell, either write “0” orwrite “1” signalis activated to push one of thebitlines to approximately 2/3 VDD so that thecontents of the cell will flip to reflect the bitlinedata. Consider the situations for the two possiblewrite operations that can be performed on the cell:Write “0” OperationAssume that initially, i.e. before write “0”operation, the values of the Q and Q_b of the cell areat “1” and “0” respectively. In this stage, transistorsM2 and M3 are in the triode region, and M1 and M4are in cut-off. The operation of write “0” isaccomplished by forcing BL_b to approximately2/3VDD by turning on both the PMOS transistorsassociated with write “0” and EN signals. Now thesource voltage of the NMOS transistor M3 is atapproximately 2/3 VDD rather than “0”, and there is acharge transfer between input terminals of theinverters because of turn on transistor M5. Thus Q_bis getting charged towards VDD due to M3, which isconducting in the triode region. When the voltage atQ_b exceeds the threshold voltage of M1, the voltage
  • 3. Bala Rama Pavithra, Suresh Angadi / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.596-601598 | P a g eat Q starts discharging towards “0”. This initiates aregenerative effect between the two inverters [5].Eventually, M2 turns off and the voltage at Q falls to“0” due to the pull-down action of M1.Simultaneously, M4turns on and the voltage atQ_brises to VDD due to the pull-up action of M4.When the cell finally flips to the new state, thewordline associated with M5 is returned to its lowstand by level.Write “1” OperationAssume that initially, i.e. before write “1”operation, the values of the Q and Q_b of the cell areat “0” and “1” respectively. In this stage, transistorsM1and M4 are in the triode region, and M2 and M3are in cut-off. The operation of write “1” isaccomplished by forcing BL to approximately 2/3VDD by turning on both the PMOS transistorsassociated with write “1” and EN signals. Now thesource voltage of the NMOS transistor M1 is atapproximately 2/3 VDD rather than “0”, and there is acharge transfer between input terminals of theinverters because of turn on transistor M5. Thus Q isgetting charged towards VDD due to M1, which isconducting in the triode region. When the voltage atQ exceeds the threshold voltage of M3, the voltage atQ_b starts discharging towards “0”. This initiates aregenerative effect between the two inverters [5].Eventually, M4 turns off and the voltage at Q_b fallsto “0” due to the pull-down action of M3.Simultaneously, M2 turns on and the voltage at Qrises to VDD due to the pull-up action of M2. Bothwrite operations are clearly shown in Fig. 4.C. Read OperationThe read operation is achieved simply byasserting the wordline (WL), which is associated withthe additional transistorM5. Consider the situationsfor the two possible read operations that can beperformed on the cell:Read “0” OperationAssume that a “0” is stored in the cell, whichimplies that Q and Q_b of the cell are at “0” and “1”respectively. Therefore, transistors M1 and M4 are inthe triode region and M2 and M3are in cutoff.Initially, BL andBL_bare precharged toa low voltagearound ground by a pair of column pull-downtransistors as shown in Fig. 3. The wordline (WL),held low in the stand by state, is now raised to VDDwhich turns on additional transistor M5, which in turncreates a current path from the bitline to VDD throughthe cell. This results in the voltage at Q increases to alittleamount from ground and at the same time thevoltage at Q_b decreases by a little amount from VDD.The voltage at Q is transferred immediately to BL dueto M1, which is conducting in the trioderegion.Meanwhile, on the other side of the cell, thevoltage on BL_b remains low since thecolumn pulldown transistor dominates the transistor M3, which isconducting at the edge of the cut-off region. Thedifference between BL and BL_b is fed to a senseamplifier in a proper manner to generate a valid lowoutput, which is then stored in a data output buffer. Incontrast to conventional 6T SRAM cell, here thebitlines are fed to the sense amplifier in invertedfashion to read proper data from the cell. Uponsuccessful completion of read cycle, the wordline(WL) is returned to its low stand by level and both thebitlines are precharged back to a value aroundground.Read “1” OperationAssume that a “1” is stored in the cell, whichimpliesthat Q and Q_b of the cell are at “1” and “0”respectively. Therefore, transistors M2 and M3 are inthe triode region and M1 and M4are incutoff.Initially, BL andBL_bare prechargedtoa lowvoltage around ground by a pair of column pull-downtransistors asshown in Fig. 3. The wordFig. 4. Waveforms for writeand read operations ofproposed 5T SRAMline (WL), held low in the stand by state, is raised toVDD which turns on additional transistor M5, which inturn creates a current path from the bitline to VDDthrough the cell. This results in the voltage at Q_bincreases to little amount from ground, and at thesame time the voltage at Q decreases by a littleamount from VDD. The voltage at Q_b is transferredimmediately to BL_b due to transistor M3, which isconducting in the triode region. Meanwhile, on theother side of the cell, the voltage on BL remains lowsince the column pull down transistor dominates thetransistor M1, which is conducting at the edge of thecut-off region. As mentioned in read “0” operation,here also the difference between BL and BL_b is fedto a sense amplifier in a proper manner to generate avalid high output. The length of the additionaltransistor M5 is 3-4 times longer than the minimumlength (Lmin), and all the transistor sizes have beenproperly designed so that the cell can preserve dataduring read operation. Both the read operations areclearly shown in Fig. 4.
  • 4. Bala Rama Pavithra, Suresh Angadi / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.596-601599 | P a g eIII. STATIC NOISE MARGIN ANALYSIS OFPROPOSED FIVE TRANSISTOR SRAM CELLThe stability and robustness of a proposedSRAM cell is usually evaluated by analyzing both itsdynamic and static behavior during the write, read,and hold operations. Stability of the memory cell canbe estimated from the static noise margin (SNM)analysis. SNM is defined as the minimum DC noisevoltage needed to flip the cell state [6],and is used toquantify the stability of the SRAM cell using a staticapproach. A significant effort has been devoted toexplore the impact of process variations using theSNM. Here about proposed 5T SRAM cell’s staticstability during read and hold period has beenpresented, and the differences between SNM duringhold and read modes are compared. The read mode isusually identified as the cell’s weakest mode.A. SNM During Hold ModeThe SRAM cell immunity to static noise ismeasured in terms of SNM that quantifies themaximum amount of voltage noise that the cell cantolerate at the output nodes of the cross-coupledinverters without flipping the cell. The graphicalmethod to determine the SNM uses the static voltagetransfer characteristics (VTC) of the SRAM cellinverters.Fig. 5 superimposes the VTC of one inverterto the inverse VTC of the other inverter. The resultingtwo lobed graph is called a “butterfly” curve and isused to determine SNM. Its value is defined as theside length of the largest square that can be fittedinside the lobes of the “butterfly” curve [6]. Fig. 5shows that the variation of the “butterfly” curves fortwo supply voltages (VDD, 2/3 VDD) during holdoperation. It clearly shows that lowering the powersupply voltage reduces the SNM.B. SNM During Read ModeStatic noise margin is a key performancefactor to estimate the ability of the cell that canpreserve data during the read operation. SNM duringread can be evaluated from voltage transfercharacteristic curves obtained by setting wordline(WL) to high, while both the bitlines are prechargedto a low voltage around ground. Generally, SNMduring read takes its lowest value and the cell is in itsweakest state.The “butterfly” curves, shown in Fig. 6, areformed by superimposing of both inverter VTCstaken under read operation. Fig. 6 shows thevariation of SNM for two power supply voltagesduring read operation, and degradation of the staticnoise margin with reduction of power supply voltage.The SNM during hold and read operation for twodifferent power supply voltages corresponding to anSRAMFig. 5. “Butterfly” curves during Hold operationFig. 6. “Butterfly” curves during Read operationcellwith cell ratio (r) of 2 are tabulated in Table I.Cell ratio(r) is defined below:𝐶𝑒𝑙𝑙𝑟𝑎𝑡𝑖𝑜 𝑟 =𝛽 𝑑𝑟𝑖𝑣𝑒𝑟𝛽 𝑎𝑐𝑐𝑒𝑠𝑠(1)Where, βdriver is the transconductance of thestorage transistors and βaccess is the transconductanceof the access transistors. M1 and M3 act as accesstransistors and M2 and M4act as storage or drivertransistors in the proposed design.The SNM reductionduring read operations with respect to hold operationsis considerable at each supply voltage.C. Impact of Power Supply Voltage Modulation onRead SNM
  • 5. Bala Rama Pavithra, Suresh Angadi / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.596-601600 | P a g eFig. 7 shows that the impact of power supply voltagereduction on read SNM under various processcorners. It is clear that irrespective of the processvariations, SNM is reduced significantly with thereduction of power supply voltage. Hence, it is morepreferable to maintain full VDDwhile reading thememory.IV. SIMULATION RESULTSThe above implemented proposed 5T SRAMwith cell ratio (r) of 2 was simulated along withconventional 6T and novel 5T SRAM cells in 180 nmCMOS process using Cadence Spectre and BSIM3v3models.SNM DURING HOLD AND READ OPERATIONS VERSUSPOWER SUPPLY VOLTAGEMode ofoperation SNM@VDD(mV) SNM@2/3 VDD ((mV)HOLD 600 480READ 432 348Fig. 7. Impact of Power Supply VoltageReduction on Read SNMThe layout of the proposed 5T SRAM cell isshown in Fig.8, and all the parasitic capacitances,which were extracted from the layouts, along withsome additional bitline capacitance approximately100 fF are included during simulations. Thecomparison of the proposed 5T SRAM to theconventional 6T and novel 5T SRAMs are tabulatedin Table II and Table III respectively. It is observedthat the proposed 5T SRAM cell shows good stabilityover both the conventional 6T and novel 5T SRAMswith better performance and low power consumption.Fig. 8.Layout of theProposed 5T SRAM CellTABLE I. PERFORMANCE COMPARISON BETWEENPROPOSED 5TAND CONVENTIONAL 6T SRAM CELLSMetricConventional Proposed %Improvement6T SRAM5TSRAMRead SNM 255 mV 432 mV 40.97Write Delay 120 ps 101.41 ps 15.49Read Delay392.4ps 303.46 ps 22.66PowerConsumption 139.14 µW 117.1µW 15.84TABLE II. PERFORMANCE COMPARISON BETWEENPROPOSED 5TAND NOVEL 5T SRAM CELLSMetricNovel Proposed %Improvement5T SRAM5T SRAMRead SNM400mV 432 mV 7.4Write Delay 300 ps101.41ps 66.19Read Delay469ps303.46ps 35.29PowerConsumption122.94µW 117.1 µW 4.75V. CONCLUSIONWith the aim of attaining a high stability andbetter performance SRAM, a five transistor (5T)SRAM cell is designed and simulated using a 180 nmCMOS process. The proposed cell exhibits 22.66%better performance with respect to conventional 6T,
  • 6. Bala Rama Pavithra, Suresh Angadi / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.596-601601 | P a g eand 35.29% improvement with respect to novel 5TSRAM cell. Read static noise margin of the proposedcell is 40.97% higher than the conventional 6TSRAM cell with significant reduction in powerconsumption. Simulated results, as seen from processcorner analysis, quite well justify the robustness ofthe design even at worst case process variations.Therefore, the proposed 5T SRAM cell design wouldbe suitable for various high speed and low powerembedded cache, stand-alone IC, and networkapplications.REFERENCES[1] A. Agarwal, C. H. Kim, S. Mukhopadhyay,and K. Roy, “Leakage in Nano-ScaleTechnologies: Mechanisms, Impact andDesign Considerations,” Proc. of the 41stDesign Automation Conference (DAC04),June 2004, pp. 6-11.[2] S. Mukhopadhyay, H. Mahmoodi,and K.Roy, “Modeling of Failure Probability andStatistical Design of SRAM Array for YieldEnhancement in Nanoscaled CMOS,” IEEETrans. on Computer- Aided DesignofIntegrated Circuits and Systems, Vol. 24, no.12, p.p 1859-1880,December 2005.[3] Debasis Mukherjee, Hemanta Kr. Mondal,and B.V.R. Reddy, “Static Noise MarginAnalysis of SRAM Cell for High SpeedApplication,” IJCSI International Journal ofComputer Science Issues, Vol. 7, Issue5,September 2010.[4] Michael Wieckowski, Martin Margala, “Anovel five-transistor (5T) SRAM cell forhigh performance cache,” Proc. of the IEEEInternational SOCConference, Dec 2005,pp.101-102.[5] David A. Hodges, Horace G. Jackson, ResveA. Saleh, Analysis anddesign of digitalintegrated circuits: In Deep SubmicronTechnology,McGraw-Hill Edition, 2004.,vol. sc-22, no. 5, October 1987.