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Nocs performance improvement using parallel transmission through wireless links
Nocs performance improvement using parallel transmission through wireless links
Nocs performance improvement using parallel transmission through wireless links
Nocs performance improvement using parallel transmission through wireless links
Nocs performance improvement using parallel transmission through wireless links
Nocs performance improvement using parallel transmission through wireless links
Nocs performance improvement using parallel transmission through wireless links
Nocs performance improvement using parallel transmission through wireless links
Nocs performance improvement using parallel transmission through wireless links
Nocs performance improvement using parallel transmission through wireless links
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Nocs performance improvement using parallel transmission through wireless links

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The Network-on-Chip (NoC) is a solution for integrating high numbers of cores on a single chip. The …

The Network-on-Chip (NoC) is a solution for integrating high numbers of cores on a single chip. The
integration of high number of cores especially on the mesh topology causes long diameter, which, in
turn, affects the network performance due to an increase in average hop count. Hence, other solutions
like long range links have been proposed to decrease average hop count. These links can be
implemented by new technologies such as high bandwidth on-chip wireless connection to decrease
latency. On-chip wireless links prepare high bandwidth interconnections using carbon nanotube
antennas. Wireless links bandwidth is higher than wire links;hence for handling bandwidth
incompatibility a new transmission rule is needed. In this paper, a method for transmitting/receiving
flits through the wireless links in a parallel manner is initially presented. Then, a parallel buffer
structure to store flits from wireless links is introduced. Finally, we demonstrate the advantages of the
proposed methodusing energy and latency analysis. Simulation results show that energy is saved
around 30% on the all-to-all traffic and 15% on the transpose traffic. Network latency as a function of
the packet injection rate can be improved on the all-to-all and transpose traffics around 71% and 19%,
respectively

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  • 1. International Journal on Computational Sciences & Applications (IJCSA) Vol.4, No.3, June 2014 DOI:10.5121/ijcsa.2014.4305 51 NOCS PERFORMANCE IMPROVEMENT USING PARALLEL TRANSMISSION THROUGH WIRELESS LINKS Shokoofeh Bakhtiari1 and Midia Reshadi2 1 Student member, Department of Computer, Science and Research Branch Islamic Azad University, Tehran, Iran 2Department of Computer, Science and Research Branch Islamic Azad University, Tehran, Iran Abstract The Network-on-Chip (NoC) is a solution for integrating high numbers of cores on a single chip. The integration of high number of cores especially on the mesh topology causes long diameter, which, in turn, affects the network performance due to an increase in average hop count. Hence, other solutions like long range links have been proposed to decrease average hop count. These links can be implemented by new technologies such as high bandwidth on-chip wireless connection to decrease latency. On-chip wireless links prepare high bandwidth interconnections using carbon nanotube antennas. Wireless links bandwidth is higher than wire links;hence for handling bandwidth incompatibility a new transmission rule is needed. In this paper, a method for transmitting/receiving flits through the wireless links in a parallel manner is initially presented. Then, a parallel buffer structure to store flits from wireless links is introduced. Finally, we demonstrate the advantages of the proposed methodusing energy and latency analysis. Simulation results show that energy is saved around 30% on the all-to-all traffic and 15% on the transpose traffic. Network latency as a function of the packet injection rate can be improved on the all-to-all and transpose traffics around 71% and 19%, respectively. Keywords network-on-chip, wireless interconnect, on-chip antenna, parallel buffer, parallel transmission 1. Introduction The Network-on-Chip (NoC) is known as a solution that creates a high degree of integration on a chip.1 The traditional NoCs that use metal/dielectric planar suffer from additional network latency and power consumption due to multi hop communications. To tackle these problems, some alternative solutions such as inserting long range links2 , 3D NoCs3,4,5 ,on-chip optical interconnects6 , RF interconnect transmission lines7 , CMOS Ultra-Wide Band (UWB) wireless interconnect technology8 and hybrid wire/wirelesstopology using the partitioning technique have been proposed.9 The basic idea behind these solutions is to decrease power consumption and latency by incrementing connectivity and using new technologies. Wireless links achieve high bandwidth using carbon nanotube antennas10 in Thz/optical
  • 2. International Journal on Computational Sciences & Applications (IJCSA) Vol.4, No.3, June 2014 52 frequency.These antennas as on-chip antennas are considered for establishing awireless link.Wireless bandwidth is more considerable than a wire link. Where only one data unit can be sent or received per clock, wireless bandwidth incompatibility appears.In this paper, an approach is proposed for using the wireless interconnect bandwidthon a hybrid wire/wireless topology thatimproves energy consumption and average network latency.Latency is defined as the time (in clock cycles) that elapses between injecting a message header into the network at the source node and the receiving a tail flit at the destination node.11 The proposed approach offers a solution to adjustdifferent interconnectbandwidth on the hybrid topologies bytransferringpacketsin a parallel manner.In wormhole switching each packet is divided to minimal data units named flits, so storing whole packet in each node does not necessary and flits are transferred in pipeline manner. Therefore, the size of each buffer and delivery latency is reduced. A packet usually includes one header, some body and one tail flits. Header and tail flits include specific control bits to reserved and release the path. The body flits consist of data units should be received in destination node. The parallel transfer needs pushing and popping flits that has similar output at the same time. To achieve this goal, a parallel buffer is proposed as a storing memory. The remaining of this paper is structured as follows.Section 2reviews the relevant literature and presents similar works undertaken in this context. Section 3 is devoted to the WirelessNoCs (WNoCs) architecture and wireless links placements algorithm. Section4introduces the proposed approach. Experimental results and cost analysis are presented in Section 5. Finally,Section 6puts a conclusion on the findings ofthis paper. 2. Related works The Network-on-Chip has replaced conventional bus-based communication with private channels for integrating hundreds of cores on a single chip.1 According to the international technology road map for semiconductors (ITRS)12 , the properties of metal wires used on traditional NoCsdo not provide expected performance, hence new interconnect paradigms have been introduced.Inserting long range links improvesthe performance of 2D NoCs by decreasing average hop count, whichthis, in turn, causeslower power consumption and network latency.2 Pavlidis and Friedman proposed 3D NoCs to decrease average hop count and achieve high performance.3 Similarly, Optical NoCs6 , RF interconnect transmission lines7 and wireless interconnects8,9,13 have been introduced to improve power consumption and latency using new interconnect technologies. The advantages and disadvantages of these approaches are fully explained byRef. 14. Wireless interconnects are designed using antennas as transceivers and receivers. Before the current improvement on the characteristics of on-chip antennas which was made using carbon nanotube10 , mm-wave antennas were being used. The mm-wave antennas support tens of GHz bandwidth15 , 1-2 mm length and 10-15mm distance.16 Despite this, the use of carbon nanotube antennascan improve the advantages of wireless interconnects by supporting a higher data rate, For instance theycan achieve the 500 GHzbandwidth.17 As seen, the data transmission of carbon nanotube antennas can be five times greater than the mm-wave antennas. To improveWNoCs, the partitioning approach wasintroduced byRef. 18and 19in which the network is divided to small parts called subnets. Every subnethas an antenna for sending flits to other subnets if the hop count is reduced and congestion is not existed. In this regard, the partitioning system was also proposed through which nodes placed in a subnet use the upper layer with wireless links on nodes that called hub nodes to send flits to other subnets.9 On other wordsahierarchicalarchitecture was introduced for interconnecting subnets using hub nodes. A recursive structure named WCubewas introduced in Ref. 20 which centralizedthe wireless router equipped to multi receivers and one transmitter. This approach reduced20-45% of latency
  • 3. International Journal on Computational Sciences & Applications (IJCSA) Vol.4, No.3, June 2014 53 compared to the 2D wire mesh.Moreover,this idea in Ref. 21restricts maximum three hops using distributing receivers consisting of256 cores;this causes 2X power saving compared to Ref. 20. Some approaches use wireless links as data transmitter without any data wire links.Passing all data packets through RF nodes makes 65% latencyimprovement as explained in Ref. 8. Promises and challenges of related wireless backbone are discussed by Sujay Deb and etal.22 None of the introduced wireless infrastructures exhibit an idea to tackle bandwidth incompatibility problem. Our proposed approach using distributed antennas to aid hop countreduction can improve 71% latency and 19% energy dissipation. It alsoprovides a solution to handle hybrid network link bandwidth incompatibility. The WCube approach presented in Ref. 19 uses a table with one entry per destination but we consider the number of entries equal to mesh directions plus parallel flits count. This decreases the memory cost a lot as explained in Section 3.3. 3. WNoC Architecture and wireless linkslocations The 2D mesh topology (see Figure 1) is known as the most popular simple network.It is used because it has short channel length, low router complexity and high bisection bandwidth. We assume no partitioning method and virtual channel on this network. Fig 1. Mesh 4*4 topology; All nodes are connected via incoming and outgoing channels Wireless links should connect the routers which have high communication and multi hops distance to decrease power consumption and latency. Hence,the priority of links is calculatedas follows. = ∑ ( , − , ), ∈ × , (1) wherehopdefsrc,des and hopwssrc,des are the number of hops between the source and destination according to the routing algorithm. hopdef considers the default routing like XY routing and hopws uses the routing that appliesLong-Range links2 . Using this routing, a packet with the (x,y) coordinate is passed to the X axis until the x coordinate is equal to destination. After that, the packet is leaded to the Y axis until destination is reached. If a wireless link is found in the path that decreases hop counts, the packet uses the transfer antenna to truncate the path. Trafficsrc,des is defined as the number of traversal packets between source and destination. The wireless links placements algorithm is shown in Figure 2. The algorithm consumes a wireless link between a pair of source and destination which have more than one hop count. Then, the cost of wireless placement is calculated using Equation 1 in order to compare it with the previous link cost. The new placement and its cost are selected as an optimized option if it is greater than the
  • 4. International Journal on Computational Sciences & Applications (IJCSA) Vol.4, No.3, June 2014 54 previous one. Thefollowing algorithm is performed for all pairs of nodes. 1. L: wireless link 2. int Head; int Tail 3. While (count( L) != 0) 4. OptCost = -1; 5. For (j=0; j<count (nodes) ) 6. For(k=0; k<count(nodes) ) 7. If(nodej is not a neighbor of nodek ) 8. If( no wireless link between nodej&nodek ) 9. Consider L between nodej&nodek 10. Compute Cost 11. If (Cost >OptCost) 12. OptCost = Cost 13. Tail = k 14. Insert L between nodeHead&nodeTail 15. remove one L Fig 2. Wireless links placementsalgorithm 3.1. Parallel Flits transmission and reception As mentionedearlier, wireless links achieve high bandwidth using carbon nanotube antennas. One way to utilize wireless bandwidth is the use of parallel flits transmission by a merging operation. This operation appends some flits to send through a wireless link. Thus, packets are arrived faster to their destination because waiting for reservation is eliminated. Section 4.1 describes buffers architecture for wireless links to enable parallel transferring. Section 4.2 shows how flits are sent through a wireless link, Section 4.3 explains flit reception at the next hop and finally, Section 4.4 presents anequation to calculate the number of parallel flits. 3.2. Buffer Structure FIFO buffers are used to store flits of a packet, and reserved while a tail flit is received if wormhole switching is consumed. Therefore, wireless links (Wslink)that can carry more than one header need a specific buffer called the parallel buffer.Using this buffer, Wslink can be reserved for more than one packet. The input and output of mentioned buffers are depicted in Figure 3. As shown, a FIFO buffer has one input and output channel but a parallel buffer has parallel incoming and outgoing. Fig 3.Input and output of (a) FIFO buffer (b) Parallel buffer The parallel buffer structure, which uses the Mano`s registers design23 , is demonstrated in Figure 4.As seen, there are three levels of gates including ‘not’, ‘and’, and ‘or’ gates levels. If the arbitrator detects a new buffering request and a free buffer cell is existed, a positivesignal is passed from the first level to the second level gates for pushing the flit to that free cell. A negative signal from the arbitrator causesthe buffer keeps previous flits.
  • 5. International Journal on Computational Sciences & Applications (IJCSA) Vol.4, No.3, June 2014 55 Fig 4. Digital design of parallel buffer 3.3. Flits Transmission To send a packet, a header flit reserves the path by using a reservation table. As seen inFigure 5, outputs can be therefore reserved by the buffer index. The constant value (CV) of cells is defined for allocating to Wslinks.These cells are called Vpi (0≤i<CV). The index of buffers for a Wslink is greater than four because of the mesh topology structure. So, if two flits are to be sent through a wireless link at the same time, the 5th and 6th cells can be reserved. Fig 5.Reservation tableis used for sending a packet at each router.N, E, S, W and Ip symbols refer to North, East, South, West and local ports. Two cells are allocated to the wireless port,labeled as Ws1Vp1 and Ws1Vp2. If the output of arouted header flit was reserved by another header, the flit should wait except where the output is a Wslink. Wslinks can be reserved by CV flits, hence, ifVpiis reserved, Vpj can be reserved while j is less than CV. After the reservation step, flits are popped up and sent through outputs. For Wsflits (i.e. wireless flits), a merging operation for parallel transmission is required. As shown in Figure 6, a flit in the north buffer is popped up and pushed in to the first part of Wsflit with Vp0, then the south flit is marked as Vp1 and pushed in to the second part. The index of Vp iscalculated Equation 2. = − (2)
  • 6. International Journal on Computational Sciences & Applications (IJCSA) Vol.4, No.3, June 2014 56 wherei is the index of Vp, BufferIndex is the index of buffer and LinkNumberWS is the index of Wslink. Fig 6.The merging operation for parallel transmission overthe wireless link 3.4. Flits reception At the next hop, Wsflit is received and it should be split to push in to the parallel buffer. The buffer index cell that the flit with Vpiis pushed into is calculated by Equation 3. = + (3) wherei is the content of the Vp flag, BufferIndex is the index of buffer and LinkNumberWSis the index of Wslink that is greater than 4 because of other neighbors. 3.5. Optimizing cost value The CV should be defined as a proper value. If this value is small, congestion occurs and delay will be high. By increasing the number of CVs, latency decreases down to a threshold with expending memory cost. For cost reduction, the threshold value should be calculated to eliminate competition. Therefore, the number of Vpsis assumedequal to the flows that are received at the same time on the wireless node according to the routing algorithm. 4. Experimental Results The parallel transferring/receiving approachconsidering various numbers of Vpsis compared with the wired network using a cycle accurate System-Cbased simulator namedNoxim.The configuration parameters are listed in Table1.The Noxim simulator has been extended by the coding to support the proposed approach. The performance of the approach is evaluated in terms of latency (part 4.1) and power consumed (part 4.2). The place of the wireless link is determined by the cost equation whereall-to-all and transpose traffics are applied. All-to-all traffic is a uniform traffic that all nodes send a packet one to another. On the transpose traffic, the n*n mesh topology is considered as a matrix of the n size which nodei, has communicated with nodej,i where i and j indices are (X ,Y) dimensions. The routing algorithm is that used in Ref. 2
  • 7. International Journal on Computational Sciences & Applications (IJCSA) Vol.4, No.3, June 2014 57 . 4.1. Latency Inserting long range links decrease the hop count;soit is an alternative to reduce latency. If the long link is wired, only one flit can be transferred/received per clock. Using the mentioned approach in this paper, the number of transmission flits is increased up to Vps that effect on average clock reductionin order to receive packets. Thus, it is expected thatlatencydecreases than full wired mesh network. The results of average latencyconsidering all-to-all traffic on the 4*4 meshare shown in Figure 7 (a), where a wireless link is placed among the first and 14th nodes. It is clear that when Vp3 is used, the latencyis less than others. Because in this state the flows at the first node come from nodes of 0, 1, 2 and 3; so there are three flows at the same time on the first node from west, east and local ports. At the 14th node, the flows come from nodes of12, 13, 14 and 15.This simulation shows that latencyis improved by 71% if the number of Vps is carefully selected. If Vp2 is used the improvement is about 15% which is 56% less than Vp3.The same reason justifies that Vp1is not useful on the all-to-all traffic An additional evaluation on the 5*5 mesh with one Wslink from the second node to the 14th one is undertaken. In this case, only two flows at the head and tail of Wslinkarereceived at the same time. As shown in Figure 7(b), the best value for the number of Vps in this case is two and an additional Vpwould not improve latency. In this case,the latency is improved about 19% compared to the simple mesh. The improvement is about 6% by using Vp2. 4.2. Power Consumption Energy is consumed when a flit is received, transferred or routed. Hence, if the number of hops decreases, energy consumption is reduced too. Moreover, if the number of flits efforts for allocating output ports decrease, power is saved. Parallel transmission/reception decreases hop counts by the long range links idea, and competition by eliminatingthe limitation of blockingan output for one packet.The energy consumption in a wireless link was modeled inRef. 9where the longestWslinkwasconsidered 23mm.The plots of the total energy consumption on both traffics are shown in Figure 8. It is evident that energy is saved using a wireless link. The simple mesh power consumption (Ws less pillar) is 18% more than the proposed approach on all-to-all traffic. The improvement is about 12% when transpose traffic is considered having hotspots nodes. Table 1. Simulation parameters Parameters Value Simulation time 100000 cycles Warm up 10000 cycles Topology Mesh Routing algorithm Routing that is explained in Ref. 2 Virtual channel Zero Packet size 10 flit
  • 8. International Journal on Computational Sciences & Applications (IJCSA) Vol.4, No.3, June 2014 58 Fig 7. Average latency of (a) 16 nodes on the all-to-all traffic, (b) 25 nodes on the transpose traffic 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 6E-05 7E-05 8E-05 9E-05 0.0001 0.0002 0.0003 0.0004 Latency(cycle) injectionrate(flits/core/cycle) vp3 vp2 vp1 WS less 0 5 10 15 20 25 30 0.004 0.005 0.006 0.007 0.008 0.009 0.01 latency(cycle) injectionrate(flits/core/cycle) vp3 vp2 vp1 Ws less 0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 )j(energy injectionrate (flits/core/cycle) vp Ws less (a) (b) (a)
  • 9. International Journal on Computational Sciences & Applications (IJCSA) Vol.4, No.3, June 2014 59 Fig 8.Energy consumption on (a) all-to-all traffic(b) transpose traffic 5. Conclusion and Future Works In this paper, a parallel transferring/receiving approach was proposed to handle bandwidth incompatibility of wire and wireless links on hybrid topologies.Carbon nanotube antennas can support 500 GHZ bandwidth on a wireless link. The placement of these antennas decreased hop counts that, in turn, it would impact on latency and power dissipation. An algorithm was presented to consider wireless links according to traffic and distance between nodes Wire link bandwidth is limited to carry one flit per clock; so flits are challenged to reserve a path at the next hop. The proposed approach merges competitor flits and makes a bigger flit to transfer through a wireless link per clock. The parallel transmission idea reminds additional ports at one direction. Therefore, a wireless link is assumed to some virtual ports that are called Vps. Vps are indexed for splitting flits to send via wire links at the next hop.A parallel transmission/reception idea needs a buffer which is able to push and pop a constant value (CV) of flits at the same time. The structure of the parallel buffer was also demonstrated. The CV was optimized by considering its value equal to the flows that were received at the same time on the wireless node. Improvements made on energy consumption and latency were also evaluated on all-to-all and transpose traffics. Simulation results showed that energy consumption was decreased around 30% and 15% on all-to-all and transpose traffics, respectively. Network latency as a function of the packet injection rate was improved 71% on the all-to-all and around 19% on transpose traffic. As a future work, a partitioning approach can be studied in order to improve wireless usage by using antennas as a bridge between partitions.This implies thatthe improvement of the proposed approach is unfolded via the number of parallel transmission flits growth. In response to this limitation, a routing algorithm can be expressed for leading flits to wireless nodes and decreasing hop counts. Further, a wireless link placement algorithm is going to improve for supporting unpredictable traffics. The related works will synthesize and compare with the proposed approach to handle bandwidth incompatibility. 6. References [1] L. Benini, G. D. Micheli, Networks on Chips: A New SoC Paradigm, IEEE Computer, 35(2002),70- 78. [2] U. Y. Ogras, R. Marculescu, it’s a small world after all: NoC performance optimization via long-range link insertion, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(2006), 693– 706. [3] V. F. Pavlidis, E. G. Friedman, 3-D Topologies for Networks-on-Chip, IEEE Transactions on Very 0 0.00005 0.0001 0.00015 0.0002 0.00025 0.0003 0.00035 0.0004 0.00045 0.0005 0.004 0.005 0.006 0.007 0.008 0.009 0.01 )j(energy injectionrate(flits/core/cycle) vp ws less (b)
  • 10. International Journal on Computational Sciences & Applications (IJCSA) Vol.4, No.3, June 2014 60 Large Scale Integration (VLSI), 15(2007), 1081-1090. [4] B. Feero, P. P. Pande, Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation,IEEETransactions on Computers, 58(2009), 32-45. [5] D. Park, et al., MIRA: A Multi-layered On-Chip Interconnect Router Architecture, IEEE International Symposium on Computer Architecture, 2008, 251-261. [6] A. Shacham, et al., Photonic Network-on-Chip for Future Generations of Chip Multi-Processors, IEEE Transactions on Computers,57(2008), 1246-1260. [7] M. F. Chang, et al., CMP Network-on-Chip Overlaid with Multi-Band RF-Interconnect, IEEE 14th International Symposium on high performance computer architecture, 2008, 191-202. [8] D. Zhao, Y. Wang, SD-MAC: Design and synthesis of a hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip, IEEE Transactions on Computers,57(2008), 1230–1245. [9] AmlanGanguly, Kevin Chang, et al., Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-Core Systems, IEEE transactions on computers, 60(2010), 1485-1502. [10] K. Kempa, et al., Carbon Nanotubes as Optical Antennae, Advanced Materials, 19(2007), 421-426. [11] P.P. Pande, C. Grecu, A. Ivanov, and R. Saleh, Design of a Switch for Network on Chip Applications, Proc. Int’l Symp. Circuits and Systems (ISCAS), 5(2003), 217-220. [12] ITRS, http://www.itrs.net/Links/2007ITRS/Home2007.htm, 2007. [13] K. Kim, H. Yoon, K. O.,On-chip wireless interconnection with integrated antennas, Electron Devices Meeting , 2000, 485 –488. [14] Luca P. Carloni, ParthaPande, Yuan Xie, Networks-on-Chip in Emerging Interconnect Paradigms: Advantages and Challenges, 3rd ACM/IEEE International Symposium, 2009, 93-102. [15] Y. Huang, W. Y. Yin, Q. H. Liu, Performance prediction of carbon nanotube bundle dipole antennas, IEEE Transactions on Nanotechnology,7(2008), 331–337. [16] J. Lin, et al., Communication Using Antennas Fabricated in Silicon Integrated Circuits, IEEE Journal of Solid-State Circuits,42(2007), 1678-1687. [17] P. J. Burke, et al., Quantitative Theory of Nanowire and Nanotube Antenna Performance, IEEE Transactions on Nanotechnology, 5(2006), 314-334. [18] Wen-Hsiang Hu, Chifeng Wang, Nader Bagherzadeh, Design and Analysis of a Mesh-based Wireless Network-on-Chip, 20th Euromicro International Conference on Parallel, Distributed and Network- based Processing, 2012, 483-490. [19] Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh, A Wireless Network-On-Chip Design for Multicore Platforms, 19th Euromicro International Conference on Parallel, Distributed and Network- based Processing, 2011, 409-416. [20] S. B. Lee et al., A scalable micro wireless interconnect structure for CMPs, in Proc. ACM Annu. Int. Con. Mobile Comput. Network, 2009, 20–25. [21] D. DiTomaso, et al., iWise: Inter-routerwireless scalable express channels for Network-on-Chips (NoCs) architecture, in Proc. Annu. Symp. High Performance Interconnects, 2011, 11–18. [22] Sujay Deb, AmlanGanguly, ParthaPratimPande, et al., Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges, IEEE Journalon Emerging and SelectedTopicsinCircuitsand Systems, 2(2012), 228-239. [23] M. Morris Mano, Michael D. Ciletti, Digital Design: With an Introduction to the Verilog HD(Prentice Hall, 2006).

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