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  1. 1. ISSN: 2277 – 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering Volume 1, Issue 5, July 2012Design of High Speed Six Transistor Full Adder using a Novel Two Transistor XOR Gates 1 Pakkiraiah Chakali, 2Adilakshmi Siliveru, 3Neelima KoppalaAbstract—In modern era, the number of transistors are To reduce the power and area requirements of thereduced in the circuit and ultra low power design have computational complexities, the size of transistors areemerged as an active research topic due to its various shrunk into the deep sub-micron region andapplications. A full adder is one of the essential component predominantly handled by process engineering. Manyin digital circuit design, many improvements have been made design architecture and techniques have been developedto reduce the architecture of a full adder.The main aim of this to reduce power dissipation complementary logic,paper is to reduce the power dissipation and area by redusing Pseudo NMOS[10], Dynamic CMOS[3], Clocked CMOSthe number of transistors.By using general logic of pmos logic (C2MOS), CMOS Domino logic[1], Cascadetransistor, the two transistor xor gate can be voltage switch logic (CVSL), Modified Domino logic,implemented. In this paper proposes the novel design of Pass Transistor Logic (PTL)[3] have been proposed.a 2T XOR gate. The design has been compared with Among the various building blocks in digital designsearlier proposed 3T, 4T and 6T XOR gates and a one of the most complex and power consuming is thesignificant improvement in silicon area and power-delay Adders. Although several Adder designs[14] have beenproduct has been obtained. An 8-T full adder has been proposed to reduce power consumption[12], they are notdesigned using the proposed 2-T XOR gate and its suitable for operation in the sub-threshold region. Inperformance has been obtained. the design is simulated addition these designs require a large number ofin Mentor graphics tool . transistors, resulting in a large area, not suitable for small, low-priced systems. The power consumption of aKeywords — XOR gate, full adder, speed, area, power CMOS circuit can be decomposed into two basicdissipation. classes: static and dynamic. I. INTRODUCTION The steady state power dissipation[12] of a circuit is expressed by the following relation Moore’s[17] law explains the requirement of thetransistors for VLSI design it gives the empirical P =I Vobservation that transistor density and performance of stat stat DD --------------(1)integrated circuits, doubles every year, which was thenrevised to doubling every two years[18]. Unfortunately, The dynamic[3] component of power dissipation issuch performance improvements have been due to its transient switching behavior of the CMOSaccompanied by an increase in power[2] and energy devicedissipation of the systems. Higher power and energy 2dissipation in high performance systems require more P = αCV f ……………..(2)expensive packaging and cooling technologies, increase dyn DDcost, and decrease system reliability. Nonetheless, thelevel of on-chip integration and clock frequency will This paper is organized as following. Section IIcontinue to grow with increasing performance demands, reviews previous work and implementation of 2T XORand the power and energy dissipation[13] of high- gate. Section III introduces implementation of fullperformance systems will be a critical design constraint. adder. Simulation and results are shown in Section IV, followed by the conclusion in Section V. Pakkiraiah Chakali, ECE Department, Sree VidyanikethanEgineering College (Autonomou), JNTUA, Anantapur.( II. DESIGN OF A TWO - TRANSISTOR XOR GATEPakkiraiah1988@yahoo.co.in). Tirupati, INDIA, Adilakshmi Siliveru, ECE Department, Sree VidyanikethanEgineering College (Autonomou), JNTUA, The circuit performance improvement in throughAnantapur.(adilakshmi458@gmail.com). Tirupati, INDIA, transistor count minimization.XOR gates form the Neelima Koppala, ECE Department, Sree Vidyanikethan fundamental building block of full adders. The earlyEgineering College (Autonomou), JNTUA, Anantapur.Tirupati, designs of XOR gates were based on either fourINDIA, Mobile No.09966547895(koppalaneelima@gmail.com). transistors[4] or three transistors[5] that are 104 All Rights Reserved © 2012 IJARCSEE
  2. 2. ISSN: 2277 – 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering Volume 1, Issue 5, July 2012conventionally used in most designs over the lastdecade.The previous designs of the four transistors andthree transistors are shown in figure1.The proposed twotransistor XOR gates can be designed using generallogic implementation. The design[15] of a two transistorXOR gate is shown in figure 2. The circuite operation is as follows when A=0 andB=0 both the pmos transistors are ON and it willproduce the output is low.when either one of thetransistor is ON it Produces output as high, when A=1and B=1 both the pmos transistors are OFF and it willproduce the output is low. Fig.2: Proposed Design of 2T -XOR. III. DESIGN OF THE SIX-TRANSISTOR FULL ADDER The new design of full adders[7][11] which forms the Fig.1(a) Fig.1(b) basic building blocks of all digital VLSI circuits has been undergoing a considerable improvement, being motivated by three basic design goals, viz. minimizing the transistor count, minimizing the power consumption and increasing the speed. Conventional Static[3] CMOS full adder: The conventional CMOS logic gate full adder[16] is shown as Fig. 2 while the equation of a full adder are present as equation(1) - (4) [7]. Fig.1(c) Fig.1(d) x + y + Cin =2Cout + Sum -------------------(3) Cout =(y(x ⊕ y)) + (Cin(x ⊕ y)) -----------(4) Sum = x ⊕ y ⊕ Cin -----------------------(5) The static CMOS Full adder is implemented by using 26 transistors.we can also minimize the number of Fig.1(e) transistors by using the CMOS Transmission gate and CMOS inverter.With this logic we reduce the number of Fig.1: Previous designs of 4-T and 3-T XOR gates. transistors to 20.By using Pass transistor logic we can minimize the static power dissipation and number of transistors.Full adder is design with 14 transistors[9] by using Pass transistor logic.which leads the moderate power dissipation.The full adder design also implemented by using 10 transistors[6]. 105 All Rights Reserved © 2012 IJARCSEE
  3. 3. ISSN: 2277 – 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering Volume 1, Issue 5, July 2012 Fig.3: Previous designs of 8T Full adder. Fig.5: Wave forms of 2T-XOR gate. [8] Mainly the XOR and XNOR circuits are used indesigning of full adder. In previous design the Fulladder is designed by using eight transistors.which candissipates more power compare to this work.In thispaper the design of full adder using two transistors xorgates can ge implemented.The Six transistor Full adderis shown in Figure.4. Fig.6: Wave form of 6T-Full adder The comparison of the different XOR gates and Full adders are shown in table.1 according to their transistor count and power dissipation. Table.1: Comparison of existed full adders with proposed one in terms of transistor count and power dissipation Fig.4: Proposed Design of 6T – Full adder Strucures No Power Transistors (μw) IV. RESULTS AND DISCUSSION XOR (Fig.1(a)) 4 0.499 The exclusive-or gate and full adder are operated at XOR(Fig.1(b)) 4 0.486100 MHz signal frequency. In fact, in addition to normal XOR(Fig.1(c)) 4 0.140transistors, circuits are tested in corner cases with fast XOR (Fig.1(d)) 4 0.434and slow transistors and their combinations too. The XOR (Fig.1(e)) 3 0.435difference in these stages is in consumption of power XOR (Fig.2) 2 0.135and falling and rising times which are caused due to the FULLADDER(Fig.3) 8 0.361difference in NMOS and PMOS transistors power FULLADDER(Fig.4) 6 0.235consumption and speed. After the simulation, the layoutof circuit is drawn. By the post simulation result alongwith a few corrections have achieved in sizes that the V. CONCLUSIONcircuit has an accurate operation. Simulation results areperformed by using digital schematic design tool of In this paper different CMOS logic design familiesMentor graphics tool. The waveforms of proposed has been reviewed and evaluated based on thedesign as shown in figure 5 and 6 for XOR gate and full performance metrics like area, power, delay andadder. transistor count. But the previous techniques have the disadvantages of transistor count, delay and power dissipation. The current work proposes the design of an 6T full adder, which is by far the full adder with the lowest transistor count. In designing the proposed 6T full adder, a novel 2T XOR gate has also been proposed. The implementation of Full Adder has been presented 106 All Rights Reserved © 2012 IJARCSEE
  4. 4. ISSN: 2277 – 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering Volume 1, Issue 5, July 2012and it can be extended to higher bit adders. The futureresearch activities may include integration of the [11] N. Zhuang and H. Wu, “A new design of theproposed full Adders in complex digital systems, CMOS full adder,” IEEE J.Solid-State Circuits,combining sequential and combinational logic. vol. 27, no. 5, May 1992, pp. 840–844. REFERENCES [12] E. Abu-Shama and M. Bayoumi, “A new cell for low power adders,” in Proc. Int. Midwest Symp.[1] M. Hosseinzadeh, S.J. Jassbi, and Keivan Navi, “A Circuits Syst., 1995, pp. 1014–1017. Novel Multiple Valued Logic OHRNS Modulo rn Adder Circuit”, International Journal of [13] J.F. Lin, Y.T.Hwang, M.H. Sheu, C.C. Ho, “A Electronics, Circuits and Systems, Vol. 1, No. 4, novel high speed and energy efficient 10 transistor Fall 2007, pp. 245-249. full adder design”, IEEE Trans. Circuits Syst. I, Regular papers, Vol. 54, No.5, May 2007, pp.[2] D. Radhakrishnan, “Low-voltage low-power CMOS 1050-1059. full adder,” in Proc.IEEE Circuits Devices Syst., vol. 148, Feb. 2001, pp. 19-24. [14] Y. Tsividis, Mixed Analog-Digital VLSI Devices and Technology, Singapore: McGraw Hill, 1st[3] Y. Leblebici, S.M. Kang, CMOS Digital Integrated edition, 1996. Circuits, Singapore: McGraw Hill, 2nd edition, 1999, Ch. 7. [15] M. Morris Mano, Digital Design, Prentice Hall of India, 2nd Edition, 2000.[4] J. Wang, S. Fang, and W. Feng, “New efficient designs for XOR and XNOR functions on the [16] S. Goel, M.A. Elgamel, M.A. Bayoumi, Y. Hanafy, transistor level,” IEEE J.Solid-State Circuits, vol. 29, “Design Methodologies for high performance noise no. 7, Jul. 1994, pp. 780–786. tolerant XOR-XNOR circuits”, IEEE Transactions on Circuits and Systems – I: Regular Papers, Vol.[5] H. T. Bui, A. K. Al-Sheraidah, and Y.Wang, “New 53, No. 4, 2006, pp. 867-878. 4-transistor XOR and XNOR designs,” in Proc. 2nd IEEE Asia Pacific Conf. ASICs, 2000, pp. 25–28. [17] Moore, Gordon E. (1965). "Cramming more components onto integrated circuits" (PDF).[6] H.T. Bui, Y. Wang, Y. Jiang , “Design and analysis Electronics Magazine. p. 4. Retrieved 2006-11-11. of 10-transistor full adders using novel XOR–XNOR gates,” in Proc. 5th Int. Conf. Signal Process., vol. [18] G. Moore, BNo exponential is forever: But 1, Aug. 21–25, 2000, pp. 619–622. Fforever_ can be delayed!’’ in Proc. IEEE Int. Solid-State Circuits Conf., 2003, Keynote address.[7] A. M. Shams, T. K. Darwish, and M. A. Bayoumi, “Performance analysis of low-power 1-bit CMOS full adder cells,” IEEE Trans. Very Large Scale Mr. Pakkiraiah Chakali completed his Integr. (VLSI) Syst., vol. 10, no. 1, Feb. 2002, pp. 0– B.Tech in Electronics and Communication 29. Engineering from Sreenivasa Institute of Technology and mamagement studies,[8] K.-H. Cheng and C.-S. Huang, “The novel efficient Chittoor, Andhra Pradesh, India in 2009. he is design of XOR/XNOR function for adder now pursuing his Master of Technology (M.Tech) in VLSI at Sree Vidyanikethan applications,” in Proc. IEEE Int. Conf. Elect., Engineering College , Tirupati, Andhra Circuits Syst., vol. 1, Sep. 5–8, 1999, pp. 29–32. Pradesh, India. His interest includes Digital Design, ASIC Design, VLSI Testing.[9] M. Vesterbacka, “A 14-transistor CMOS full adder with full voltage swing nodes,” in Proc. IEEE Ms. Adilakshmi Siliveru completed her Worksh. Signal Process. Syst., Oct. 20–22,1999, pp. B.Tech in Electronics and Communication 713–722. Engineering from Kandula Obula Reddy Memorial College Of Engineering, Kadapa,[10] R. Zimmermann and W. Fichtner, “Low-power Andhra Pradesh, India in 2011. She is now logic styles: CMOS versus pass-transistor logic,” pursuing her Master of Technology (M.Tech) IEEE J. Solid-State Circuits, vol. 32, July 1997, in VLSI at Sree Vidyanikethan Engineering pp.1079–90. College , Tirupati, Andhra Pradesh, India. Her interest includes Digital Design, VLSI Testing. 107 All Rights Reserved © 2012 IJARCSEE
  5. 5. ISSN: 2277 – 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering Volume 1, Issue 5, July 2012Ms. Neelima Koppala, M.Tech., is currentlyworking as an Assistant Professor in ECEdepartment of Sree VidyanikethanEngineering College, Tirupati. She hascompleted M.Tech in VLSI Design, fromSatyabhama University. Her research areas areRFIC Design, Digital Design, Low PowerVLSI Design and VLSI Signal Processing. 108 All Rights Reserved © 2012 IJARCSEE