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Low-jitter Differential Fanout Buffers - 8SLVP and 8SLVD Families from IDT
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Low-jitter Differential Fanout Buffers - 8SLVP and 8SLVD Families from IDT

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Overview of IDT's 8LSVP (LVPECL) and 8SLVD (LVDS) families of low-jitter fanout buffers from IDT. Fanout buffers are a useful building block of many clock trees, providing signal buffering and …

Overview of IDT's 8LSVP (LVPECL) and 8SLVD (LVDS) families of low-jitter fanout buffers from IDT. Fanout buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. IDT's high-performance, low additive phase noise, differential clock fan-out buffers offer up to 2 GHz clock operation, low additive phase jitter (12kHz - 20MHz) of 50 to 100 femtoseconds RMS max, fast output rise & fall times (less than 150 ps), and single and dual channel functions (dual: matched propagation delay). Presented by Baljit Chandhoke, Product Marketing Manager at Integrated Device Technology, Inc. To learn more about IDT's industry-leading portfolio of fanout buffers, visit www.idt.com/products/clocks-timing/clock-distribution.

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  • Clocks are the basic building blocks for all electronics today. Clock buffers are useful building blocks of clock trees because they are used to create multiple copies, multiply and divide clock frequencies. Since clocks are used to drive the processors and to synchronize the transfer of data between system components, the clock distribution system is an essential part of the system design. Identifying the correct clock buffer for a system is important.
    The IDT Buffer portfolio includes devices with up to 27 outputs and with Output dividers up to divide-by-32. Single-ended or differential outputs such as LVPECL, LVDS, HSTL, SSTL and CML are available. IDT’s extensive portfolio Differential output frequencies up to 3.2 GHz and single ended LVCMOS outputs for frequencies up to 350 MHz
  • Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP Family ideal for clock distribution applications demanding well-defined performance and repeatability.
  • The device is optimized for low power consumption, small output to output skew and propagation delay and low additive phase jitter.

Transcript

  • 1. High Performance Low Additive Phase Noise, Differential Clock Fan-out Buffers IDT 8SLVP Family of LVPECL Buffers and IDT 8SLVD Family of LVDS Buffers Baljit Chandhoke Product Marketing Manager Integrated Device Technology ©2013 Integrated Device Technology, Inc.
  • 2. Fanout Buffers ● Fanout Buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal ● Buffers are useful for translating a clock from one signaling standard to another (e.g. LVCMOS-in to LVPECL-out) Benefits • Extremely low additive phase noise to drive jitter sensitive devices • Reduction in Board Space with reduced BOM www.IDT.co PAGE 2
  • 3. Key Applications and Customer Needs KEY APPLICATIONS ● Networking ● Computing ● Base Stations ● High-end consumer ● Industrial ● Communications ● Instrumentation APPLICATION ISSUES SOLVED ● Clock Fan-out to reduce BOM and Board space ● Frequency synchronized clock outputs to the same clock input reference ● Low output to output skew between clock outputs ● Low propagation delay between input and output clock ● Low additive clock jitter at the output clock www.IDT.co PAGE 3
  • 4. 8SLVP Family of LVPECL Fan-out Buffer Overview High-performance differential LVPECL fan-out buffer family with best in class very low additive phase-jitter ● Characterized to operate from a 3.3V and 2.5V power supply ● Guaranteed output-to-output and part-to-part skew characteristics ● 8SLVP1208I www.IDT.co PAGE 4
  • 5. 8SLVP Family of LVPECL Fan-out Buffer Overview Features ● Low skew, low additive jitter LVPECL output pairs ● Two selectable, differential clock input pairs ● Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML ● Maximum ● Output input clock frequency: 2GHz skew: 28ps (typical) ● Propagation delay: 410ps (maximum) ● Low additive phase jitter, RMS: 54.1fs (maximum) ● 3.3V and 2.5V supply voltage ● -40°C www.IDT.co 8SLVP1208I to 85°C ambient operating temperature PAGE 5
  • 6. IDT8SLVP (LVPECL) Buffer Devices 8SLVP1102I 8SLVP2102I 8SLVP1204I 8SLVP1104I 8SLVP2104I 8SLVP1208 I 8SLVP2108 I 8SLVP2106 I 1:2 Fanout Dual 1:2 Fanout 1:4 Fanout -Dual in: 1204 -Single in: 1104 Dual 1:4 Fanout 1:8 Fanout Dual 1:8 Fanout 1:6 Fanout 1:12 Fanout In Production In Production In Production In Production In Production In Production In Production In Production • • • • Up to 2 GHz clock operation Low additive phase jitter (12 KHz – 20 MHz): 50-100 fs RMS max Fast output rise & fall time (<150 ps) Single and dual channel functions (dual: matched propagation delay) www.IDT.co PAGE 6 8SLVP121 2i
  • 7. 8SLVD Family of LVDS Fan-out Buffer Overview IDT8SLVD Family is a high-performance differential LVDS fan-out buffer family with best in class very low additive phase-jitter. Features ● Low skew, low additive jitter LVDS output pairs ● Two selectable differential clock input pairs Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL ● ● Maximum input clock frequency: 2GHz ● Output skew: 20ps (maximum) ● Propagation delay: 300ps (maximum) ● Low additive phase jitter, RMS: 95 fs (maximum) ● 2.5V supply voltage ● -40°C to 85°C ambient operating temperature www.IDT.co VersaClock 3 PAGE 7 8SLVD1204I
  • 8. IDT8SLVD (LVDS) Buffer Family 8SLVD1102I 8SLVD2102I 1:2 Fanout Dual 1:2 Fanout Samples Now Samples Now 8SLVD1204I 8SLVD2104 I 8SLVD1208 I 8SLVD2108I 8SLVD2106I 8SLVD121 2I 1:4 Fanout Dual 1:4 Fanout 1:8 Fanout Dual 1:8 Fanout Dual 1:6 Fanout 1:12 Fanout In Production Samples Q4 2013 Samples Q4 2013 Samples Q4 2013 Samples Q4 2013 Samples Q4 2013 8SLVD1204I-33 (3.3V): Samples Q4 2013 8SLVD1208I33 (3.3V): Samples Q4 • Low additive phase jitter (12 KHz – 20 MHz): 50-100 fs RMS max • Fast output rise & fall time • 2.5V voltage supply • Selected devices with 3.3V supply www.IDT.co PAGE 8
  • 9. Summary ● IDT8SLVP and IDT8SLVD Family is a high-performance differential LVPECL and LVDS fan-out buffer family with best in class ● ● ● ● ● ● Low Additive Clock Jitter Low Power Consumption Small Propagation Delay Low output to output Skew Fast Rise Time/ Fall Time Extensive portfolio with single channel and dual channel LVPECL and LVDS fan-out buffers from 2 outputs to 12 outputs www.IDT.co PAGE 9
  • 10. Support and More Information COMPLETE PRODUCT SUPPORT ● Datasheets ●Timing Solutions Book on IDT website ●Fan-out Buffer flyer on IDT website ●IDT has the largest portfolio of Fan-out Buffers with over 400 Devices ●IDT ● ● ● ● is committed to helping our customers with: Schematic Reviews of their board design IBIS or HSpice Models for Signal Integrity simulations Well established network of FAEs in all Geographies Application Notes on topics: • Layout Guidelines • Crystal Selection • Power Supply Filtering • Termination Schemes www.idt.com/products/clocks-timing/clock-distribution Email: clocks@idt.com www.idt.com/go/sales www.IDT.co PAGE 10
  • 11. Transcript ● Hello. My name is Baljit Chandhoke and I'm the product marketing manager of clocking products at IDT. Today, I'll be giving you a brief overview of high performance differential clock fanout buffer family IDT 8SLVP family of LVPECL Buffers and IDT 8SLVD family of LVDS Buffers. ● Clocks are the basic building blocks for all electronics today. Clock buffers are useful building block of clock trees because they're used to create multiple copies of the input clocks. Since clocks are used to drive processors and to synchronize the transfer of data between system components, the clock distribution system is an essential part of the system design. Hence, identifying the correct clock buffer for a system is extremely important. The key benefits of clock buffers are extreme low additive phase noise to drive jitter sensitive devices. Reduction in board space with reduced bill of material. ● Key application of clock buffers: networking, computing, base stations, high end consumer, industrial communications, and instrumentation. Application issues solved by clock buffers: clock fanout to reduce bulk bill of material and board space. Fanout buffers enable frequency synchronized clock outputs to the same clock input reference. Fanout buffers enable low output to output skew between clock outputs. Low propagation delay between input and output clock. Low additive clock jitter at the output clock. ● Now I'll talk about the 8SLVP family of LVPECL clock fanout buffers. These are high performance differential LVPECL clock fanout buffers with best in class extremely low additive phase-jitter. They are characterized to operate with a power supply of 3.3 volts and 2.5 volts. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP family ideal for clock distribution applications demanding to modeling well-defined performance and repeatability. ● The features of 8SLVP family of LVPECL fanout buffers are two selectable differential clock inputs which can accept LVPECL, LVDS or CML inputs. Output skew of 28ps. Propagation delay, 410ps. Low additive phase jitter with a RMS phase jitter of 54.1fs maximum. The device operates with a 3.3 volt and 2.5 volt power supply and operating temperature range of minus 40 degrees Celsius to 85 degrees Celsius. ● IDT8SLVP family of LVPECL buffers is offered in different output configurations, with one to two fanouts to one to 12 fanouts. Dual channel options are available with dual one to four fanouts, dual one to eight fanouts. All these devices can operate with an input frequency up to 2 GHz with extremely low additive phase jitter of 50 to 100 fs RMS max. This device family has extremely fast output rise and fall time, with less than 150ps. ● Now I'm going to talk about the 8SLVD family of LVDS fanout buffers. This family has optimized for low power consumption small output to output skew and propagation delay and best in class very low additive phase jitter. The key features of this family are two selectable clock inputs which can accept LVPECL or LVDS inputs. Maximum input clock frequency up to 2 GHz. Output skew 20ps max. Propagation delay 300ps. Low additive phase jitter, 95fs. This device family operates with a 2.5 volt supply voltage with some devices being offered with 3.3 volt power supply as well. ● This slide shows you the family of devices. We offer LVDS fanout buffers with one to two fanout, dual channel one to two, one to four fanout. Dual channel one to four all the way up to one to 12 fanout buffers, with extremely low additive phase jitter, between 50 and 100fs. ● In summary 8SLVP and 8SLVD family is a high performance differential LVPECL and LVDS fanout buffer family from IDT with best in class low additive clock jitter with 50 to 100fs RMS max. Low power consumption, small propagation delay, low output to output skew, fast rise time and fall time. IDT offers an extensive portfolio of single channel and dual channel LVPECL and LVDS fanout buffers from two outputs to 12 outputs. ● We provide a complete product support with datasheets, timing solutions book, fanout buffer flyers on IDT website. In addition to the 8SLVP and 8SLVD family of fanout buffers we have the largest portfolio of fanout buffers with over 400 devices. IDT is committed to helping our customers with schematic reviews, IBIS or HSpice Models, well-established networks of FAEs in all geographies. Application notes on topics, layout guidelines, crystal selections, power supply filtering. For more information you can contact the link shown. Thank you for your time. www.IDT.co PAGE 11