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This paper presents a multiplier less approach
to implement high speed and area efficient decimator for
down converter of Software Defined Radios. This
technique substitutes multiplyandaccumulate (MAC)
operations with look up table (LUT) accesses. Proposed
decimator has been implemented using Partitioned
distributed arithmetic look up table (DALUT) algorithm
by taking optimal advantage of embedded LUTs of target
FPGA device. This method is useful to enhance the system
performance in terms of speed and area. The proposed
decimator has used half band polyphase decomposition
FIR structure. The decimator has been designed with
Matlab 7.6, simulated with Modelsim 6.3XE simulator,
synthesized with Xilinx Synthesis Tool (XST) 10.1 and
implemented on Spartan3E based 3s500efg3204 FPGA
device. The proposed DALUT approach has shown an
improvement of 24% in speed by saving almost 50%
resources of target device as compared to MAC based
approach.
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