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The phase frequency detector has been designed for
high frequency phase locked loop in 180 nm CMOS Technology
with 1.8V supply voltage using CADENCE Spectre tool. A
Virtuoso Analog Design Environment and Virtuoso LayoutXL
tools of Cadence have used to design and simulate schematic
and layout of phase frequency detector respectively.
Architecture of phase frequency detector (PFD) has simulated
to get low dead zone and low power consumption. A layout has
designed by above tool and DRC by Assura. This circuit has
designed with low power dissipation and small area .The total
area required without pad is 0.06988 mm2 and current
consumption is found to be 132.6 uA respectively.