ACEEE Int. J. on Communication, Vol. 02, No. 03, Nov 2011     An Area Efficient, High Performance, Low Dead    Zone, Phase...
ACEEE Int. J. on Communication, Vol. 02, No. 03, Nov 2011The delay time of logic components and reset time of feedback    ...
ACEEE Int. J. on Communication, Vol. 02, No. 03, Nov 2011                                                                 ...
ACEEE Int. J. on Communication, Vol. 02, No. 03, Nov 2011                 Prof. R. H Talwekar received the BE, ME degree i...
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An Area Efficient, High Performance, Low Dead Zone, Phase Frequency Detector in 180 nm CMOS Technology for Phase Locked Loop System

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The phase frequency detector has been designed for
high frequency phase locked loop in 180 nm CMOS Technology
with 1.8V supply voltage using CADENCE Spectre tool. A
Virtuoso Analog Design Environment and Virtuoso LayoutXL
tools of Cadence have used to design and simulate schematic
and layout of phase frequency detector respectively.
Architecture of phase frequency detector (PFD) has simulated
to get low dead zone and low power consumption. A layout has
designed by above tool and DRC by Assura. This circuit has
designed with low power dissipation and small area .The total
area required without pad is 0.06988 mm2 and current
consumption is found to be 132.6 uA respectively.

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An Area Efficient, High Performance, Low Dead Zone, Phase Frequency Detector in 180 nm CMOS Technology for Phase Locked Loop System

  1. 1. ACEEE Int. J. on Communication, Vol. 02, No. 03, Nov 2011 An Area Efficient, High Performance, Low Dead Zone, Phase Frequency Detector in 180 nm CMOS Technology for Phase Locked Loop System R. H. Talwekar, Dr. S. S. Limaye Department of Electronics & Telecommunication 1 Disha Institute of Management and Technology, Raipur (CG) 2 Jhulelal Institute of Technology, Nagpur (MS) ur_talwekar@yahoo.com, shyam_limaye@hotmail.comAbstract: The phase frequency detector has been designed forhigh frequency phase locked loop in 180 nm CMOS Technologywith 1.8V supply voltage using CADENCE Spectre tool. AVirtuoso Analog Design Environment and Virtuoso LayoutXLtools of Cadence have used to design and simulate schematicand layout of phase frequency detector respectively.Architecture of phase frequency detector (PFD) has simulatedto get low dead zone and low power consumption. A layout hasdesigned by above tool and DRC by Assura. This circuit hasdesigned with low power dissipation and small area .The totalarea required without pad is 0.06988 mm2 and current Figure 1. PLL Architectureconsumption is found to be 132.6 uA respectively. II. PFD ARCHITECTUREIndex terms: Phase locked loop (PLL), Phase frequency detector(PFD), Charge pump (CP), Voltage controlled oscillator (VCO), The traditional design consists of two D flip-flops and aDead Zone, Low pass filter (LPF), and D flip flop (DFF). NOR gate in the reset path to reset both the flip flop. The proposed schematic of the D flip flop (DFF) is shown in figure I. INTRODUCTION 3.The undetectable small phase range called as dead zone influences the effective sensitivity of a PFD.To minimize the A PFD can detect the smallest phase difference of refer- power consumption of the PFD, it is must to reduce the resetence signal and output signal of VCO, because of this char- path delay so that dead zone can be minimized. In order toacteristic of the PFD it can be used as one of the important avoid dead-zone a useful equation for the minimum resetpart of a PLL. The PLL consist of a PFD, LPF, CP and VCO. delay of the PFD is given by equ.1.The PLL based on CP which is shown in figure 1 has been Treset =Tth = (Tr +Tf) /2 - - - - - - - - - - - - - (1);used because of its wide capture range and no phase offset.The operation of this circuit is basically a feedback control Where Tth is the CP switching time and can be approximatedsystem that controls the phase of a VCO. The input signal is by the average of the rise time Tr and the fall time Tf .To avoidapplied to one input of a phase frequency detector. The other a dead zone the minimum delay in the PFD reset path is Tresetinput is taken from the divide by N counter.Now a day’s PLLs = Tth and the maximum delay in the PFD reset path is theare widely used in microprocessors and digital systems for maximum operating frequency of the PFD [3].The main reasonclock generation and as a frequency synthesizer in commu- of creation of static error at the output of the PLL is the longnication systems for clock extraction and generation of a low reset pulse which reduces the operating frequency of thephase noise local oscillator. The phase difference between PFD and the additional charges which are fed to the chargetwo input signals, i.e. the reference signal and the VCO out- pump [4].The aim of this design is to reduce size and dead-put signal, can be processed by the PFD which is shown in zone because sensitivity of circuit is inversely proportionalfigure 2 for getting the phase error relative to the input and to the value of dead-zone [5].When delay time and reset timereference frequency. After detecting the phase error in terms are large, a PFD cannot detect small phase error.of voltage, PFD can generate two signals named as UP andDN, which are connected to the charge pump circuit [1]. Theoutput voltage of CP is used to control the output frequencyof VCO. To tune according to output voltage of CP, the out-put value of PFD influences the output voltage of CP forVCO [2]. Figure 2. Block diagram of the PFD architecture© 2011 ACEEE 41DOI: 01.IJCOM.02.03.1
  2. 2. ACEEE Int. J. on Communication, Vol. 02, No. 03, Nov 2011The delay time of logic components and reset time of feedback to the stability of the loop is small [11].The divider logicpath of flip-flop causes a PFD to detect phase and frequency divides the VCO frequency and output of divider logic sentwith distortion [6]. to the phase frequency detector. The timing and phase of both can be compared by PFD and sent to CP which gives III. PROPOSED PFD ARCHITECTURE output in terms of a current pulse width which is equal to the amount of timing and phase error [12]. To achieve a high To design PFD, two D flip flops along with a AND gate speed PFD, it is modified and another design is proposedhave been used. When CLK and RST signals applied to DFF’s which is shown in figure 4, which depends on detecting theare at low level then drain node of NM4 (A) through pmos rising and falling edge of the input signals [13].The non ide-transistors PM4 and PM5 will be connected to VDD. alities in analog CMOS switches, such as charge injection and clock feed through periodically disturb the voltage on the LPF when it is off [14].In the PFD and CP circuits non- linearity is mainly caused by the mismatch between the up and down currents and the gain variation. A maximum opera- tion frequency is one over the shortest period with corrects UP and DN signals when the inputs have the same frequency and phase difference [15].Due to smaller node capacitances speed of the PFD increases. But due to finite delays of both D- flip flop and reset paths lead to a reduced linear range of its transfer characteristics. Therefore, it has high speed and Figure 3. Schematic design of the D flip-flop. fast acquisition [16].To implement higher speed PFD ,W/L ofAt the rising edge of the CLK, Node B(drain of NM5) will be all transistors have been changed to reduce the node capaci-connected to ground through nmos transistor NM5 and tances of transistors because the charge sharing phenom-NM6, because node ‘A’ is connected to VDD which turns off enon interchanges the control voltages of the PMOS transis-pmos transistor PM7.Node A will be connected to the ground tors [17].A proposed PFD generating the UP and DN pulsesthrough nmos transistor NM4, which leads to pull up node B according to the input applied to it .When CLK is appliedas RST signal charges up and it will become high due to with lagging to RST , number of UP pulses getting at theswitching ON of pmos transistor PM4.Transistor PM5 job is output of the PFD with lower width as compared to DN pulseto prevent a short circuit in the PM4, PM5 and NM4 path. width which is shown in Fig.5. However when CLK appliedWhen CLK is at low level and RST is at high level, a large to PFD is lagging, number of pulses of DN signal getting atcurrent w flows through this path. Therefore PM5 has been PFD with lower pulse width as compared to UP signal whichplaced there to prevent this current and lower the power is shown in figure 7.consumption of the D flip flop [7]. A AND gate has been usedinstead of NOR gate because NOR gate produces a large IV. RESULTdead zone. In both these cases, different clock input to DFF,the subsequent rising-edge of the CLK causes the DN signal The input clock frequency is 500 MHz with CLK leadingto lead the UP signal which causes a negative output in- RST by 4 ns this result in generation of an UP signal. Thecreasing the phase and frequency difference. These kinds of power consumption of the PFD is 2.08 mW @ 100 MHz whichmalfunctions seriously degrade the locking property in PLLs is a high value and that is due to the reset path that consumes[8].Such type of two DFFs are connected to implement a PFD some power to charge up and reset both flip-flops. Figure 5with a AND gate as shown in Fig 2.The flip-flops have the and figure 6 shows a simulation of PFD at 100 MHz and CLKsame design, one of them will control the UP output of the leading RST by 750 ps .The complete layout of the PFD isPFD and the other will control the DOWN(DN) output. figure shown in Figure 7. The dead zone of the PFD can be reduced3 shows schematic designs of the D flip flop. This type of to 3 ps and which is shown in figure 6 and 7.The total layoutrising edge detection connection for getting the phase de- area required for the PFD without pad is found to be is 0.06988tection scheme can be expanded further to reduce the bang- mm 2 and current consumption is found to be 132.6 uAbang jitter. Compared with the binary detector, one NMOS is respectively.additionally required to pull-down the reset path [9].The UPand DN signals are fed to the charge pump to provide thecontrol signal to VCO.A Large switch buffers are required inthe CP to degrade the circuit noise performance for which alarge transistors have been used.Large devices not only oc-cupy larger chip area, but also slow down the circuit tran-sient response [10].In order to increase the filtering effect forhigh-frequency and low-filter, a RC filter has been introduced.When RC filter pass band cut-off frequency is far greaterthan ten times of the loop bandwidth, impact of the RC filter Figure 4. Proposed PFD Architecture© 2011 ACEEE 42DOI: 01.IJCOM.02.03. 1
  3. 3. ACEEE Int. J. on Communication, Vol. 02, No. 03, Nov 2011 REFERENCES [1] N. H. E. Weste and K. Eshragrian, principles of CMOS VLSI Design, 2nd ed. MA Addison Wesley, 2001. [2] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. [3] Han-il Lee, Tae-won Ahn, Duck-young Jung and Byeong-ha Park,” Scheme for No Dead Zone, Fast PFD Design”, Journal of the Korean Physical Society, Vol. 40, No. 4, April 2002, pp. 543_545. [4] Lip-Kai Soh, Yew-Fatt Kok Edwin, “An Adjustable Reset Pulse Phase Frequency Detector for Phase Locked Loop” Altera Corporation, Penang, Malaysia, ©2009 IEEE 343 1st Int’l Symposium on Quality Electronic Design-Asia Figure 5. Output waveform of PFD when CLK is lagging [5] Bianchi, Giovanni. Phase-Locked Loop Synthesizer Simulation. McGraw-Hill, 2005. [6] Best, Roland E. Phase-Locked Loops Design, Simulation and Application. McGraw-Hill, 2003. [7] Stephens, D. “Phase-Locked Loops for Wireless Communications Digital and Analog Implementations” Kluwer Academic Puplishers, 1998. [8] Kun-Seok Lee*, Byeong-Ha Park, Han-il Lee, and Min Jong Yoh,” Phase Frequency Detectors for Fast Frequency Acquisition in Zero-dead-zone CPPLLs for Mobile communication Systems “ RF P/J, SYSTEM-LSI DIVISION, SAMSUNG ELECTRONICS, YONGIN, KYOUNGGI-DO, 449-711, KOREA. [9] Young-Sang KIM, Yunjae SUH, Hong-June PARK, Jae-Yoon ,”Deadzone-Minimized Systematic Offset-Free Phase Detectors,” SIM IEICE TRANS. ELECTRON., VOL.E91–C, NO.9 SEPTEMBER 2008,1525 LETTER. Figure 6. Output waveform of PFD with Dead Zone when CLK is [10] Ching-Lung Ti, Yao-Hong Liu and Tsung-Hsien Lin, “ A 2.4- leading GHz Fractional-N PLL with a PFD/CP Linearization and an Improved CP Circuit”, Graduate Institute of Electronics Engineering and Department of Electrical Engineering National Taiwan University [11] Sun Wenyou, Hu Yonghong,” Design and Realization of Direct PLL FM Transmitter for UAV Data Link”, 2009 WASE International Conference on Information Engineering [12] Xiang Gao, A. M. Klumperink, , Mounir Bohsali, and Bram Nauta, “A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied “ JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 12, DECEMBER 2009 3253 [13] K. H. Cheng, T. H. Yao, S . Y. Jiang and W. B. Yang, “A Difference Detector PFD for Low Jitter PLL,” Proceeding of the 8th IEEE Int. Conference on Circuits and Systems, vol. 1, pp. 43- 46, Sept. 2001. Figure 7. Layout of the PFD [14] Che-Fu Liang, Hsin-Hua Chen and Shen-Iuan Liu,” Spur- Suppression Techniques for Frequency Synthesizers”, IEEE V. CONCLUSION TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: The phase frequency detector has been designed to EXPRESS BRIEFS, VOL. 54, NO. 8, AUGUST 2007.implement the PLL at 2.4 GHz and simulated by Virtuoso [15] K. Arshak O. Abubaker E. Jafer,”Design and Simulation Difference Types CMOS Phase Frequency Detector for high speedCadence Spectre for low dead zone, small area and low power and low jitter PLL”, Proceedings of the Fifth IEEE Internationalconsumption. This circuit can be used in the application on Caracas Conference on Devices, Circuits and Systems, Dominicanhigh frequency, low dead zone and low power phase locked Republic, Nov.3-5, 2004.loop. [16] I Ahmed, R D Mason,”A DUAL EDGE-TRIGGERED PHASE-FREQUENCY DETECTOR ARCHITECTURES”, Department of Electronics, Carleton University, Ottawa, ON K1S 5B6, CANADA. [17] R. Y. Chen and W.-Y. Chen,”A High-speed Fast-acquisition CMOS Phase/Frequency Detector for MB-OFDM UW”, Manuscript received January 10, © 2007 IEEE.© 2011 ACEEE 43DOI: 01.IJCOM.02.03.1
  4. 4. ACEEE Int. J. on Communication, Vol. 02, No. 03, Nov 2011 Prof. R. H Talwekar received the BE, ME degree in Prof (Dr). S.S. Limaye received the BE and ME in Electronics Engg. from Nagpur and Pune University Electronics engineering from VNIT, Nagpur and in 1993 and 1997 respectively. He is currently a IIT Kharagpur, India in 1971 and 1973 respec- doctoral fellow at Nagpur University. Currently he tively. He received his PhD degree in Electronics is Associate professor of Electronics and Engineering from Nagpur University in 1997. He Telecommunication Deptt. at Disha Institute of worked for 15 years in industries and have beenManagement and Technology in Chhattisgarh Swami Vivekananda working in the field of teaching from last 21 years. Currently he isTechnical University, Bhilai, Chhattisgarh India. His research Principal at Jhulelal Institute of Technology in Nagpur University,interest fields are CMOS based analog mixed signal Design. Nagpur. His research interest fields are FPGA based system, and CMOS based wireless IC Design.© 2011 ACEEE 44DOI: 01.IJCOM.02.03.1

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