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### 36 sarang

1. 1. “Asymmetrical Cascaded H-Bridge Multilevel Inverter” Authors- Dr. S. S. Bharatkar Mr. R. R. Bhoyar Mr. S. A. Khadtare 1
2. 2. OUTLINE OF PRESENTATION Abstract  Introduction  Concept of CHB MLI  5-Level CHB MLI  7- Level Symmetrical CHB MLI  7- Level Asymmetrical CHB MLI  9- Level Asymmetrical CHB MLI  Result  Conclusion 2
3. 3. ABSTRACT The inverter can be categorized as two level conventional inverter and multilevel inverter (MLI). These two level (conventional) inverters have many drawbacks particularly for high voltage and high power applications.  The MLI is able to provide more number of levels in the output. The harmonics are greatly reduced with increase in levels and output voltage waveform approaches to sine wave.  The MLI requires more components to produce more number of levels in the output.  This paper deals with, the study of Asymmetrical configuration for seven level and nine level H-bridge multilevel inverter. The simulations for five level symmetrical, seven level symmetrical and asymmetrical and nine level asymmetrical configurations are carried out in MATLAB. It is observed that, asymmetric MLI has ability to provide more pure output without increasing the structure compared to symmetrical MLI. 3
4. 4. INTRODUCTIONINVERTER TWO LEVEL NCP MLI MULTILEVEL FLYING CAPACITOR MLI CHB MLI SYMMETRICAL CHB MLI ASYMMETRICAL CHB MLI 4
5. 5. Concept of CHB MLI- Fig. 1 Structure of m-cells cascaded multilevel inverter 5
6. 6. Fig. 2 H-bridge cell structure 6
7. 7. 5-LEVEL CHB MLIA S1 S3 B S9 Vdc Vdc C S11 S2 S12 S10 S5 S7 S13 S15 S6 S20 S18 S21 S23 S24 S22 Vdc Vdc S8 S19 Vdc S4 Vdc S17 S16 S14 7 N
8. 8. 7-LEVEL SYMMETRICAL CHB MLIA S1 S3 B S13 Vdc Vdc S4 S2 S5 S7 C S15 S25 S27 S28 S26 Vdc S16 S9 Vdc S6 S20 S18 S11 S21 S32 S30 S35 S36 S34 S23 Vdc S12 S31 Vdc Vdc S8 S19 S29 S33 Vdc S17 S14 S10 Vdc S24 S22 8 N
9. 9. 7-LEVEL ASYMMETRICAL CHB MLI- 9
10. 10. Fig. 3 Seven level Asymmetrical cascaded H-bridge MLI for 10 Phase A
11. 11. LEVELS SWITCHES 3Vdc S1, S5 2Vdc S1 Vdc S5 0 -Vdc S1, S3, S5, S7 (OFF) & S2, S4, S6, S8 (ON) S7 -2Vdc S3 -3Vdc S3, S7 11
12. 12. 9-LEVEL ASYMMETRICAL CHB MLI- 12
13. 13. 400 Result- For 5 level Inverter 300 Phase Voltage(Volts) 200 100 0 -100 -200 -300 -400 0 0.08 0.16 0.24 0.32 0.4 Time(Sec) 0.48 0.56 0.64 0.72 0.08 0.16 0.24 0.32 0.4 Time(Sec) 0.48 0.56 0.64 0.72 0.8 800 600 Line Voltage(Volts) 400 200 0 -200 -400 -600 -800 0 13 0.8
14. 14. 400 For 7- Level Symmetrical Inverter 300 Phase Voltage(Volts) 200 100 0 -100 -200 -300 -400 0 0.08 0.16 0.24 0.32 0.4 Time(Sec) 0.48 0.56 0.64 0.72 0.4 Time(Sec) 0.48 0.56 0.64 0.72 0.8 800 600 Line Voltage(Volts) 400 200 0 -200 -400 -600 -800 0 0.08 0.16 0.24 0.32 14 0.8
15. 15. For 7- Level Asymmetrical Inverter 400 300 Phase Voltage(Volts) 200 100 0 -100 -200 -300 -400 0 0.08 0.16 0.24 0.32 0.4 Time(Sec) 0.48 0.56 0.64 0.72 0.4 Time(Sec) 0.48 0.56 0.64 0.72 0.8 800 600 Line Voltage(Volts) 400 200 0 -200 -400 -600 -800 0 0.08 0.16 0.24 0.32 15 0.8
16. 16. For 9- Level Asymmetrical Inverter 400 300 Phase Voltage(Volts) 200 100 0 -100 -200 -300 -400 0 0.08 0.16 0.24 0.32 0.4 Time(Sec) 0.48 0.56 0.64 0.72 0.08 0.16 0.24 0.32 0.4 Time(Sec) 0.48 0.56 0.64 0.72 0.8 800 600 Line Voltage(Volts) 400 200 0 -200 -400 -600 -800 0 16 0.8
17. 17. THD and Vdc values for output line voltage of 400V TYPE VOLTAGE (volts) THD (%) 5-LEVEL SYMMECTRICAL 7-LEVEL SYMMETRICAL 163.5 17.12 109 10.63 7-LEVEL ASYMMETRICAL 109 10.63 9-LEVEL SYMMETRICAL 79 7.90 9-LEVEL ASYMMETRICAL 79 7.90 17
18. 18. COMPARISON OF MLIType of Inverter No. of Switches No. of DC Sources 5-level symmetrical 24 6 7-level symmetrical 36 9 9-level symmetrical 48 12 7-level Asymmetrical 24 6 9-level Asymmetrical 24 6 18
19. 19. CONCLUSIONFrom the simulation results it is concluded that, by taking different geometric progression factor the output levels of Asymmetrical MLI can be increased without any increased in components. So the output of ACMLI has very less amount of harmonic content i.e., the output is smoother. As compare to SCMLI, the numbers of bridges, DC sources required in ACMLI are less for attaining same number of levels. So the problem of requirement of more components to achieve more number of output levels are eliminated with proposed ACMLI topology. 19
20. 20. REFERENCES Mr. M.H. Rashid, "Power Electronics Circuit, Devices and Applications", 3rd edition, Pearson publication sou th Asia, 2007.  Mr. Bin Wu "High Power Converters & AC Drives" 2 nd edition, John Wiley publication, California, U.S.A., 2007.  Jannu Ramu, S.J.V. Prakash, K. Satya Srinivasu, R.N. D. Pattabhi Ram, M. Vishnu Prasad and Md. Mazhar Hussain, ''Comparison between Symmetrical and Asy mmetrical Single Phase Seven Level Cascade H-Bridg e Multilevel Inverter with PWM Topology", Internatio nal Journal of Multidisciplinary Sciences and Enginee ring, Vol. 3, No. 4, pp.16-20, April 2012. 20
21. 21.  F. Khoucha, M. S Lagoun, K. Marouani, A. Kheloui, and M.E.H. Benbouzid, “Hybrid cascaded H-bridge multilevel inverter induction motor drive direct torqu e control for automotive applications”, IEEE Trans. I nd. Electron., vol. 57, no.3, pp.892–899, Mar. 2010.  Farid Khoucha, Mouna Soumia Lagoun, Abdelaziz Kheloui, and Mohamed El Hachemi Benbouzid, "A Comparison of Symmetrical and Asymmetrical Thre e-Phase H-Bridge Multilevel Inverter for DTC Induc tion Motor Drives'', IEEE Trans. on Energy Conversi on, vol. 26, no. 1, pp.64-72, March 2011.  Hemant Joshi, P.N. Tekwani and Amar Hinduja, "Im plementation of A five-level Inverter using reversing voltage topology: A competitive solution for high-po wer IM drive applications", National power electroni cs conference 2010, pp.1-8, 2010. 21
22. 22.  Bindeshwar Singh, Nupur Mittal , Dr. K.S. Verma , D r. Deependra Singh, S.P.Singh, Rahul Dixit, Manvendr a Singh and Aanchal Baranwa, "Multi-level inverter: A literature survey on topologies and control strategies", International Journal of Reviews in Computing, Vol. 1 0, 31st July 2012.  K.Surya Suresh and M.Vishnu Prasad, "PV Cell Based Five Level Inverter Using Multicarrier PWM", Interna tional Journal of Modern Engineering Research (IJME R), Vol.1, Issue.2, pp-545-551.  Bipin Singh, K.P. Singh and A.N. Tiwari, ''Modeling of 5-Level Inverter Controlled with DVR Technique'', VSRD-IJEECE, Vol. 2 (1), pp.16-21, 2012. 22
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