Design of power efficient 4x4 array multiplier using adiabatic logic

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  • 1. International Journal of Electronics and Communication Engineering AND COMMUNICATION0976 – INTERNATIONAL JOURNAL OF ELECTRONICS & Technology (IJECET), ISSN 6464(Print), ISSN 0976 – 6472(Online) Volume & Issue 3, October- December (2012), © IAEME ENGINEERING 3, TECHNOLOGY (IJECET)ISSN 0976 – 6464(Print)ISSN 0976 – 6472(Online)Volume 3, Issue 3, October- December (2012), pp. 14-21 IJECET© IAEME: www.iaeme.com/ijecet.aspJournal Impact Factor (2012): 3.5930 (Calculated by GISI) ©IAEMEwww.jifactor.com DESIGN OF POWER EFFICIENT 4x4 ARRAY MULTIPLIER USING ADIABATIC LOGIC A.Andamuthu, Assistant Professor Muthayammal Engineering College,Tamilnadu,India. Email ID: andamuthuece@gmail.com R. Shankar, Assistant Professor Dept of ECE, Vidhya Mandhir Institute of Technology Erode, Email: sha8189@gmail.com J. Vinoth Kumar Assistant Professor Dept of ECE, J. J. College of Engineering and Technology Trichy, Email: vino.vinothkumar@gmail.com ABSTRACT The main process of this paper is to reduce the power in array multiplier using adiabatic logic. Adiabatic logic is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic logic is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. With the help of TSPICE simulations, the power consumption is analyzed by variation of parameter. In existing method, two logic families, 2N-2P logic and 2N-2N2P logic are compared with conventional CMOS logic for array multiplier circuits. In proposed method, 2N-2P logic is enhanced by adding pull down network and power clock to reduce the power consumption. It is find that adiabatic technique is good choice for low power application in specified frequency range. IndexTerms— Adiabatic logic, power dissipation, power clock I. INTRODUCTION Reducing power consumption has become an important issue in integrated circuit design owing to the strong demand for low power system-on-chip (SoC) and portable electronic 14
  • 2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEMEequipment [2].The energy dissipated in adiabatic circuits is considerably lesser than that in thestatic CMOS circuits, hence adiabatic circuits are promising candidates for low power circuitsthat can be operated in the frequency range in which signals are digitally processed. In this study,we compare the power consumption in Adiabatic CMOS logic circuits and conventional CMOScircuits. In most of the DSP system the multiplier is part of the critical path that determines theoverall performance of the system. That is why enhancing the performance of the 1-bit full-addercell (the building block of the binary adder) is a significant goal. Based on the full adder designcircuits, the multiplier was designed. Adiabatic logic circuits reduce the energy dissipationduring switching process, and reuse the some of energy by recycling from the load capacitance[4, 5]. For recycling, the adiabatic circuits use the constant current source power supply and forreduce dissipation it uses the trapezoidal [6] or sinusoidal power supply voltage [3].II. PRINCIPLES OF ADIABATIC LOGIC: The word ADIABATIC comes from a Greek word that is used to describethermodynamic processes that exchange no energy with the environment and therefore, noenergy loss in the form of dissipated heat. In real-life computing, such ideal process cannot beachieved because of the presence of dissipative elements like resistances in a circuit. However,one can achieve very low energy dissipation by slowing down the speed of operation and onlyswitching transistors under certain conditions. The signal energies stored in the circuitcapacitances are recycled instead, of being dissipated as heat. The adiabatic logic is also knownas ENERGY RECOVERY CMOS. In the adiabatic switching approach, the circuit energies areconserved rather than dissipated as heat. Depending on the application and the systemrequirements, this approach can sometimes be used to reduce the power dissipation of the digitalsystems.III. ADIABATIC LOGIC FAMILIES: Practical adiabatic families can be classified as either Partially adiabatic or fullyadiabatic. In partially adiabatic circuit, some charge is allowed to be transferred to the ground,while in fully adiabatic circuit all the charge on the load capacitance is recovered by the powersupply. Fully adiabatic circuits face so many problems with respect to operating speed and inputpower clock synchronization. Different logic families are 2N-2P Adiabatic logic, 2N- 2N2PAdiabatic Logic, Positive Feedback Adiabatic Logic (PFAL),NMOS Energy Recovery Logic(NERL), Clocked Adiabatic Logic (CAL),True Single-Phase Adiabatic Logic (TSEL),Source-coupled Adiabatic Logic (SCAL),Two phase adiabatic static CMOS logic(2PASCL) and fullyadiabatic logic families are ,Pass Transistor Adiabatic Logic (PAL),Split- Rail Charge RecoveryLogic (SCRL). In this project we are going with enhanced 2N-2P adiabatic logic familycompared with 2N-2P,2N-2N2P logic families and conventional cmos logic.IV.2N-2P ADIABATIC LOGIC FAMILY: The schematic and simulated waveform of the 2N-2P inverter gate is shown in Fig.2 andFig.3 respectively. Initially, input ‘in’ is high and input ‘/in’ is low. When power clock (pck)rises from zero to VDD, since F is on so output ‘out’ remains ground level. Output ‘/out’ follows 15
  • 3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEMEthe pck. When pck reaches at VDD, outputs ‘out’ and ‘/out’ hold logic value zero and VDDrespectively. This output values can be used for the next stage as an inputs. Now pck falls fromVDD to zero, ‘/out’ returns its energy to pck hence delivered charge is recovered. ECRL usesfour phase clocking rule to efficiently recover the charge delivered by pck. For detailed studyfollow the reference [4]. 2N-2P INVERTER Fig.2 WAVEFORM FOR 2N-2P INVERTER Fig.3 16
  • 4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME 4x4 2N-2P ARRAY MULTIPLIER WAVEFORM FOR 4x4 2N-2P ARRAY MULTIPLIERV.2N-2N2P ADIABATIC LOGIC The schematic and simulated waveform of the 2N-2N2P inverter gate is shown in Fig.4and Fig.5 respectively The 2N-2N2P logic family was derived from 2N-2P in order to reducethe coupling effect. The major difference with respect to 2N-2P is that the latch is made by twopMOSFETs and two nMOSFETs, rather than by only two pMOSFETs as in 2N-2P.Theadditional cross-coupled nMOSFET switches lead to non-floating outputs for a large part of therecovery phase. 17
  • 5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME 2N-2N2P INVERTER Fig.4 WAVEFORM FOR 2N-2N2P INVERTER Fig.5 4x4 2N-2N2P ARRAY MULTIPLIER 18
  • 6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME WAVEFORM FOR 4x4 2N-2N2P ARRAY MULTIPLIERVI. ENHANCED 2N-2P ADIABATIC LOGICThe ENHANCED 2N-2P operation consists of • The pre-resolving phase, when the inputs are preresolved. • The Evaluate phase, when PC raises and evaluates using the pre-resolved circuit states. • The Hold phase. • The Recovery phase. ENHANCED 2N-2P INVERTER WAVEFORM FOR ENHANCED 2N-2P INV: 19
  • 7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME 4x4 ENHANCED 2N-2P ARRAY MULTIPLIER WAVEFORM FOR 4x4 ENHANCED 2N-2P ARRAY MULTIPLIER:VII. COMPARISION RESULTS OF 4x4 ARRAY MULTIPLIERS: LOGICFAMILIES Avg. POWER(uw) CMOS 0.5914806 2N-2P 0.5213958 2N-2N2P 0.5114439 ENHANCED2N-2P 0.3460064VIII. CONCLUSION The different parameter variations against adiabatic logic families are investigated, whichshows that adiabatic logic families highly depend upon its. But less power consumption inadiabatic logic families can be still achieved than CMOS logic over the wide range of parametervariations. Enhanced 2n-2p logic shows better energy savings than other families at the 100Mhzfrequency. Hence adiabatic logic families can be used for low power application over the widerange of applications. 20
  • 8. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEMEREFERENCES[1] Rakesh Kumar Yadav, Ashwani K. Rana, “Adiabatic Technique for Energy Efficient LogicCircuits Design” Proceedings of ICETECT ,pp.776-780,2011.[2] R. C. Chang, P. -C. Hung, and I. -H, Wang, “Complementary pass-transistor energy recoverylogic for low-power applications”, IEEE Proc. Computers and Digital Techniques, Vol. 149, pp.146-151, July 2002.[3] B. Voss and M. Glesner, “A low powersinusoidal clock,” In Proc. Of the International Symposium on Circuits and Systems, pp.108-111, May200l.[4] Y. Moon and D.K. Jeong, “An efficient charge recovery logic circuit,” IEEE J. Solid-StateCircuits, vol. 31, no. 4, pp. 514–522, Apr. 1996.[5] W. C. Athas, L.J. Svensson, J.G. Koller, N. Tzartzanis, and E. Chou, “Low power digitalsystems based on adiabatic-switchin principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp.398-407, Dec. 1994.[6] J. S. Denker, “A review of adiabatic computing,” in IEEE Symp. On Low Power Electronics,pp. 94-97, 1994.[7] T. Gabara, “Pulsed Power Supply CMOS,” Technical Digest IEEE Symposium Low PowerElectronics, San Diego, pp. 98- 99, Oct. 1994. 21