Split set data weighted averaging – an efficient approach for removal of periodic

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Split set data weighted averaging – an efficient approach for removal of periodic

  1. 1. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME243SPLIT SET DATA WEIGHTED AVERAGING – AN EFFICIENTAPPROACH FOR REMOVAL OF PERIODIC NOISE IN DATACONVERTERSDr. Syed Abdul Sattar1, Mohammed Arifuddin Sohel 2Dr. K. Chennakeshava Reddy 31Professor, Royal Institute of Technology and Science, Chevella, Ranga Reddy Dist,A.P., INDIA2Associate Professor, Department of Electronics and Communication Engineering,Muffakham Jah College of Engineering and Technology, Hyderabad, A.P., India3Principal, TKR College of Engineering and Technology, Meerpet, Ranga Reddy Dist,A.P., INDIAABSTRACTData Converter (ADC and DAC) architectures which rely on matched components, sufferperformance degradation due to component mismatch. In practice, perfectly matched components likeresistors, capacitor and switches are impossible to fabricate, and mismatch errors are inevitable. Theseerrors can be corrected by means of Dynamic Element Matching (DEM) techniques. Data WeightedAveraging (DWA) is the most commonly used DEM technique, but it results in presence of unwantedinband periodic noise in the output, for a slow varying or DC input. This paper proposes an efficienttechnique of mismatch noise shaping, named Split-Set Data-Weighted Averaging (SDWA) that makesthe DAC immune to component mismatch noise and at the same time eliminates the inband noisetones in the DC response of the System. Hardware implementation of SDWA is cost-effective anddisplays low-latency, which makes its use practical, in high speed applications.Keywords: Data Converters, Component Mismatch, Dynamic Element Matching, Data weightedaveraging, Split Set Data Weighted Averaging.1. INTRODUCTIONIn VLSI circuits, component mismatch errors are caused by process variations such as maskmisalignment, non-uniform oxide thickness, and non-uniform doping densities. Further, mismatcherrors can be generated by temperature gradients across the circuit, component aging and componentnoise [1], [2]. In ADCs and DACs, mismatch errors lead to errors in the converter’s transfer functionand thus the converter’s performance is adversely affected.INTERNATIONAL JOURNAL OF ADVANCED RESEARCH INENGINEERING AND TECHNOLOGY (IJARET)ISSN 0976 - 6480 (Print)ISSN 0976 - 6499 (Online)Volume 4, Issue 3, April 2013, pp. 243-250© IAEME: www.iaeme.com/ijaret.aspJournal Impact Factor (2013): 5.8376 (Calculated by GISI)www.jifactor.comIJARET© I A E M E
  2. 2. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME244Various techniques, including special VLSI layout Procedures, Laser Trimming, Self-Calibration and Dynamic Element Matching (DEM) [3][4][5], can reduce the effects of componentmismatch errors in Data converters that have a resistor based design. While the techniques proposedin [3][4]and [5] are very costly to implement, the dynamic element matching technique has emergedas the most efficient cost effective method for reduction of resistor based mismatch errors.DEM is a dynamic process that reduces the effects of component mismatches in electroniccircuits by rearranging dynamically the interconnections of mismatched components so that the timeaverages of the equivalent components at each of the component positions are equal or nearly equal.By appropriately varying the mismatched components’ virtual positions, the effects of mismatchedcomponents can be reduced, eliminated, or frequency shifted. This technique is known as DataWeighted Averaging (DWA)[6].2. COMPONENT MISMATCH PROBLEM IN DACA Digital-to-Analog Converter (DAC) is a device that reconstructs a continuous-time analogsignal from its digital form. A unit-element DAC, is a widely used structure for an M-bit DAC, whichis built from unit elements such as resistors or capacitors or current sources. Figure 1 shows thediagram of the unit-element DAC.Figure 1 - The Unit-Element DACAn M-bit unit-element DAC usually has M+1 output levels and for an M-bit inputdata, equation 1, describes the output of the unit-element DAC.(1)Where is the input data and is the unit-element value. Normal DACs use weighted resistortechnique to implement binary weighted codes. But, the input data to a unit-element DAC, is thethermometer code in which, the number of 1’s correspond to the decimal value that a code represents.Table 1 shows the thermometer codes for a seven-level unit-element DAC.
  3. 3. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME245Table 1: A 3-Bit Binary to Thermometer CodeDecimalBinary Thermometer Codeb2 b1 b0 d6 d5 d4 d3 d2 d1 d0012345670 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 0 0 0 0 00 0 0 0 0 0 10 0 0 0 0 1 10 0 0 0 1 1 10 0 0 1 1 1 10 0 1 1 1 1 10 1 1 1 1 1 11 1 1 1 1 1 1A Thermometer based DAC is not a minimal representation, since a binary weighted DACrequires only N digital inputs and Thermometer based DAC needs 2Ndigital input values. This leadsto an additional hardware requirement, of a binary to thermometer code converter. However, athermometer based converter does have advantages of low DNL errors, guaranteed monotonicity, andreduced glitching noise when compared to its binary counterpart [4].2.1 Thermometer Based DACA method to realize a D/A converter with the use of a thermometer code input is to build 2N-1equal-sized resistors and switches attached to the virtual ground of an opamp, as shown in figure 2.Figure 2 - Thermometer Code based Resistor DAC [4]Many DAC architectures use matched references, amplifiers and switches to perform signalconversion. DAC references are typically voltages or currents generated by matched components,such as resistors, transistors, and capacitors. These component values will differ from their designvalues due to fabrication process variations and temperature gradients across the circuit. Thesevariations, or mismatch errors, cause inaccurate output levels such that the DAC’s output containsharmonic distortion.2.2 Integral Non Linearity(INL) And Differential Non Linearity(DNL)The component mismatch problem further leads to non linearity errors called INL and DNL.INL error is described as the deviation, of an actual transfer function from a straight line joining theend points of the output. DNL error is defined as the difference between the converter’s ideal codewidths and the converter’s actual code widths. Figure 3 shows the maximum INL and DNL of a non-ideal three bit DAC.
  4. 4. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME246Figure 3: INL and DNL – Nonlinearity for a Three bit DAC [4]3. DYNAMIC ELEMENT MATCHINGThermometer codes have a highest priority to select the first unit-element-U0 and lowestpriority to select the last one - U6. Since mismatches usually exist among all the unit elements, theINL and DNL errors increase in a unit-element DAC by such a selection process. This non linearityshould be reduced in order to achieve high accuracy. A Dynamic Element Matching (DEM) block istargeted towards reducing this mismatch error.3.1 Data Weighted Averaging (DWA)The data weighted averaging DEM algorithm rotates circuit elements at the maximumpossible rate while ensuring that each element is used the same number of times [11]. The circuitelements are selected sequentially from the array starting with the next available unused element. Thecircuit components are used at the maximum possible rate, causing the mismatch errors to sum to zeromore quickly. The output of thermometer DAC with DWA and without DWA, for similar inputs isshown in Table 2. It is clear that, without DWA U0 is most frequently used unit element and U6 is notused at all. Comparatively, DWA technique uses all unit elements with equally likely probability andleads to reduction in mismatch errors.Table 2: The DWA EncodingOutput withoutDWAOutput With DWADecimalinput4 3 1 5 4 3 1 5 0 2 6HexdecimalOutput0f 70 01 3e 0f 70 01 3e 3e 41 7eU(6) 0 0 0 0 0 1 0 0 0 1 1U(5) 0 0 0 0 0 1 0 1 1 0 1U(4) 0 0 0 1 0 1 0 1 1 0 1U(3) 1 0 0 1 1 0 0 1 1 0 1U(2) 1 1 0 1 1 0 0 1 1 0 1U(1) 1 1 0 1 1 0 0 1 1 0 1U(0) 1 1 1 1 1 0 1 0 0 1 03.2 The Inband Noise Tone Generation in DWA algorithmDWA uses the unit-element cyclically in order to make the long-term average use of each unitelement in the DAC the same. The power spectrum of mismatch errors at DAC output is given by [10](2)
  5. 5. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME247As can be seen, first-order DAC mismatch errors shaping is achieved by using DWA.However, if the DAC input is a DC or a low-frequency signal, the mismatch errors are not first-ordershaped [12]. For example, for a six-element DAC with consecutive inputs 2, 2, 2, 2 ,…, the selectedunit elements are going to be (U1 U2), (U3 U4), (U5 U6), (U1 U2) , then the output mismatch errorsare periodic, which results in an undesired situation. With a random input signal, the maximumachievable resolution of a unit-element DAC with oversampling factor M is given by equation 3. (3)Here, is the variance of the unit elements and N is the number which signifies unitelements. For a DC input signal to the same unit-element DAC, the spectrum of the mismatch errorsdepends on the DC levels [13]. Generally, a low order error component of high power is folded backinto the baseband for some values of DC inputs and the equivalent resolution is then decreased.In order to overcome the tone problem, a modified algorithm, named split-set data weightedaveraging (SDWA), is proposed. SDWA operates by splitting the unit element set into subsets in aspecial way, and randomizing each subset independently.4. IMPLEMENTATION OF DWA ALGORITHMDWA employs the technique in which each element of the unit element DAC is not usedagain until all the unit elements are used at least once. The algorithm to achieve this is shown below.4.1 DWA Algorithm1. Set the pointer to zero level.2. Convert the input binary data b to thermometer code with n ones starting from t0 to tn.3. Use the n elements of the DAC from the pointer level.4. Set the pointer to (n+1) level for the next input.5. For an N element thermometer DAC with elements starting from 0 to (N-1), if the codeexceeds (N-1) element reuse the elements again starting from 0.6. Repeat steps 2 to 5 for each input to the DAC.The above algorithm is implemented in verilog code and when executed in cadence virtuosoresulted in the test schematic shown in figure 4(a) and its output waveform is shown in figure 4(b).Figure 4: (a) Test schematic of DWA algorithm (b) output waveform of DWAThe simulation results of DWA algorithm are presented in Table 3, the first element to beused is U(0), it is not used again until all the other elements U(1) to U(7) are used at least once. For abinary input 000 to 111, we get the DWA output as 00(h) wherein no elements are one, 01(h) whereinU(0) is selected, 06(h) wherein the next unused elements U(1) and U(2) are selected, 38(h) in whichelements U(3) U(4) and U(5) are selected and so on. The hexadecimal results 00 01 06 38 79 7e 7fare in agreement with the cyclic order selection as required by the DWA algorithm.
  6. 6. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME248Table 3: Simulation result of DWA algorithmDWAinput0 1 2 3 4 5 6 7DWAoutput00 01 06 38 47 79 7e 7fU(6) 0 0 0 0 1 1 1 1U(5) 0 0 0 1 0 1 1 1U(4) 0 0 0 1 0 1 1 1U(3) 0 0 0 1 0 1 1 1U(2) 0 0 1 0 1 0 1 1U(1) 0 0 1 0 1 0 1 1U(0) 0 1 0 0 1 1 0 1The problem with DWA comes when a slow varying signal is given as input. Consider abinary input 100 given to the DWA block for a series of clock cycles. The result obtained is shown inTable 4.Table 4 – Simulation Result of DWA algorithm for constant binary input of 4DWAinput4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4DWAoutput0f 71 1e 63 3c 47 0f 71 1e 63 3c 47 0f 71 1e 63 3c 47 0fU(6) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0U(5) 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0U(4) 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0U(3) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1U(2) 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1U(1) 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1U(0) 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1The results obtained are hexadecimal - 0f 71 1e 63 3c 47 78 0f 71 and so on. As can be seen,the ouput repeats after 7 clock cycles and is an unwanted low frequency noise tone. In-Band tonesgenerated by the basic DWA algorithm are unacceptable in audio applications[14]. Hence we go foran improved technique SDWA which is a modification of the basic DWA algorithm.5. IMPLEMENTATION OF SPLIT-SET DATA WEIGHTED AVERAGING (SDWA)ALGORITHMSplit set data weighted averaging technique not only performs the cyclic selection as inDWA, but also rotates the zeroes(0’s) among themselves and ones(1’s) among themselves in everyclock cycle.5.1 SDWA algorithmSDWA operates by splitting the unit element set into subsets in a special way, andrandomizing each subset independently. For an N-element DAC, SDWA is carried out in thefollowing steps:1. Apply DWA to the N unit elements of the DAC in each clock cycle, i.e., use them consecutively ina cyclic manner;2. Split the set of all unit elements into two subsets K and L. Subset K contains elements 1 through k,where k is the highest unit-element index used; its complement L contains elements with indices k+1through N;
  7. 7. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME2493. Rotate or scramble all elements of K within the subset K , and similarly rearrange the elements ofL internally within the subset L .4. Return to Step 1, starting with the unit element now occupying position k+1.It is easy to see that this randomization only minimally disturbs the equal usage of unit elements, andspecifically that all unit elements are used at least M times before any one is used M+1 times. Hence,the noise floor should not be significantly affected by the process, while the tones are prevented bythe randomization performed in Step 3. The above algorithm is implemented in verilog code andwhen executed in cadence virtuoso resulted in the test schematic shown in figure 5(a) and its outputwaveform shown in figure 5(b).(a) (b)Figure 5: (a) Test schematic of SDWA algorithm (b) Output waveform of SDWAConsider a seven-level DAC with the input sequence 4, 3, 1, 5. The initial order of the unit elements isU0, U1, U2, U3, U4, U5, U6. Starting with an input code 4, unit elements U0, U1, U2, and U3 areused. Then the unit elements are split into two subsets (U0, U1, U2, U3) and (U4,U5, U6), which arerotated by one position independently in order to give (U3, U0, U1, U2) and (U6, U4, U5). The neworder of all unit elements is thus (U3 U0 U1 U2 U6 U4 U5). A second input data 3 is then going tochoose unit elements (U3 U0 U1). Again the unit elements are split into (U3 U0 U1), (U2 U6 U4 U5)and are rotated separately. The new order of unit elements now is (U1 U3 U0 U5 U2 U6 U4).Theresults of SDWA 00 40 03 1c 71 75 3f and 7f comply with the conditions of DWA circular shift andsplit set shifts among zeroes and ones as shown in table 5.Table 5: Simulation Result of SDWA Algorithm with normal input and DC input of 4SDWA Input 0 1 2 3 4 5 6 7 4 4 4 4 4 4 4 4SDWA output(Hexadecimal)00 40 03 1c 71 75 3f 7f 78 4B 59 0F 2B 1E 56 3CU(6) 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 0U(5) 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 1U(4) 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 1U(3) 0 0 0 1 0 0 1 1 1 1 1 1 1 1 0 1U(2) 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 1U(1) 0 0 1 0 0 0 1 1 0 1 0 1 1 1 1 0U(0) 0 0 1 0 1 1 1 1 0 1 1 1 1 0 0 0The advantage of SDWA over DWA comes when a constant input is given to the DAC.Consider in the following example, wherein, the SDWA block is given input constantly as binary100(4d) for a series of clock cycles. SDWA eliminates the tones which would have been produced incase of DWA and the ouput is random without repetition thus eliminating tone problem of DWA.
  8. 8. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME250SDWA output 0f 78 4b 59 0f 2b 1e 56 3c depicted in Table 5 shows that there is no repetitionand the tonal problem of DWA is completely eliminated. This happened because of the internal shiftsamong the subsets of 0’s and 1’s which result in randomization of the data which was otherwiseperiodic and resulted in in-band tones in DWA.6. CONCLUSIONThe output of DWA with binary input 100 was 0f 71 1e 63 3c 47 78 0f and 71 i.e., the patternis repeated after every 7 clock cycles, whereas output with binary input 100 when given to SDWAgives the result 0f 78 4b 59 0f 2b 1e 56 3c. It can be observed that the cyclic repetition pattern iscompletely removed. Hence the non-linearity is eliminated. Further, the INL of SDWA is calculatedto be 45 mV and DNL of 25mV which is very low in comparison with standard DWA algorithm.REFERENCES1. S. Kuboki, K. Kato, N. Miyakawa and K. Matsubara, “Nonlinearity Analysis of resistor stringA/D converters,” IEEE Tran. Circuits and Systems, vol. 29, no. 6, pp. 383-389, June 1982.2. B. Razavi, Principles of data conversion system design, Piscataway, NJ: IEEE Press, 1995.3. R. Wittmann, et al, “Trimless High Precision Ratioed resistors in D/A and A/D converters,” IEEEJ. Solid-State Circuits, vol. 30, pp. 935-939, August 1995.4. D. A. Johns, and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc. 1997.5. I. Fujimori, A. Nogi, and T. Sugimoto, “A Multibit Delta-Sigma Audio DAC with 120dBdynamic range”IEEE Journal of Solid-State Circuits, vol. 35, No.8, pp. 1066-1073, August 2000.6. R. T. Baird, and T. S. Fiez, “Linearity Enhancement of Multibit A/D and D/A converters usingData Weighted Averaging”. IEEE Transactions on Circuits and Systems II, vol.42 no.12 pp.753-762, December 1995.7. O. J. A. P. Nys, and R. K. Henderson, “An analysis of dynamic element matching techniques insigma-delta Modulation”, IEEE International Solid-State Circuits Conference, Digest ofTechnical Papers, February 1996, pp. 231-234.8. K. D. Chen, and T. H. Kuo, “An improved technique for reducing baseband tones in sigma-deltaemploying data weighted averaging algorithms without adding dither”. IEEE Transactions onCircuits and Systems II, vol.46 no.1 pp. 63-68, January 1999.9. M. Vadipour, “Techniques for preventing tonal behavior of data weighted averaging algorithm insigma delta modulators”,. IEEE Transactions on Circuits and System II, vol.47 no.11 pp. 1137-1144, November 2000.10. Hasanpour, Y. ,BandPass Dynamic Element Matching for low OSR high resolution Delta SigmaModulators, Electronic Devices, Systems and Applications (ICEDSA), 2011 InternationalConference on, Page(s): 232 – 236, 25-27 April 2011.11. D. K. Su, Oversampling digital-to-analog conversion, PhD dissertation, Stanford University,199412. R. Schreier, and G.C. Temes, Understanding Delta-Sigma Data Converters,IEEE Press, 2005.13. V. Colonna, .A 0.22-mm2 7.25-mW per-channel audio stereo-DAC with 97-dB DR and 39-dBSNRout,. IEEE Journal of Solid-State Circuits, vol. 40, no.7 pp. 1491-1498, July 2005.14. Neitola, M. and Rahkonen, T. , “A Generalized Data-Weighted Averaging Algorithm” Circuitsand Systems II: Express Briefs, IEEE Transactions on, Volume: 57 , Issue: 2 Page(s): 115 – 119,Feb. 2010.15. P. Hari Krishna Prasad and Dr. M. Venu Gopal Rao, “DC-DC Converters for Telecom PowerSupply Applications”, International Journal of Electrical Engineering & Technology (IJEET),Volume 3, Issue 1, 2012, pp. 156 - 166, ISSN Print : 0976-6545, ISSN Online: 0976-6553.

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