• Share
  • Email
  • Embed
  • Like
  • Save
  • Private Content
Mitigation of switching overvoltage by application of surge arrester on capacitor
 

Mitigation of switching overvoltage by application of surge arrester on capacitor

on

  • 412 views

 

Statistics

Views

Total Views
412
Views on SlideShare
412
Embed Views
0

Actions

Likes
0
Downloads
2
Comments
0

0 Embeds 0

No embeds

Accessibility

Categories

Upload Details

Uploaded via as Adobe PDF

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

    Mitigation of switching overvoltage by application of surge arrester on capacitor Mitigation of switching overvoltage by application of surge arrester on capacitor Document Transcript

    • INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 2, March – April (2013), © IAEME & TECHNOLOGY (IJEET)ISSN 0976 – 6545(Print)ISSN 0976 – 6553(Online) IJEETVolume 4, Issue 2, March – April (2013), pp. 37-45© IAEME: www.iaeme.com/ijeet.aspJournal Impact Factor (2013): 5.5028 (Calculated by GISI) ©IAEMEwww.jifactor.com MITIGATION OF SWITCHING OVERVOLTAGE BY APPLICATION OF SURGE ARRESTER ON CAPACITOR BANK Dr. Mrs. Hina Chandwani1, C. D. Upadhyay2 , Akil Vahora3, Goutam Som4 1 Associate Professor, FTE, The M. S. University of Baroda, Vadodara, Gujarat, India 2 Reseach Scholar, FTE, The M. S. University of Baroda, Vadodara, Gujarat, India 3 Student of Master of Engineering L.D.College of Engineering, Ahmedabad, Gujarat, India 4 Student of Master of Engineering L.D.College of Engineering, Ahmedabad, Gujarat, India ABSTRACT The paper presents the application of surge arresters as a switching overvoltage protection of capacitor bank circuit breakers. Based on an existing Medium Voltage-Capacitor bank MATLAB power simulink is performed to show the effectiveness of the surge arrester in reducing circuit breaker Transient Recovery Voltages and minimizing the probability of circuit breaker restrikes. The energy requirements of the surge arresters and the overvoltage protection levels of the capacitors for different surge arrester arrangements are calculated. KEYWORDS: TRVs, Capacitor Bank, Surge Arrestor, De-energisation 1. INTRODUCTION Medium voltage capacitor banks are designed for industrial, utility and commercial power systems to improve power factor, increase system capacity, reduce harmonic distortion and improve voltage regulation.[1,2,3] Capacitor bank switching is one of the most demanding operations in MV networks, due to its associated transients. During the opening operation the TRVs across the circuit breaker can rise to very high values and that can initiate breaker restrikes which in turn generate even higher overvoltage [4, 8]. Consequently, any restrike implies additional stress to capacitor and circuit breaker, which reduces their lifetime. If multiple restrikes occur, which can damages the capacitor and circuit breaker immediately [6, 7]. A way to prevent these overvoltages for new switchgears is the installation of modern circuit breakers with a low probability of restrike [5]. For users, having old existing 37
    • International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 2, March – April (2013), © IAEMEswitchgear not suitable for capacitor bank applications, the question is whether the insertingof surge arresters across the capacitor can minimize the probability of the circuit breakerrestrikes [9, 10]. Based on a real existing installation of a MV-Capacitor bank a study usingthe MATLAB power simulink Software was performed in order to evaluate the effectivenessof the surge arrester application in minimizing the probability of circuit breaker restrikes.2. MODELLING A case of substation of 220/33 KV, located at Versova, MUMBAI is taken here.Based on an existing installation of a 33kV, 14.7 MVAR capacitor bank (ungrounded doublewye -connected), a 3-phase model of a MV-Capacitor bank including the networkcomponents (capacitors, reactor, circuit breaker, and transformer) has been developed toperform an MATLAB power simulink Simulation for the opening operation of the capacitorbank. A single-line diagram of the substation and capacitor bank is shown in withall the ratings marked therein Fig.1. The modelling is based on the following conditions:•The sequence of a three-phase break of capacitive load followed by restrikes in two phasesat t=10 ms (1/2cycle) after current interruption was identified as the decisive case. Thenetwork with isolated neutral and a power frequency of 50Hz was selected as the most severecase• The circuit breaker interrupts the high frequency current at the first current zero.According to figure 2 three arrester arrangements are investigated for phase to phase andphase to ground. The system neutral Rg was set to zero. 38
    • International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 2, March – April (2013), © IAEME• As a surge arrester model a class 3 gap less surge arrester type with a fixed protection level of Ures(lightning withstand voltage) /Uc(max residual discharge voltage) = 170/85=2.0 (at in(nominaldischarge current) = 10ka) is used• The magnitude of overvoltages is given in p.u. (per unit) as a multiple of the peak value of the phase peak-to-phase voltage Fig.2: Equivalent circuit with the arrester arrangements: phase to ground, phase to neutral, phase to phase2.1 DE-ENERGISATION OF CAPACITOR BANK ENERGISATION In order to evaluate the severity of over voltages and to determine the effectiveness of a surgearrester application, the step by step procedure was simulated for the following cases2.1.1 Three phase break of capacitive load Using the equivalent circuit according Fig.2 for a single stage capacitor bank (S=14.7 MVA)with no surge arrester connected on the network the Voltage and current characteristics shown inFig.4 are obtained. The first pole to-clear is phase b and the circuit breaker SW1 interrupts the current to uitin Phase b. From the moment the current is interrupted, the charge of the capacitor is trapped and thevoltage remains constant at the value it had at zero current. The recovery voltage across the circuitbreaker for the first pole to clear rises up to 2.8 p.u. This overvoltage is the most severe voltage stressfor the circuit breaker for all investigated cases. As an assumption the circuit breaker is able towithstand the voltage stress of 2 p.u. without a restrike. In FFT analysis tool of MATLAB we aregetting total harmonic distortion of 71.01% which is very harmful for other system equipment Fig. 3 modelling in MATLAB power simulink of capacitor bank system 39
    • International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 2, March – April (2013), © IAEME Fig.4 capacitor bank voltage current without surge arrester2.1.2 Capacitor bank switching with surge arresterAccording to figure 5, Surge arrester is connected between phase to phase capacitor bankreduce the overvoltage same arrangement of surge arrester model in simulink as shown figure9 which limit to 1.5 p.u. voltage which is in withstand limit of breaker unit Figure 5. Modelling in MATLAB power simulink of capacitor bank with surge arrangement 40
    • International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 2, March – April (2013), © IAEME Figure6. Capacitor bank voltage and current with surge arrester2.1.3 Three phase break of capacitive load associated with multiple breaker restrikes The same sequence is simulated as in case 1 but as an assumption the circuit breakeris not able to withstand the voltage stress of 2 p.u. and a two phase restrike occurs at the peakvalue of the recovery voltage in phase a and b (Fig.7). A transient current with an oscillationfrequency starts to flow and the voltage across the capacitor swings up to 3 p.u. The circuitbreaker interrupts the current again at the first of its current zeros, with the result that thevoltage across the capacitor remains on the new constant value and voltage across the circuitbreaker SW1 in Phase a and b rises up to 2.3 p.u. In case of further restrikes overvoltages willraise up to 3.0 p.u. across the capacitors and 4.15 p.u for further restrike. This process ofvoltage and current escalation can damage the capacitor and breaker units. Figure 7: Three phase break of capacitive load associated with multiple breaker restrikes 41
    • International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 2, March – April (2013), © IAEME 2.1.4 Three phase break of capacitive load associated with multiple breaker restrikes and using surge arresters FIG.8A Capacitor voltage Fig.8B Breaker currentFigure 8 Capacitor bank voltage and current when surge arrester connected to phase to ground 42
    • International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 2, March – April (2013), © IAEME The same sequence is simulated as in case 2 but using a surge arrester arrangementphase to ground. The obtained voltage and current characteristics are shown in Fig.8. Thesurge arrester limits the overvoltage across the capacitors at 1.55p.u. In the case of multiplerestrikes this overvoltage level remains constant. A voltage escalation across the capacitorand thus a capacitor failure is prevented. The transient recovery circuit breaker voltage acrossthe first pole-to-clear is limited at 2.0p.u. After the first restrike and that mitigates the risk offurther breaker restrikes. A surge arrester arrangement phase to phase also reduce the overvoltage to 1.2 p.u The surge arrester not only protects the capacitor from dangerousovervoltages but decreases the probability of multiple restrikes of the breaker, too .2.1.5 Comparison of breaker TRVs and capacitor voltages for the first pole-to-clear phase A detailed one-to-one comparison of the cases 2 and 3 for the first pole-to-clear(Phase c) characteristic shows the effectiveness of a surge arrester application (Fig.6 & 8).The effect of the TRV-limitation across the capacitor and the circuit breaker starts with thefirst restrike. There is no voltage limitation during the opening operation without a restrike.Therefore, the surge arrester can only reduce the over voltages if a restrike occurs. There isno benefit for the circuit breaker to reduce the risk of a first restrike, but it mitigates the riskof multiple restrikes3. ENERGY STRESS ON SURGE ARRESTER The energy stresses on the surge arresters were calculated for different arresterarrangements (Fig.2) and different circuit parameters. The following results are obtained3.1 Energy stress as a function of the three phase capacitor bank size A single-stage capacitor bank is used to vary the three-phase bank size in order toevaluate the effect on the surge arrester energy stress. The grounding conditions of the systemneutral don`t affect the energy stress on the surge arrester. Only In case of a directly-grounded neutral (Rg = 0) and an arrester arrangement phase to ground a slightly higherenergy of 7% has to take into account.Fig. 9 Energy stress as a function of capacitor bank size (based on 3 successive restrikes)In case of a directly-grounded neutral (Rg = 0) and an arrester arrangement phase to ground aslightly higher energy of 7% has to take into account. 43
    • International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 2, March – April (2013), © IAEME3.2 PROTECTION CONSIDERATIONS The voltage across the capacitor bank for a single stage capacitor bank is determinedas a function of the three phase capacitor size. The resulting voltages depending on thearrester Positioning are shown in Figure 10.The same capacitor voltage is obtained forsystems with directly-grounded (Rg = 0) as well as ungrounded neutral (Rg = ∞). The effectof the number of parallel capacitor stages and the number of repeated restrikes on thecapacitor voltage is negligible. Fig.10 Resulting capacitor voltages as a function of capacitor size4. CONCLUSION Based on the computer simulation of the capacitor bank Deenergisation the followingapplication considerations and conclusions can be drawn: In the simulation of the capacitor switching, the mal-effect of over voltage on Circuit Breaker can be reduced by implementing surge arresters at an instant. Not only the reduction of C.B failure is done but also the risk of multiple restrikes is controlled by limiting the TRVs of the C.B5. ACKNOWLEDGEMENTS For the technical & data support we are thankful to Schneider electrical infrastructureltd. Vadodara, India.REFERENCESBooks [1] Ramasamy Natrajan, Power system capacitors ( Taylor & Francis Group, LLC,2005) [2] L. Van Der Sluis, Transients in Power Systems (John Wiley & Sons, 2001) [3] A. Greenwood, Electrical Transients in Power Systems ( New York: John Wiley & Sons, 2nd Ed., 1991) 44
    • International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 2, March – April (2013), © IAEMEJournal Papers [4] Grebe, T.E., Application of Distribution System Capacitor Banks and Their Impact on Power Quality (IEEE Transactions on Industry Applications, 1996,.32(3): P. 714-719) [5] Das J. C., Analysis And Control Of Large Shunt Capacitor Bank Switching Transient (IEEE Transactions On Industry Application, 2005. 41(6): P.1444-1451) [6] D. Rodriguez Sanabria, C. Ramos-Robles, L. Orama Exclusa, Lightning And Lightning Arrester Simulation In Electrical Power Distribution Systems (IEEE Transaction 2004) [7] Sahib Abdoolwadood Ali, Capacitor Banks Switching Transient In Power System (Cscanada Energy Science And Technology 2011, Vol. 2, No. 2, 2011, Pp. 62-73) [8] Mehdi Nafar, Gevork B Gharehpetian And Taher Niknam , A Novel Parameter Estimation Method For Metal Oxide Surge Arrester Models (Indian Academy of Sciences Part 6, pp. 941–961. Dec 2011) [9] Nilesh S. Mahajan and A. A. Bhole, “Black Box ARC Modeling of High Voltage Circuit Breaker Using MATLAB/SIMULINK” International Journal of Electrical Engineering & Technology (IJEET), Volume 3, Issue 1, 2012, pp. 69 - 78, ISSN Print : 0976-6545, ISSN Online: 0976-6553Proceedings Papers [10] Braun. D., Koeppl G, Transient Recovery Voltages during the Switching Under Out- Of-Phase Conditions (International Conference on Power Systems Transients IPST 2003 in New Orleans, USA) 45