Your SlideShare is downloading. ×
Low power cmos binary counter using conventional flip   flops
Low power cmos binary counter using conventional flip   flops
Low power cmos binary counter using conventional flip   flops
Low power cmos binary counter using conventional flip   flops
Low power cmos binary counter using conventional flip   flops
Low power cmos binary counter using conventional flip   flops
Low power cmos binary counter using conventional flip   flops
Upcoming SlideShare
Loading in...5
×

Thanks for flagging this SlideShare!

Oops! An error has occurred.

×
Saving this for later? Get the SlideShare app to save on your phone or tablet. Read anywhere, anytime – even offline.
Text the download link to your phone
Standard text messaging rates apply

Low power cmos binary counter using conventional flip flops

425

Published on

Published in: Technology, Business
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total Views
425
On Slideshare
0
From Embeds
0
Number of Embeds
0
Actions
Shares
0
Downloads
16
Comments
0
Likes
0
Embeds 0
No embeds

Report content
Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
No notes for slide

Transcript

  • 1. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN INTERNATIONAL JOURNAL OF ELECTRONICS AND 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEMECOMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)ISSN 0976 – 6464(Print)ISSN 0976 – 6472(Online)Volume 4, Issue 2, March – April, 2013, pp. 243-249 IJECET© IAEME: www.iaeme.com/ijecet.aspJournal Impact Factor (2013): 5.8896 (Calculated by GISI) ©IAEMEwww.jifactor.com LOW POWER CMOS BINARY COUNTER USING CONVENTIONAL FLIP - FLOPS G. RAMESH1, J. PAUL RICHARDSON GNANARAJ2, M. VELVIZHI3, G. JESLY MARSHA4 1, 2, 3, 4 (ECE, Anna University, Chennai, India) ABSTRACT The performance of the proposed technique with the conventional clock gated and conventional non clock gated FFs were designed in 0.18-µm CMOS technology. The comparison and selection was based on the operation principle and the structure, since each type of FFs takes on a different behaviour in terms of redundant transitions depending on the factors. For the conventional counters, the amount of power consumed in FFs and logic gates used for evaluating the next counter values for implementing the clock gating are measured, including the power consumption and the clock inputs of the FFs and the logic gates. For the proposed counters, the amount of power consumed in FFs and LCGs are measured. The experimental result indicates that the proposed synchronous counter achieves a power saving and device count reduction. Keywords: Clock Gating, Non - clock gating, and Proposed clock gating - D flip-flops, HLFF, TGFF, Sense-Amplifier, Counter. I. INTRODUCTION In the past, the major concerns of the VLSI designer were area, performance, cost and reliability; power considerations were mostly of only secondary importance. In recent years, however, this has begun to change and, increasingly, power is being given comparable weight to area and speed in VLSI design. The continuing increase in chip scale and operating frequency has made power consumption a major concern in VLSI design. The need for low- power design is also becoming a major issue in high-performance digital systems, such as microprocessors, digital signal processors (DSPs) and other applications. Increasing chip density and higher operating speed lead to the design of very complex chips with high clock frequencies. 243
  • 2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEMEII. CIRCUIT DESIGN One of the best ways to reduce the power dissipation of a circuit is to lower the transistor supply voltage. Power reduces proportionally with the square of the of the supply voltage, while other components like frequency and capacitance produce only a linear reduction in power consumption. It can therefore be beneficial to determine the minimum voltage a circuit can successfully run, thus producing very low power consumption. This project attempts to determine the lowest successful operating voltage of a 4 bit counter in a high leakage, small feature size process. This experiment was completed in a series of steps. First, an appropriate counter design was selected. Second, the various design and simulation tools were identified and studied. Last, the design was implemented and the results were measured and evaluated. A. Timing Principles There are a number of factors to consider when choosing an appropriate design for a low voltage counter. By using a high static leakage technology, a large number of transistors in the design can be a significant source of static power dissipation. It can therefore be beneficial to keep the size of the circuit as small as possible. However, if in reducing the size of the circuit, the delay is increased, then this can negatively affect the amount of energy consumed per cycle. The simplest counter with the fewest number of gates is the asynchronous (ripple) counter shown in Figure 1. This type of counter can be constructed using nothing but flip-flops connected in series. Each previous flip flop acts as the clock for the higher order flip flop. When the least significant bit makes a transition, the information is rippled through to each successive flip-flop changing values as necessary [1]. The asynchronous counter can be useful in small counters, but as the number of bits of the counter grows, this ripple effect causes an increasing delay period in which the output of the counter is indeterminate. B. Synchronous timing principle The operation of conventional synchronous counters is usually based on a synchronous timing principle in which new data values of the entire counter bits are evaluated at every clock cycle and captured by associated flip-flops (FFs) at every triggering edge of the clock. Because the switching activity of counter bits in a binary counter is decreased by half as the significance of each bit increases, this type of operation apparently causes a lot of redundant transitions, particularly for counter bits having higher significance. C. Selection of synchronous Principle Synchronous counters solve the ripple effect problem by clocking every flip-flop simultaneously. All of the flip-flops make their transitions at the same time, and the information travels from the output to the input before the next rising edge of the clock. In a synchronous counter the indeterminate period of all of the flip-flops is the same, but as with the asynchronous counter, the delay of each flip-flop still increases as the number of bits grows The maximum delay of the synchronous counter, while also increasing, is significantly better at 1 flip-flop plus 16 AND gates. 244
  • 3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME Fig 1. 2-Bit Asynchronous Counter For this simulation, I chose the synchronous counter due to its ability to scale to a higher number of bits and adding a minimal amount of delay per bit. In a high leakage technology, reducing the delay can potentially help to reduce the amount of static leakage power consumed in the circuit. Also, by using a high bit count asynchronous counter in combination with low voltage, the unstable period where the counter produces the wrong value would become excessive. Fig 2. 2-Bit Synchronous CounterIII. DESIGN OF FLIP – FLOPS USING DIFFERENT CLOCKING METHODS A. Conventional Clock Gated In the conventional timing principle, the output of the combinational logic block is fed into the data input of the FF, and the triggering operation of the FF is controlled by a global clock (CK). Then, the input to the FF coming from the combinational logic block is unconditionally captured at every triggering edge of CK regardless of the previous value of the FF to advance system states, as shown in Fig. 3. Fig. 3 Generic structure of conventional synchronous timing principle 245
  • 4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME B. Proposed Timing Principle The proposed conditional pulse-based timing principle shown in Fig. 4, the output of the combinational logic block, which is shaped as a conditional pulsed signal, feeds the triggering input of the FF, and an inverted output of the FF is fed into the data input of the FF itself. Fig. 4 Generic structure of proposed principle C. Conventional Clock Gated The method is based on the clock gate design which can lead to power reduction without unduly complicating the traditionally simple topology. The analysis demonstrated that the power reduction hardly depends on the technological characteristic of the gates employed. Finally, the real efficiency of the presented gated-clock design should be evaluated also considering the increased silicon area required to implement the gating circuit in Fig 5. Fig. 5 Conventional clock gated principleIV. SIMULATION RESULTS AND COMPARISON OF FLIP FLOPS A. Simulation Results The simulation was performed using LT SPICE 0.18um technology and the comparison of conventional clock gated, non clock gated and proposed clock gated technique have been proposed and the simulation results shows that the proposed clock gated technique results in reduction of power by 12% 246
  • 5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME Fig. 6 D Flip Flop circuit with non-gated clock Fig.7 D Flip Flop circuit with gated clock Fig. 8 D Flip Flop circuit with proposed gated clock B. COMPARISON OF POWER CONSUMPTION AND SILICON AREA IN FFS No of Comparisons of FFs Power transistors Conventional non-clock-gated 10 80µW Conventional clock gated 26 95µW Proposed clock gated 12 75µW When this technique implemented in counters with several representative FFs such astransmission-gate FF (TGFF) , hybrid latch FF (HLFF) , and sense - amplifier-based FF(SAFF) were used as clocked storage elements for each type of counter. The selection of FFtypes was based on the operation principle (static versus dynamic) and the structure (singleended versus differential), since each type of FFs takes on a different behavior in terms ofredundant transitions depending on these factors. 247
  • 6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME Fig. 9 Transient Analysis of Counter Circuit Fig 10 comparison of transistors and power consumption of flip flops Fig. 11 Comparison of Power Dissipation of TGFF, HLFF, SAFFV. CONCLUSION This paper deals with the reduction of power and area in FFs which are used in the proposed counter. The analysis of power and area for FFs with conventional non -clock gated, conventional clock gated and proposed clock gated techniques to reduce power and area reduction in FFs and are carried out in CMOS counters in which FFs captures the value at every triggering edge of the clock. The experimental result using a 0.18-µm CMOS process technology indicates that the proposed principle used in FFs achieves power and device savings. Hence FFs using proposed timing principle, the area and power thereby can be reduced and hence there will be a reduction in power and devices and also we can eliminate redundant transitions and switching power consumption. 248
  • 7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEMEREFERENCESJournal Papers[1] N. H. E. Weste and D. Harris, CMOS VLSI Design. Reading, MA: Pearson Education,Inc., 2005.[2] M. R. Stan, A. F. Tenca, and M. D. Ercegovac, “Long and fast up/down counters,” IEEETrans. Comput., vol. 47, no. 7, pp. 722–735, Jul. 1998.[3] M. Katoozi and M. Soma, “A testable CMOS synchronous counter,” IEEE J. Solid-StateCircuits, vol. 23, no. 5, pp. 1241–1248, Oct. 1988.[4] M. Nogawa and Y. Ohtomo, “A data-transition look-ahead DFF circuit for statisticalreduction in power consumption,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 702–706,May 1998.[5] B.-S. Kong, S.-S. Kim, and Y.-H. Jun, “Conditional-capture flip-flop for statistical powerreduction,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1263–1271, Aug. 2001.[6] H. Jacobson, P. Bose, Z. Hu, A. Buyuktosunoglu, V. Zyuban, R. Eickemeyer, L. Eisen, J.Griswell, D. Logan, B. Sinharoy, and J. Tendler, “Stretching the limits of clock-gatingefficiency in serverclass processors,” in Proc. Int. Symp. High-Perform. Comput. Archit.,Feb. 2005, pp. 238–242.[7] W. Aloisi and R. Mita, “Gated-clock design of linear-feedback shift registers,” IEEETrans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 6, pp. 546–550, Jun. 2008.[8] H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper, “Flow-throughlatch and edge-triggered flip-flop hybrid elements,” in Proc. IEEE Int. Solid-State CircuitsConf., Feb. 1996, pp. 138–139.[9] B. Nikolic, V. G. Oklobdzija, V. Stojanovic, W. Jia, J. K.-S. Chiu, and M. M.-T. Leung,“Improved sense-amplifier-based flip-flop: Design and measurements,” IEEE J. Solid-StateCircuits, vol. 35, no. 6, pp. 876–883, Jun. 2000.[10] Kim, Young-Won, Kim, Joo-Seong; Oh, Jae-Hyuk; Park, Yoon-Suk; Kim, Jong-Woo;Park, Kwang-Il Il; Kong, Bai-Sun; Jun, Young-Hyun Hyun, “Low power cmos synchronouscounter with clock gating embedded into carry propagation,” IEEE J. Circuits & Systems II,vol. 56, no. 8,pp. 649-653, Aug. 2009.[11] Khaja Mujeebuddin Quadry, Dr. Syed Abdul Sattar and Dr. K. Soundara Rajan, “Designof 16 Bit Low Power Processor using Clock Gating Technique”, International journal ofElectronics and Communication Engineering & Technology (IJECET), Volume 3, Issue 3,2012, pp. 333 - 340, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.[12] P.Sreenivasulu, Krishnna veni ,Dr. K.Srinivasa Rao and Dr.A.VinayaBabu, “Low PowerDesign Techniques of CMOS Digital Circuits”, International journal of Electronicsand Communication Engineering & Technology (IJECET), Volume 3, Issue 2, 2012,pp. 199 - 208, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472. 249

×