Your SlideShare is downloading. ×
Fpga implementation of vedic multiplier
Upcoming SlideShare
Loading in...5
×

Thanks for flagging this SlideShare!

Oops! An error has occurred.

×

Introducing the official SlideShare app

Stunning, full-screen experience for iPhone and Android

Text the download link to your phone

Standard text messaging rates apply

Fpga implementation of vedic multiplier

770
views

Published on

Published in: Technology

0 Comments
1 Like
Statistics
Notes
  • Be the first to comment

No Downloads
Views
Total Views
770
On Slideshare
0
From Embeds
0
Number of Embeds
0
Actions
Shares
0
Downloads
0
Comments
0
Likes
1
Embeds 0
No embeds

Report content
Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
No notes for slide

Transcript

  • 1. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME150FPGA IMPLEMENTATION OF VEDIC MULTIPLIERKavita1, Umesh Goyal21E & Ec Department, PEC University of Technology, Chandigarh, India,2E & Ec Department, PEC University of Technology, Chandigarh, India,ABSTRACTAs Multipliers plays an important role in many fields like signal processing,embedded systems, so the demand to have an efficient and fast multiplier is increasing.This paper presents an efficient algorithm of Vedic Multiplier. Vedic Multiplier ascompared to other multipliers like array multiplier, Wallace tree multiplier, boothmultiplier, Modified booth multiplier etc. carry out the multiplication of two numbersvery efficiently and Vedic Multiplication process as compared to others is also fast. Thispaper briefly describes the methods used for Vedic Multiplication and the flow ofmultiplication with the help of flow chart. The hardware implementation of VedicMultiplier is carried out using Spartan 3E kit using Xilinx ISE Design Suite 14.2 tool forsimulation and the corresponding results are shown.Keywords: Multiplier, Vedic, Xilinx, Multiplication1. INTRODUCTIONDue to the growth of signal processing and demand of high speed processing, themultipliers have a great role to play. The multipliers are used to multiply two numbers.The more efficient and fast a multiplier is, the more it will be suitable for fast processingapplications. So an algorithm is developed for fast multiplication of two numbers. Thiswill be discussed later on in this paper.INTERNATIONAL JOURNAL OF ADVANCED RESEARCH INENGINEERING AND TECHNOLOGY (IJARET)ISSN 0976 - 6480 (Print)ISSN 0976 - 6499 (Online)Volume 4, Issue 4, May – June 2013, pp. 150-158© IAEME: www.iaeme.com/ijaret.aspJournal Impact Factor (2013): 5.8376 (Calculated by GISI)www.jifactor.comIJARET© I A E M E
  • 2. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME1512. VEDIC MULTIPLIERThe word “Vedas” which literarily means knowledge has derivational meaning asprinciple and limitless store-house of all knowledge. The word Veda also refers to thesacred ancient Hindu literature which is divided into four volumes. Vedas initially werepassed from previous generation to next generation orally. Later they were transcribed inSanskrit [1].Vedas include information from many subjects such as from religion, astronomy,architecture, mathematics, medicine etc. Vedic mathematics is not only a mathematicalwonder but also it is logical. That’s why Vedic mathematics has such a degree ofprominence which cannot be disapproved. Due to these characteristics, Vedicmathematics has already crossed the boundaries of India and has become a leading topicof research abroad. Vedic mathematics deals with various mathematical operations [2].The system of Vedic mathematics is based on 16 Sutras – formulas and 13 Up-sutras orCorollaries [3].The 16 Sutras are:1. Ekadhikina Purvena – By one more than the previous one.2. Nikhilam Navatashcaramam Dashatah – All from 9 and last from 10.3. Urdhva-tiryakbhyam – Vertically and crosswise.4. Paraavartya Yojayet – Transpose and adjust.5. Shunyam Saamyassamuccaye – When the sum is the same that sum is zero.6. Anurupye Shunyamanyat – If one is in ratio, the other is zero.7. Sankalana-vyayakalanabhyam – By addition and by subtraction.8. Puranapuranabyham – By the completion and noncompletion.9. Chalana-Kalanabyham – Differences and Similarities.10. Yaavadunam – Whatever the extent of its deficiency.11. Vyashtisamanstih – Part and Whole.12. Shesanyankena Charamena – The remainders by the last digit.13. Sopaantyadvayamantyam – The ultimate and twice the penultimate.14. Ekanyunena Purvena – By one less than the previous one.15. Gunitasamuchyah – The product of the sum is equal to the sum of the product.16. Gunakasamuchyah – The factors of the sum is equal to the sum of the factors [4].3. GUNAKASAMUCHYAH SUTRAIn this method, if we want to multiply two numbers a and b (each 4 bit). Then theirpartial product terms are formed and they are added successively according to the normalmultiplication process using 4 bit adder to obtain the final result. The arrangement to two4 bit numbers is sown below in fig. 1. This figure shows the 4 bits of both numbers a andb denoted as (ܽ଴, ܽଵ, ܽଶ, ܽଷሻ ܽ݊݀ ሺܾ଴, ܾଵ, ܾଶ, ܾଷሻ. The multiplication of these two numbersis shown with their 16 partial product terms. Now 4 bit adder is used to add the termsaccording to the multiplication process to obtain the final result.
  • 3. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME152Fig. 1 Multiplication of two 4 bit numbersNow let us see the flow code to generate these partial product terms using VHDL. The flowchart is shown as below in fig. 2:Fig. 2 Flow Chart of Partial Product generatorStartInitialize a, b (4 bit numbers)PP1 a(1) and bPP2  a(2) and bPP3 a(3) and bInitialize Partial Products PP0to PP3 to zero (8 bits)PP0 a(0) and bStop
  • 4. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME153The scheme for Vedic multiplication is followed as below in fig. 3. In this 4 bit Vedic addersare used to obtain the result. A partial product generator is used to obtain the partial productsafter multiplication of different bits of the numbers.Fig. 3 Flow Chart of Vedic MultiplierStartInitialize Multiplicand X and multiplier Y(both 4 bit) and output (8 bit)Partial Product generator16 partial products generatedVedic 4 bit adderStopVedic 4 bit adderVedic 4 bit adderResult Obtained
  • 5. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME154S0 S1c0 C1SumC2Carry3.1.Vedic 4 bit adderVedic 4 bit adder is used to add 4 bits and thus generating sum bit and a carry bit. Inthis adder two bits are added first to obtain the partial sum and carry bit. Then the remainingtwo bits are added to obtain other partial sum and carry bit. Now to obtain the final sum bitthe partial sum bits are added and in this process a carry bit if present is also generated. Nowthese three partial carry bits are processed to obtain the final carry bit.Fig. 4 Flow Chart of 4 bit Vedic AdderStartInitialize 4 input bits as a0, a1, a2, a3,sum bit and carry out bitAdd first two bits a0and a1Add other two bitsa2 and a3Process c0, c1 andc2StopAdd s0 and s1Result Obtained
  • 6. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME1554. HARDWARE IMPLEMENTATIONThis section presents the hardware design of the system. The schematic diagram ofthe circuit being designed is shown in this section. This section also describes theimplementation of software on the system designed.4.1.Schematic Design of the circuitFig. 5 Schematic Design of the systemSW0SW1SW2SW3L13L14H18N17SPARTAN 3EFPGAXC3S500ELED0LED1LED2LED3LED4LED5LED6LED71001F12E12E11F11C11D11E9F950 MHz Oscillator5 VDC, 2A Supply100-240V AC Input3.3VRegulator2.5VRegulator1.2VRegulator
  • 7. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME156Fig. 6 Complete Setup of the system4.2.Implementation ResultFig. 7 Implementation Result
  • 8. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME1575. CONCLUSIONThe Vedic Multiplier designed here is an efficient and fast multiplier as compared toother multipliers. The number of Look up tables required to implement this multiplier is alsoless as compared to other multipliers. The result of this multiplier is shown below:Fig. 8 Simulation Results of 4 bit Vedic AdderFig. 9 Simulation Results of 4x4 bit Vedic Multiplier
  • 9. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME158The simulation results of 4x4 bit Vedic Multiplier in terms of number of occupied slices,number of 4 inputs LUT and IOBs are shown in Table. 1.Table 1: Xilinx Results for 4x4 bits Vedic MultiplierPARAMETER Used Available UtilizationNumber of 4 input LUTs 16 63400 1%Number of occupied Slices 6 15850 1%Number of bonded IOBs 16 210 7%Thus the result shows that number of 4 input LUTs required is 16 and percentage utilizationof resources is 1%. Similarly other results are shown based on other parameters like numberof occupied slices and number of bonded IOBs.REFERENCES[1] D.Kishore Kumar, A.Rajakumari, Modified Architecture of Vedic Multiplier for HighSpeed Applications, International Journal of Engineering Research & Technology, Vol. 1Issue 6, August – 2012.[2] Pushpalata Verma, K. K. Mehta, Implementation of efficient multiplier based on VedicMathematics using EDA tool, International Journal of Engineering and AdvanceTechnology,Volume-1, Issue-5, June 2012.[3] G.Ganesh Kumar, V.Charishma, Design of high Speed Vedic Multiplier using VedicMathematic Techniques, International Journal of Scientific and Research Publication,Vol 2, Issue 3, March 2012.[4] Ramachandran.S*, Kirti.S.Pande, Design, Implementation and Performance Analysis ofan Integrated Vedic Multiplier Architecture, International journal of ComputationalEngineering Research.[5] Sharada Kesarkar and Prof. Prabha Kasliwal, “FPGA Implementation of Scalable QueueManager”, International Journal of Electronics and Communication Engineering &Technology (IJECET), Volume 4, Issue 1, 2013, pp. 79 - 84, ISSN Print: 0976- 6464,ISSN Online: 0976 –6472.[6] B.K.V.Prasad, P.Satishkumar, B.Stephencharles and T.Prasad, “Low Power Design ofWallance Tree Multiplier”, International Journal of Electronics and CommunicationEngineering & Technology (IJECET), Volume 3, Issue 3, 2012, pp. 258 - 264,ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.