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Fpga implementation of low complexity linear periodically time varying filter

Fpga implementation of low complexity linear periodically time varying filter






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    Fpga implementation of low complexity linear periodically time varying filter Fpga implementation of low complexity linear periodically time varying filter Document Transcript

    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 INTERNATIONAL JOURNAL OF ELECTRONICS AND– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)ISSN 0976 – 6464(Print)ISSN 0976 – 6472(Online)Volume 3, Issue 1, January- June (2012), pp. 130-138 IJECET© IAEME: www.iaeme.com/ijecet.htmlJournal Impact Factor (2011): 0.8500 (Calculated by GISI) ©IAEMEwww.jifactor.com FPGA IMPLEMENTATION OF LOW COMPLEXITY LINEAR PERIODICALLY TIME VARYING FILTER Sriadibhatla Sridevi, Dr. Ravindra Dhuli and Prof. P. L. H. VaraprasadABSTRACT This paper presents a low complexity architecture for a linear periodically timevarying (LPTV) filter. This architecture is based on multi-input multi-output(MIMO)representation of LPTV filters. The input signal is divided into blocks and parallelprocessing is incorporated, there by considerably reducing the effective input samplingrate. A single multiplier can be shared for each linear time invariant (LTI) filter in therepresentation. Each LTI filter is realized in the transposed direct form filter usingmultiplier less multiplication structures based on Binary common bit patterns (BCS). Theproposed structure is simulated, synthesized and implemented on Virtex v50efg256-7Field Programmable Gate Array (FPGA).Index Terms: LPTV, MIMO representation, BCS, FPGA I. INTRODUCTIONLINEAR periodically time varying (LPTV) systems/filters have number of applicationsin many fields such as Control systems, Communications, Signal processing and Circuitmodeling [3], [7], [21], [6]. Spread spectrum applications [6], Trans multiplexing [16],blind channel estimation [18], spectral scrambling [9], temporal scrambling [4], digitalwater marking of natural images [12], sample data systems [21] and multi rate filterbanks [19] are the potential applications. LPTV systems can be expressed as generalization of Linear time invariant (LTI)systems. If the input for a M-period LPTV system is delayed by M samples, output is alsodelayed by the same number of samples. An LPTV system with a period of ’1’ is nothingbut an LTI system [15]. Various equivalent structures for an LPTV filters and their interrelationships were derived in [14]. 130
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME The relations between multi-input multi-output (MIMO) representation andvarious other representations are presented in [15]. Here the authors present a techniqueto transform from the LTI MIMO structure to the original single-input/single-outputLPTV difference equation and discusses its implications. The hardware implementationof the LPTV filters is the area of greater interest now a day. Much of the previous workconcentrated on VLSI implementation of LTI filters. The complexity of LTI filters isdominated by the complexity of coefficient multipliers. R. I. Hartley proposed that thecommon sub expression elimination (CSE) methods based on canonical signed digit(CSD) coefficients will produce low complexity FIR filter coefficient multipliers [8]. In[13], the technique in [8] was modified to minimize the number of adder-steps in amaximal path of decomposed multiplications and thus to improve the speed of operation.In [10], R. Mahesh and A. P. Vinod proposed the Binary Common Sub expression (BCS)elimination algorithm. It resulted in improved adder reductions and thus low complexityFIR filters compared to [8] and [13]. In [20], a method based on the pseudo floating pointmethod was used to encode the filter coefficients and thus to reduce the complexity of thefilter. Implementation approach for reconfigurable FIR filters has been proposed in [17]and [11]. Ref [2], [1] have touched on the VLSI implementation of multi rate FIR filterdesign. In the present work we introduce a novel implementation strategy for an LPTV filterusing the MIMO representation. Any given LPTV filter can be viewed as MIMO LTI system.Thus the analysis of MIMO LTI systems can be directly applied to LPTV systems. If we areconsidering an LPTV system of period M, we will divide the input signal into blocks of size M.We employ parallel processing on this blocks using LTI systems. Hence the effective inputsampling rate reduces by a factor M. After processing the resulting output signals are interlacedequivalently to perform unblocked. Since there is a considerable reduction in the input samplingrate, we can employ single multiplier on shared basis for each LTI filter. In the proposedarchitecture, multiplication is performed without multipliers using Binary Common Bit patterns(BCS) based shift and add units, multipliers and adders. The organization of the paper is as follows. Section II deals with the basics ofLPTV system. Section III explains the proposed LPTV FIR filter design. Simulation andsynthesis results are presented in section IV. Section V concludes the paper. (a) Blocking operator (b) MIMO Representation Fig. 1 Blocking operator and MIMO representation 131
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME II. BASICS OF LPTVA Linear system is called an LPTV system of period M, if a shift of M samples in theinput sequence result in similar shift of M samples in the output sequence. The inputoutput relationship of any linear system is given by the generalization of convolution sumas y (n) = (1) where x(n) and y(n) denote the input and output sequences respectively. Theresponse of the system to an impulse response at n = k is denoted by kernel h(n, k). If thelinear system is an LPTV system, then the kernel satisfies the relation h(n+M, k+M) =h(n, k). An LPTV system can be viewed as an LTI system with increased input andoutput dimension, which is termed as MIMO LTI system. For this MIMO representation,we divide the input and output sequences as blocks of size M. If a block wise shift isintroduced in the input signal, the corresponding shift is observed in the output signalblocks. The blocking effect is given by the multi rate structure shown in Fig. 1(a).If the blocking by a factor M is denoted by BM , we obtain the relation , T Where, The blocking operation is reversible. Thus x . The multi ratesystem corresponding to is represented by the structure shown in Fig. 1(a). Theblocking can be implemented in hardware with the help of a serial to parallel converter.The inverse blocking operation can be realized by a parallel to serial converter orequivalently by a switch. In operator notation, if the LPTV system operator is denoted byH, the input output relation is given by y =Hx. If we block output by BM, we obtain (2) Where denote MIMO LTI corresponding to the LPTV system.xM denote the blocked input sequence and yM denote the resulting blocked outputsequence. Fig. 1(b) show the MIMO representation of LPTV system. The transfer matrixof MIMO LTI is given by H(z). Due to down sampling operation, the input sampling frequency denoted by fs isreduced by a factor M. The input signal dimension in increased by a factor M and parallelprocessing is employed. The LTI filters in the MIMO representation operate at the rate fs/M. However, the output is obtained at fs , but not fs /M. The entries of the transfer matrixare given in terms of the kernel function as (3) 132
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME This relation an be proved by Fig. 1(a) and Fig. 1(b). Interested reader may refer[5].To realize an N-tap, M period LPTV system in MIMO representation M2 LTI filtersconsisting of N/M taps each are required. There are two advantages in this realization.First advantage is that, instead of M number of N-tap filters, we can use M2 number ofN/M-tap filters. This facilitates to run all N/M tap filters in parallel which increases thespeed of operation. All the LTI filters can run at a sampling frequency of fs /M, instead offs. This is the second advantage. Each N/M tap filters requires N/M coefficient multipliersnormally. But as the rate at which multiplier has to operate is reduced by a factor M, wecan use a single multiplier in time sharing basis for all N/M coefficient multiplications.Hence the total number of multipliers required for the entire LPTV system is reducedfrom M × N to only M and this can considerably reduce the area occupied. (a) Shift and Adder architecture (b) Multiplication block III. LOW COMPLEXITY LPTV FIR FILTER DESIGN An N- tap, M- period LPTV filter can be realized by using M2 LTI filters of N/M tapseach. Each LTI filter in the proposed design is in transposed direct form. In the proposeddesign ,the coefficient multiplier of each LTI filter is replaced by a multiplier lessmultiplication block based on Binary Common bit patterns (BCS).The novelmultiplication block can be divided into two units. BCS based shift and add unit andmultiplication unit.A. BCS based Shift and Add Unit An n-bit binary number in general can form 2n Binary Common Bit patterns. Forexample, a 3-bit binary representation can form 8 common bit patterns. They are (000),(001), (010), (011), (100), (101), (110), (111). The common bit patterns like (001), (010)and (100) do not require any adder for their implementation as they have a single nonzero bit. The bit pattern (000) does not need an adder or a shifter. Considering x as inputsignal, the remaining bit patterns can be expressed as follows 133
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME (011) = 2−1x + 2−2x (101) = x + 2−2x (4) (110) = x + 2−1x (111) = x + 2−1x + 2−2x To realize the above Binary Common Bit patterns, five adders are required.However, if we perform some simplifications such as 2-1x + 2−2x = 2−1(x + 2−1x) and x+[2-1x+2-2x ] = x+ 2-1 x+2-2x, then all the BCSs can be realized with a minimum of threeadders . The number of adders required to realize all the possible n-bit common binary bitpatterns is 2n-1-1. The architecture of shift and add unit is shown in Fig. 2(a). All the eightBCS are fed to the multiplication block.B . Multiplication Block The architecture of multiplication block is shown in Fig. 2(b). The coefficientword length is 16 bits .The filter coefficients are stored in the coefficient memory in signmagnitude form with most significant bit representing the sign bit. Each 16 bit coefficientis stored as 17 bit value in coefficient memory. Each row in the memory corresponds toone coefficient. The coefficient values corresponding to 20 to 2−14 are partitioned intogroups of three bits and they are used as select signals to multiplexers MUX1 to MUX5.It is easy to note that MUX1 to MUX5 are 8:1 multiplexers as they have three selectlines. The value corresponding to 2−15 forms the select line to a 2:1 multiplexer. Let r1 tor6 denote the outputs of MUX1 to MUX6 respectively. Then the output is given by TABLE I MACRO-STATISTICS TABLE II SYNTHESIS RESULTS 134
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME (5) The shifts in Eq.(5) are obtained by partitioning the 16 bit coefficient into groupsof 3 bits as shown in Eq. (6). Then we get (6)The sums , and are obtained by the three addersA1, A2, A3 and respectively three shifters. The outputs of adders are designated as r7, r8and r9 and now (7)The sum is obtained from adder A4 and a shifter is represented as r10 andnow (8)Adder A5 along with a shifter will provide the sum and it is r11 andfinally (9) The required shift is obtained by a shifter. The complement of y is obtained by acomplementor. MUX7 is a 2:1 multiplexer and it decides whether the output need to becomplemented based on the sign bit of the filter coefficient. The main advantage of thisstructure is that all the shifts provided here are constants irrespective of the coefficientsand so easy to implement and also result in high speed as they can be hardwired. Hence the proposed LPTV structure consisting of M2 LTI filters, each running ata reduced sampling frequency fs /M involving M number of multiplier lessmultiplication blocks, consumes less power and occupies smaller area comparatively. IV. SIMULATION AND SYNTHESIS RESULTSA 32-tap 4-period LPTV filter is designed by using sixteen 8-tap LTI filters in MIMOrepresentation. All the filters are designed with finite impulse response (FIR) coefficients.The sampling frequency is 10 MHz, but because of MIMO structure the input sampling isdivided by M=4 and each LTI FIR filter operates at 2.5 MHz The output frequency isstill 10 MHz because 135
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEMEof the interlacing at the output end. The simulation results are shown in Fig. 3. The inputsignal x is given to the blocking operation resulting in four blocked signals x1,x2,x3,x4. InFig 1(b), the array of down samplers performs the blocking operation. It is easy to notethat the sample values at four consecutive pulses are 7F, 7C, 7C and 78. So afterblocking, we obtain x1=7F, x2=7C, x3=7C and x4=78. The blocked inputs are given toFIR filters. The MIMO filtering in Fig. 1(b) is performed. After filtering we obtain theoutputs yij , where i,j = 1,2,3,4. We combined outputs and obtain y1, y2, y3 and y4 usingthe relation . It can be noted that the unblocking operation with the array ofup samplers perform the interlacing. Hence, we interlaced y1, y2, y3 and y4 and obtainedfinal output y. We can correlate these operations from Fig. 3 containing the simulationresults. We synthesized LPTV FIR filters of two different structures. Conventional designconsists of multipliers in LTI filter blocks whereas our proposed design utilizes multiplierless Multiplication blocks based on BCS. The two designs are synthesized andimplemented on virtex v50efg256-7 FPGA. Table I and Table II present the synthesisresults. The synthesis results show that our proposed design occupies smaller area andconsumes less power comparatively.V. CONCLUSIONWe proposed a low area complexity LPTV filter in MIMO representation with transposeddirect form LTI FIR filter blocks .We designed LPTV filters in two different structures.Both the structure are Simulated, synthesized and implemented on Virtex v50efg 256 -7FPGA .Synthesis results show that Design2 ,which is a novel multiplier less LPTVsystem will occupy smaller area and consumes less power comparatively. 136
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME Fig. 3 Simulation resultsREFERENCES[1] K.H. Abed and S.B. Nerurkar. Implementation of a low power decimation filter using1/3-band iir filter. In Wireless Communications and Networking, 2003. WCNC 2003.2003 IEEE, volume 1, pages 460–465. IEEE, 2003.[2] D.C. Andreas. Vlsi implementation of a one-stage 64: 1 fir decimator. In 89thConvention of the Audio Engineering Society, J. Audio Eng. Soc.(Abstracts), volume 38,page 872, 1990.[3] W. Chauvet, B. Cristea, B. Lacaze, D. Roviras, and A. Duverdier. Design oforthogonal lptv filters: Application to spread spectrum multiple access. In Acoustics,Speech, and Signal Processing, 2004. Proceedings.(ICASSP’04). IEEE InternationalConference on, volume 2, pages ii–645. IEEE, 2004.[4] W. Chauvet, B. Lacaze, D. Roviras, and A. Duverdier. Spreading properties ofperiodic clock changes application to interleavers. Signal Processing, 88(2):221–235,2008.[5] Ravindra Dhuli and Brajesh Lall, Generalized poly phase identity. In the proceedingsof INDICON 09,DAIICT,Gandhinagar,India,December 2009.[6] A. Duverdier and B. Lacaze. Transmission of two users by means of periodic clockchanges. In Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998IEEE International Conference on, volume 3, pages 1825–1828. IEEE, 1998. 137
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