Enrichment towards the design of efficient 4 bit reversible subtractor 2
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    Enrichment towards the design of efficient 4 bit reversible subtractor 2 Enrichment towards the design of efficient 4 bit reversible subtractor 2 Document Transcript

    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 1 ENRICHMENT TOWARDS THE DESIGN OF EFFICIENT 4 BIT REVERSIBLE SUBTRACTOR USING TR GATE: A LOW POWER APPLICATION Amit Nigam Dept. of Electronics and Communication Engineering, Ansal Institute of Technology and Management, Lucknow, Uttar Pradesh, India ABSTRACT Reversible logic has widespread employments in quantum computing and low power VLSI design. In the intended work, I will put forward the design, synthesis and simulation of novel reversible subtractor to submit an application of reversible logic. The reversible plan, synthesis and simulation of a 4 bit subtractor will be verified using a reversible TR gate. Idyllically, reversible circuits squander nil energy i.e. zero energy. Thus, it would be of enormous significance to apply reversible logic to designing. The projected effort will be coded in VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using Xilinx ISE Design Suite 14.5. Keywords: Reversible Logic, Reversible subtractor, And Reversible design: low power application. I. INTRODUCTION Reversible logic has got ample implementations in micro-electronics, in the designing of reversible processors. Similar approaches of reversible logic that are used differently are used in ballistic computations, Mechanical computations, Cellular automata in their basis technologies. Sometimes null convention logic is also thought over as partially reversible logic. Clock-less logic is a technique that leads to circuits that run just as fast as normal synchronous CMOS Boolean logic, but use less power. They might be thought over as orthogonal approaches. It is generally believed as the information talked about in thermodynamics is dissimilar to information talked about in INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) ISSN 0976 – 6464(Print) ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August, 2013, pp. 01-12 © IAEME: www.iaeme.com/ijecet.asp Journal Impact Factor (2013): 5.8896 (Calculated by GISI) www.jifactor.com IJECET © I A E M E
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 2 informatics, which is a wrong concept as they are identical. As just as similar to the concept of thermodynamic entropy, the information entropy is also a known concept. The inverter logic gates or the like such as the NOT, CNOT and TOFFOLI gates [10] are the typical reversible logic gates as the input can be retrieved and achieved. The tree input version of the CNOT gate is the TOFFOLI gate. It keeps two of its inputs intact and replaces the third C by A XOR B. With c=0, the output is the same as that of an AND function and with A.B =1 , it gives a NOT function. The C-NOT gate can be defined as the one that preserves one of its inputs. The Toffoli gate is a universal gate and can implement any reversible Boolean Function with zero initialized ancillary bits. The connection in a reversible circuit has got an equal number of inputs and outputs wires each going through the circuit. The practical improvements of bit manipulation transforms in computer graphics and Cryptography are considerations of zero energy consumption. Reversible circuits have applications in quantum mechanics in designing of quantum algorithms and in photonic and Nano-computing technologies in recent times where no signal gain has been offered by some switching devices. The construction and optimization of reversible circuits or loss less circuits as they have come to be known as over the years is a major area under research. Reversible logic is materializing as a promising computing model with applications in up- and-coming technologies such as quantum computing, quantum dot cellular automata, optical computing, etc. [3, 4, 5, 11, 12, 13]. Reversible circuits can engender exclusive output vector from each input vector, and vice versa, that is, there is a one-to-one mapping relating the input and output vectors. Landauer has shown in [1] that for irreversible logic computations, each bit of information lost, generates kTln2 joules of heat energy, where k is Boltzmann’s constant and T the absolute temperature at which computation is executed. Bennett showed that kTln2 energy dissipation would not occur, if a computation is conceded out in a reversible way [2], since the quantity of energy debauched in a system bears a direct connection to the number of bits rubed out while performing the computation. This makes reversible logic in demand for low power VLSI circuits effective even outside the thermodynamic restrictions of computation [8, 7]. In [6], several designs for binary subtractors are examined based on the Fredkin and Feynman gates [9, 10]. These gates are prevalently used in reversible logic design. II. REVERSIBLE TR GATE TR gate is a 3 inputs 3 outputs gate comprising the inputs to outputs mapping as (P=A, Q=A xor B, R= (A.B’) xor C), here A, B, C are the contributions and P, Q, R are the productions, respectively. Figure 1 shows the TR gate and Table 1 shows its truth table. Figure 1: Reversible TR gate
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 3 Table 1: Truth Table of TR gate A B C P Q R 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 0 1 0 0 1 1 1 1 0 1 III. REVERSIBLE SUBTRACTORS USING TR GATE We used TR gate to design the binary subtractors such as half subtractor, full subtractor and parallel subtractor. HALF SUBTRACTOR Let A and B represented in the TR Gate diagram be the two binary numbers required for the input of the Half subtractor. Then the realization of the TR Gate as a Half Subtractor is shown in the Figure 2. While Table 1 shows the truth table of the half subtractor. Figure 2: TR gate Based Design of Reversible Half Subtractor Table 2: Truth Table of Half Subtractor A B Borr. (R) Diff. (Q) 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 4 FULL SUBTRACTOR To subtract three binary numbers, one can use full subtractor which realizes the operation Y=A-B-C. The truth table of the full subtractor is shown in Table 3. Let A, B and C represented in the TR Gate diagram be the three binary numbers required for the input of the Full subtractor. Then the realization of the TR Gate as a Full Subtractor is shown in the Figure 3 via the two Half subtractors realized from the TR Gate. Figure 3: TR gate Based Design of Reversible Full Subtractor Table 3: Truth Table of Full Subtractor A B C Diff. (Q) Borr. (R) 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 PARALLEL SUBTRACTOR The four bit parallel subtractor subtracts a 4 bit number Y from a 4 bit number X. Thus, it can be designed from 1 reversible half subtractor (RHS) and 3 reversible full subtractors (RFS). Figure 4 shows the reversible design of 4 bit parallel subtractor [14] subtracting 4 bit number Y from 4 bit number X. Here RHS and RFS refers to reversible half subtractor and reversible full subtractor, respectively, designed from TR gate, g1 to g7 represents the garbage outputs. In the design B1 to B4 represents the borrow and D0 to D3 represents the difference.
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 5 Figure 4: TR gate Based Design of Reversible Parallel Subtractor IV. RTL AND TECHNOLOGY VIEW OF REVERSIBLE SUBTRACTORS USING TR GATE The projected effort after the coding in VHDL (Very High Speed Integrated Circuits Hardware Description Language), is synthesized and simulated using Xilinx ISE Design Suite 14.5. Thus, generating the RTL view of the reversible TR Gate (Figure 5), reversible half subtractor (Figure 6), reversible full subtractor (Figure 7), reversible four bit parallel subtractor using the half adder and full adders (Figure 8) and reversible four bit parallel subtractor using the TR Gate (Figure 9), and also the technology view of the reversible four bit parallel subtractor (Figure 10). Figure 5:RTL View of Reversible TR gate
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 6 Figure 6: RTL View of TR gate Based Design of Reversible Half Subtractor Figure 7: RTL View of TR gate Based Design of Reversible Full Subtractor
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 7 Figure 8: RTL View of Reversible Parallel Subtractor
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 8 Figure 9: RTL View of TR gate Based Design of Reversible Parallel Subtractor
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 9 Figure 10: Technology View of TR gate Based Design of Reversible Parallel Subtractor
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 10 V. SIMULATION RESULT OF THE TR GATE BASED REVERSIBLE SUBTRACTOR The following are the simulation result of the half subtractor (figure 11), full subtractor (figure 12), and the four bit parallel subtractor (figure 13), by means of the XILINX ISE Design Suite 14.5. This paper uses VHDL as a design entity, and their Synthesis by Xilinx Synthesis Tool on Vertex kit has been done. The input of the reversible parallel subtractor has been given by a PS2 KEYBOARD using a test bench and output has been displayed using the waveforms on the Xilinx Design Suite 14.5. The simulation result obtained in Xilinx ISE Design Suite 14.5 shows the Advanced HDL Synthesis Report for the Xilinx Vertex 7 XC7VX485T, package FFG1761, speed grade -2 (Table 4) . Table 4: Synthesis report of the 4 bit reversible parallel subtractor Figure 11: Simulation result of TR gate Based Reversible Half Subtractor Figure 12: Simulation result of TR gate Based Reversible Full Subtractor
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 11 Figure 13: Simulation result of TR gate Based Reversible Parallel Subtractor
    • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 12 REFERENCES [1] R. Landauer, “Irreversibility and Heat Generation in the Computational Process”, IBM J. Research and Development, 5, pp. 183-191, 1961. [2] C.H. Bennett, “Logical Reversibility of Computation”, IBM J. Research and Development, pp. 525-532, November 1973. [3] A.N. Al-Rabadi, “Reversible Logic Synthesis: From Fundamentals to Quantum Computing”, Springer- Verlag, New York, First Edition, 2004 [4] V. Vedral, A. Bareno and A. Ekert, “Quantum Networks for Elementary Arithmetic Operations”. arXiv:quant-ph/9511018 v1. (nov 1995) [5] H. Thapliyal and N. Ranganathan, "Reversible Logic Based Concurrently Testable Latches for Molecular QCA", To appear IEEE Trans. on Nanotechnology, 2009. [6] H. Thapliyal, M.B Srinivas and H.R Arabnia, “Reversible Logic Synthesis of Half, Full and Parallel Subtractors”, Proc. of the 2005 Intl. Conf. on Embedded Systems and Applications, June 2005, Las Vegas, pp.165-181. [7] M.P Frank, “Introduction to reversible computing: motivation, progress, and challenges”, Proc. of the 2nd Conf. on Computing Frontiers, 2005, pp 385–390. [8] A. D. Vos and Y. Van Rentergem, “Power consumption in reversible logic addressed by a ramp voltage”, Proc. of the 15th Intl. Workshop Patmos 2005, Lecture Notes of Computer Science, vol. 3728, pp. 207-216, Springer- Verlag, Oct 2005. [9] E. Fredkin, T Toffoli, “Conservative Logic”, Int. J. Theor. Phys, vol. 21, no. 3–4, pp. 219–253, 1982. [10] T. Toffoli, “Reversible Computing”, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980). [11] H. Thapliyal and N. Ranganathan, "Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits", Proc. of the 22nd Intl. Conf. on VLSI Design, New Delhi, India, Jan 2009, pp. 511- 516 [12] H. Thapliyal and N. Ranganathan, "Testable Reversible Latches for Molecular QCA", Proc. of the 8th Intl. Conf. on Nanotechnology, Arlington, TX, Aug 2008, pp. 699-702. [13] X. Ma, J. Huang, C. Metra, F.Lombardi, “Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA”, Springer Journal of Electronic Testing, Vol. 24, No. 1-3, pp.297-311, Jan 2008. [14] Himanshu Thapliyal, Nagarajan Ranganathan, “Design of Efficient Reversible Binary Subtractors Based on A New Reversible Gate”, 2009 IEEE Computer Society Annual Symposium on VLSI. [15] Y.Varthamanan and V.Kannan, “Performance Evaluation of Reversible Logic Based Cntfet Demultiplexer”, International Journal of Electrical Engineering & Technology (IJEET), Volume 4, Issue 3, 2013, pp. 53 - 62, ISSN Print : 0976-6545, ISSN Online: 0976-6553.