Design of area optimized aes encryption core using pipelining technology
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Design of area optimized aes encryption core using pipelining technology Document Transcript

  • 1. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME308DESIGN OF AREA OPTIMIZED AES ENCRYPTION CORE USINGPIPELINING TECHNOLOGYAnubhav Gupta1, Harish Bansal21Student M.Tech(VLSI), M.M Engineering College, Maharishi Markandeshwar University,Mullana (Ambala)2Asstt. Prof. M.M Engineering College, Maharishi Markandeshwar University, Mullana(Ambala)ABSTRACTA new pipelining technology based design scheme of the AES-128 (AdvancedEncryption Standard, with 128-bit key) encryption algorithm is proposed in this paper. Formaintaining the speed of encryption, the pipelining technology is applied and the mode ofdata transmission is modified in this design so that the chip size can be reduced. The 128-bitplaintext and the 128- bit initial key, as well as the 128-bit output of cipher text, are alldivided into four 32-bit consecutive units respectively controlled by the clock. The synthesisverification based on HJTC0.18um CMOS process shows that this new program cansignificantly decrease quantity of chip pins and effectively optimize the area of chip.Keywords: Area optimization; Pipelining; VHDL.1. INTRODUCTIONThe number of individuals and organizations using wide computer networks forpersonal and professional activities has recently increased a lot. A cryptographic algorithm isan essential part in network security. With the rapid development and wide application ofcomputer and communication networks, the information security has aroused high attention.Information security is not only applied to the political, military and diplomatic fields, butalso applied to the common fields of people’s daily lives. With the continuous developmentof cryptographic techniques, the long-serving DES algorithm with 56-bit key length has beenbroken because of the defect of short keys. The "Rijndael encryption algorithm" invented byBelgian cryptographers Joan Daemen and Vincent Rijmens had been chosen as the standardINTERNATIONAL JOURNAL OF ELECTRONICS ANDCOMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)ISSN 0976 – 6464(Print)ISSN 0976 – 6472(Online)Volume 4, Issue 2, March – April, 2013, pp. 308-314© IAEME: www.iaeme.com/ijecet.aspJournal Impact Factor (2013): 5.8896 (Calculated by GISI)www.jifactor.comIJECET© I A E M E
  • 2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME309AES (Advanced Encryption Standard) algorithm whose packet length is 128 bits and the keylength is 128 bits, 192 bits, or 256 bits. Since 2006, the Rijndael algorithm of advancedencryption standard has become one of the most popular algorithms in symmetric keyencryption. AES can resist various currently known attacks.Hardware security solution based on highly optimized programmable FPGA providesthe parallel processing capabilities and can achieve the required encryption performancebenchmarks. The current area-optimized algorithms of AES are mainly based on therealization of S-box mode and the minimizing of the internal registers which could save thearea of IP core significantly.In this paper, we present an design of the AES block cipher with pipeliningtechnology. We have exploited the temporal parallelism available in the AES algorithm. Ourchip contains the same ten units, and each unit can execute one round of the algorithm. Usingexternal pipelined design, ten rounds of the algorithm are executed in parallel in a chip.Furthermore, using internal pipelining and key exchange pipelining, pipelining technologywas utilized in the intermediate nine round transformations so that the new algorithmachieved a balance between encryption speed and chip area, which met the requirements ofpractical application.The results show that this new algorithm with pipelining technology and special modeof data transmission can significantly decrease the quantity of chip pins and reduce the chiparea.2. AES OVERVIEWAES is a symmetric cipher that processes data in 128-bit blocks. It supports key sizesof 128, 192, and 256 bits and consists of 10, 12, or 14 iteration rounds, respectively. Eachround mixes the data with a roundkey, which is generated from the encryption key.Decryption inverts the iterations resulting in a partially different data path.The steps involved are given below:1. Key Expansion using Rijndaels key schedule2. Initial Roundo AddRoundKey3. Roundo Sub Bytes—a non-linear substitution step where each byte is replaced with anotheraccording to a lookup table.o Shift Rows—a transposition step where each row of the state is shifted cyclically a certainnumber of steps.o Mix Columns—a mixing operation which operates on the columns of the state,combining the four bytes in each columno AddRoundKey—each byte of the state is combined with the round key; each round key isderived from the cipher key using a key schedule.
  • 3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME310Figure 1. AES round operations4. Final Round (no Mix Columns)o Sub Byteso Shift Rowso AddRoundKeyThis is the iterative looping architecture of the AES. VHDL code is written for the AESencryption algorithm for finding cipher for any given plaintext input.3. RELATED WORKAfter the ratification of AES, a large number of its hardware implementations haveappeared. Whereas the earlier designs mainly focused on intensively pipelined, high-speedimplementations, the more recent work has concentrated on compact and low-powerarchitectures considering low-cost devices and feedback modes of operation.Basically pipelining means to process the data that is given as input in a continuousmanner without having to wait for the current process to get over. This pipelining concept isseen in many processors. In the architecture in the registers are used to store the currentoutput of the round that is being executed. Now instead of passing the output of each round tothe next round directly we use a register which would act as a bypass or an internal register.Since the current rounds value is stored in the register the next input to the current round canbe given as soon as the current output is obtained. And the input to the next round is givenfrom the register thus avoiding a direct contact between the two rounds. This is not possiblein the iterative looping architecture because the next input can be given only when the whole
  • 4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME311round based processing is over since the same hardware is used over and again in the processof obtaining the cipher text. Thus, the pipelined architecture increases the speed of executionfor obtaining the cipher text but at a cost of increased hardware. In the substitute bytes we usea look up table based S-box. This contributes for some of the hardware in the form of blockRAMs. With the help of a search based look up table (LUT) we can reduce the hardware costto a considerable extent.From the above analysis, we can find that the process of AES encryption can bemainly divided into two parts: key schedule and round transformation. The improvedstructure is also divided into these two major processes.The initial key will be sent to the two modules: Keyexpansion and Keyselection,while the plaintext is to be sent to the round transformation after the roundkey is selected. Butthe operand of data transmission is turned into a 32-bit unit.Figure 2. The new improved structure of AES algorithmThe functions of various parts of the structure shown above are described as follow:1. The initial round of encryption:The four packets of consecutive 32-bit plaintext (128 bits) have been put into thecorresponding registers. Meanwhile, another four packets of consecutive 32-bit initial key(128 bits) have been put into other registers by the control of the enable clock signal.Furthermore, this module should combine the plaintext and initial key by using the XORoperators.2. Round Transformation in the intermediate steps:A round transformation mainly realizes the function of SubBytes and MixColumns with 32-bit columns. Four packets of round transformation are processed independently. Then theresults of MixColumns and the 32-bit keys sourced from Keyexpansion are combined byusing XOR operators. Here, the round transformation is a module with 64 input ports (32- bitplaintext+32-bit key) and 32 output ports.The function of SubByte is realized by Look-Up Table (LUT). It means that the operation iscompleted by the Find and Replace after all replacement units are stored in a memoy(256×8bit = 1024 bit).
  • 5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME312The implementation of MixColumn is mainly based on the mathematical analysis in theGalois field GF(28). Only the multiplication module and the 32-bit XOR module of eachprocessing unit (one column) are needed to design, because the elements of the multiplicationand addition in Galois field are commutative and associative. Then the function ofMixColumn can be achieved.4. FUNCTIONAL SIMULATION AND SYNTHESISIn this paper, the new structure of AES-128 encryption algorithm introduced above isimplemented with VHDL hardware description language, while minimizing the input /outputports to save redundant area of the chip. The V file named aes_control in the project of thedesign contains the input and output ports, interface converters and controllers. Otherfunction modules are described in independent V files respectively. We used ModelSim SEPLUS 6.0 for the waveform simulation platform and verified the results.The Simulation in the Modelsim SE PLUS 6.0 PlatformFirstly, all project files of the design were compiled in Modelsim SE PLUS 6.0simulation platform. If the files were all compiled successfully, the simulated waveformscould be obtained when loading the test file test_bench_top. Figure shows the simulationwaveform of the new algorithmFigure 3. The 32-bit plaintext, 32-bit initial key and 32-bit cyphertextThe initial 128-bit input tmp0 sequences are extracted to four 32-bit words as theplaintext (128bit) meanwhile, the 128-bit input sequences tmp1 are extracted to four 32-bitwords as initial key (128bit); the sequences of tmp2(128bit) are the correct ciphertext data,which is used for validating the correctness of the new encryption scheme. We found that theinput in0 of four continuous state words and 128 bits plaintext tmp0 express the same by thecontrol signal of en; four consecutive state-words of input in1 are consistent with 128 bitskey. After a complete process of AES encryption, the output stream data_out_32 exports fourcontinuous 32-bit sequences, which are consistent with the 128bits ciphertext tmp2. Inconclusion, the logic function of improved algorithm is correct and it satisfies therequirement of AES encryption algorithm.
  • 6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME313Above table shows that the logic elements of the new improved structure increase andthe total registers is more than twice of the original quantity. The reason lies on thesegmentation of data in the Round Transformation. The pipelining process of four 32-bitpackets data needs more registers than before. A certain clock delay will be produced in theencryption process, because of the processing mode of packets. So the pipelining technologyis used in the round transformation, ensuring that the encryption speed meets the actualdemand.The pipelining technology and 32-bit packet segmentation greatly reduces the area of thechip.Dynamic power consumption accounts for the majority of the circuit power consumption, andthe dynamic power is relatively reduced compared with the unimproved algorithms, and theencrypted rate decreases. However, this clock delay is acceptable and still meets theapplication requirement.5. CONCLUSIONA design using pipelining technology for area-optimized AES algorithm which meetsthe actual application is proposed in this paper. After being coded with VHDL HardwareDescription Language, the waveform simulation of the new algorithm was taken in theModelSim SE PLUS 6.0. Ultimately, a synthesis simulation of the new algorithm has beendone. The result shows that the design with the pipelining technology and special datatransmission mode can optimize the chip area effectively. Meanwhile, this design reducespower consumption to some extent, for the power consumption is directly related to the chiparea. Therefore the encryption device implemented in this method can meet some practicalapplications.
  • 7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME314REFERENCES[1] J.Yang, J.Ding, N.Li and Y.X.Guo, “FPGA-based design and implementation of reducedAES algorithm” IEEE Inter.Conf. Chal Envir Sci Com Engin(CESCE).,Vol.02, Issue.5-6,pp.67-70, Jun 2010.[2] A.M.Deshpande, M.S.Deshpande and D.N.Kayatanavar,“FPGA Implementation of AESEncryption and Decryption”IEEEInter.Conf.Cont,Auto,Com,and Ener., vol.01, issue04, pp.1-6,Jun.2009.[3] Hiremath.S. and Suma.M.S.,“Advanced Encryption Standard Implemented on FPGA”IEEE Inter.Conf. Comp Elec Engin. (IECEE), vol.02,issue.28,pp.656-660,Dec.2009.[4] Abdel-hafeez.S.,Sawalmeh.A. and Bataineh.S.,“High Performance AES Design usingPipelining Structure over GF(28)” IEEE Inter Conf.Signal Proc and Com.,vol.24-27, pp.716-719,Nov. 2007.[5] Rizk.M.R.M. and Morsy, M., “Optimized Area and Optimized Speed HardwareImplementations of AES on FPGA”, IEEE Inter Conf. Desig Tes Wor.,vol.1,issue.16,pp.207-217, Dec. 2007.[6] Liberatori.M.,Otero.F.,Bonadero.J.C. and Castineira.J. “AES-128 Cipher. High Speed,Low Cost FPGA Implementation”, IEEE Conf. Southern Programmable Logic(SPL),vol.04,issue.07,pp.195-198,Jun. 2007.[7] Abdelhalim.M.B., Aslan.H.K. and Farouk.H. “A design for an FPGAbasedimplementation of Rijndael cipher”,ITICT. Ena Techn N Kn Soc.(ETNKS), vol.5,issue.6,pp.897-912,Dec.2005.[8] D. Canright. A very compact S-box for AES. In Proc.7th Int. Workshop on CryptographicHardware and EmbeddedSystems (CHES 2005), pages 441–455, Edinburgh, UK, Aug. 29–Sept. 1, 2005.[9] P. Chodowiec and K. Gaj. Very compact FPGA implementation of the AES algorithm. InProc. 5th Int. Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003),pages 319–333, Cologne, Germany, Sept. 8–10, 2003.[10] S. Farhan, S. Khan, and H. Jamal. Mapping of high-bit algorithm to low-bit foroptimized hardware implementation. InProc. 16th IEEE Int. Conf. on microelectronics (ICM 2004),pages 148–151, Tunis, Tunisia,Dec. 6–8, 2004.[11] M. Feldhofer, S. Dominikus, and J. Wolkerstorfer. Strong authentication for RFIDsystems using the AES algorithm. In Proc. 6th Int. Workshop on Cryptographic Hardwareand Embedded Systems (CHES 2004), pages 357–370, Boston, MA, USA, Aug. 11–13,2004.[12] Sandeep Bidwai, Saylee S. Bidwai, Dr.S.P.Patil and Sunita S. Shinde, “Implementation& Performance Analysis of Cordic in OFDM Based Wlan System Using VHDL”,International Journal of Electronics and Communication Engineering & Technology(IJECET), Volume 3, Issue 3, 2012, pp. 103 - 111, ISSN Print: 0976- 6464, ISSN Online:0976 –6472.[13] Nilesh P. Bodne and A.A. Kelkar, “VHDL Modeling for Wi-Fi Mac Layer Transmitterand Receiver”, International Journal of Electronics and Communication Engineering &Technology (IJECET), Volume 3, Issue 1, 2012, pp. 171 - 177, ISSN Print: 0976- 6464,ISSN Online: 0976 –6472.