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Design of 64 bit error tolerant adder
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Design of 64 bit error tolerant adder

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    Design of 64 bit error tolerant adder Design of 64 bit error tolerant adder Document Transcript

    • INTERNATIONAL JOURNAL OF ADVANCED RESEARCH INInternational Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME ENGINEERING AND TECHNOLOGY (IJARET)ISSN 0976 - 6480 (Print) IJARETISSN 0976 - 6499 (Online)Volume 3, Issue 2, July-December (2012), pp. 235-247© IAEME: www.iaeme.com/ijaret.asp ©IAEMEJournal Impact Factor (2012): 2.7078 (Calculated by GISI)www.jifactor.com DESIGN OF 64 BIT ERROR TOLERANT ADDER 1A.S.Prabhu, 2V.Elakya,3A.Andamuthu and 4 N.Vignesh 1 Asst Prof, VLSI Design, EBET Group of Institutions, Kangayam, Tamil Nadu, India. Mail id: prabhu.mevlsi@gmail.com 2 Asst Prof, VLSI Design, Angel College of Engineering and Technology, Tirupur, Tamil Nadu, India. Mail id: elakya17@gmail.com 3 Asst Prof, VLSI Design, Muthayammal Engineering College, Rasipuram, Tamil Nadu, India. Mail id : andamuthuece@gmail.com 4 Asst Prof, VLSI Design, Karpagam College of Engineering and Technology, Tamil Nadu, India. Mail id : vickee76@gmail.com ABSTRACT Adders are the core element of complex arithmetic operations like addition, multiplication, division, exponentiation etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. This project introduces the design of low power error tolerant adder which acquires less area with the lowest transistor count. Enhanced performance of the proposed Error Tolerant adder in terms of power makes it suitable for portable image processing applications where minimum percentage of error is tolerable. The low power error tolerant adder circuit design and the simulation have been carried out on T a n n e r EDA tool. The result shows that t h e proposed low power error tolerant adder is an efficient adder cell with less MOS transistor count that reduces the high power consumption and it considerably increases the speed. Index Terms—Adders, Error Tolerant adder, low power, error tolerant INTRODUCTION The design of error tolerant adder consists of accurate part and inaccurate part. in accurate part the conventional ripple carry adder is replaced by the ripple carry adder designed using 8 transistor full adder. In the inaccurate part the 3 transistor XOR logic is used in the modified XOR gate. The power comparison is made between the existing design and the proposed method [2]. PROPOSED METHOD OF ETA BLOCK DIAGRAM The block diagram of the hardware implementation of such an ETA that adopts our proposed addition arithmetic is provided in Figure 4.1. This most straightforward structure consists of two parts: an accurate part and an inaccurate part. The accurate part is constructed using a conventional adder such as the RCA. The carry-in pin of this adder is connected to ground. The inaccurate part constitutes two blocks: a carry-free addition block and a control block. The Control block is used to generate the control 235
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEMEsignals, to determine the working mode of the carry-free Addition block. A 64-bit adder is used as anexample for illustration of the design methodology and circuit implementation of an ETA [1]. Figure 1: Hardware Implementation of the Proposed ETA. DESIGN OF 64 BIT ERROR TOLERANT ADDER Strategy of Dividing the Adder The first step of designing a proposed ETA [2] is to divide the adder into two parts in a specific manner. The dividing strategy is based on a guess- and-verify stratagem, depending on the requirements, such as accuracy, speed, and power. First, we define the delay of the proposed adder as Td = max (Th, Tl), where Th is the delay in the accurate part and Tl is the delay in the inaccurate part. With the proper dividing strategy, we can make Th approximately equal to Tl and hence achieve an optimal time delay. With this partition method defined, we then check whether the accuracy performance of the adder meets the requirements preset by designer/ customer. This can be checked very quickly via some software programs. For example, for a specific application, we require the minimum acceptable accuracy to be 95% and the acceptance probability to be 98%. The proposed partition method must therefore have at least 98% of all possible inputs reaching an accuracy of better than 95%. If this requirement is not met, then one bit should be shifted from the inaccurate part to the accurate part and have the checking process repeated. Also, due to the simplified circuit structure and the elimination of switching activities in the inaccurate part, putting more bits in this part yields more power saving. Having considered the above, we divided the 64-bit adder by putting 24 bits in the accurate part and 40 bits in the inaccurate part. Design of the Accurate Part In our proposed 64-bit ETA [1], the inaccurate part has 40 bits as opposed to the 24 bits used in the accurate part. The overall delay is determined by the inaccurate part, and so the accurate part need not be a fast adder. The ripple-carry adder, which is the most power-saving conventional adder[7], has been chosen for the accurate part of the circuit. The conventional ripple carry adder is replaced by the ripple carry adder designed using 8 transistor full adder. The power is drastically reduced by using 8 transistor full adders [8]. 236
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME Design of the Inaccurate Part The inaccurate part is the most critical section in the proposed ETA [1] as it determines the accuracy, speed performance, and power consumption of the adder. The inaccurate part consists of two blocks: the carry free addition block and the control block. The carry-free addition block is made up of 40 modified XOR gates, and each of which is used to generate a sum bit. The block diagram of the carry-free addition block and the schematic implementation of the modified XOR gate are presented in Figure 1. In the modified XOR gate [6], three extra transistors, M1, M2, and M3, are added to a 3 transistor XOR gate. CTL is the control signal coming from the control block of Figure 2 and is used to set the operational mode of the circuit. When CTL = 0, M1 and M2 are turned on, while M3 is turned off, leaving the circuit to operate in the normal XOR mode. When CTL = 1, M1 and M2 are both turned off, while M3 is turned on, connecting the output node to DD, , and hence setting the sum output to “1”. Figure 2: Carry-Free Addition Block. (a) Overall Architecture and (b) Schematic Diagram of a Modified XOR Gate. 237
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME The function of the control block is to detect the first bit position when both input bits are “1,”and to set the control signal on this position as well as those on its right to high. It is made up of 40control signal generating cells (CSGCs) and each cell generates a control signal for the modified XORgate at the corresponding bit position in the carry-free addition block. Instead of a long chain of 40cascaded GSGCs [3], the control block is arranged into ten equal-sized groups, with additionalconnections between every two neighboring groups. Two types of CSGC, labeled as type I and II inFigure 2 (a) are designed, and the schematic implementations of these two types of CSGC are provided inFigure 2(b). The control signal generated by the leftmost cell of each group is connected to the input ofthe leftmost cell in next group. The extra connections allow the propagated high control signal to “jump”from one group to another instead of passing through all the 40 cells. Figure 3: Control Block. (a) Overall Architecture and (b) Schematic Implementations of CSGC.3T XOR Gate The design of 3T XOR gate is shown in figure 4. The heart of the design is comprises of twoPMOS and one NMOS. The output signal for inputs AB= 01 and 11 will be complete. Both M2 and M3will be on and will pass a poor “HIGH” signal level to the output for AB= 10, the reason is that whenM2 and M3 will be on the resistance of both devices will come in parallel and the total resistance willdecrease which will lead to the degradation in output voltage and as the aspect ratio of M2 is largerthan that of M3, the voltage at OUT terminal will be reflected as per the functioning of transistor M2.However, the threshold drop occurs across M2 for AB=00 and consequently the output Y degrades withrespect to the input. The voltage degradation due to threshold drop can be minimized considerably byincreasing the W of M3. Figure 4: 3T XOR Gate 238
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEMEPower Consumption in Adders Addition is a common operation in circuits designed for portable equipment and is typical of thedigital processing carried out in computer systems. In CMOS circuits most of the energy consumed isdue to switching activity[6], with the number of nodes in the circuit, the stored energy per nodeand the number of switching operations per second all contributing to the total power consumption. Power consumption was paid more and more attention to by IC designers. The motive of lowpower design comes from two reasons: For those chips used in products supplied by battery, such asportable computers and hand-held devices, lower power consumption is one of the key featuressurpassing their competitors [2]With the steadily increasing of chip’s capacity and density, low powerconsumption becomes a vital feature for chip’s functionality and reliability. High power density willmake chip’s temperature increasing, thus cause path delay increasing and problem of metal immigrationBuilding low power VLSI system has emerged as significant performance goal because of the fasttechnology in mobile communication and computation. The advances in battery technology have nottaken place as fast as the advances in electronic devices. So the designers are faced with more constraint;high speed[4], high throughput and at the same time, consuming as minimal power as possible. The goal is to extend battery life span of portable electronics is to reduce the energy expendedper arithmetic operation, but low power consumption does not necessarily result in low energydissipation. To execute an arithmetic operation, a circuit can consume very low power by clocking atextremely low frequency but it may take a very long time to complete the operation. We measure theenergy consumption by the product of average power and worst case delay (power delay-product).ThusETA is found to have less delay and have less power consumption [2].IMPLEMENTATION OF 64-BIT ETA The simulation results of 64-bit ETA are obtained using Tanner EDA tool.Comparative analysis on the error tolerant adders has been done. 239
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME Figure 5: Design of Accurate Part of Existing Method Figure 5 shows the design of accurate part of existing method. The design is created using S- Edit in Tanner. The ripple-carry adder, which is the most power-saving conventional adder, has been chosen for the accurate part of the circuit [5], [7]. Among the 64 bits input the first 24 bits are given to Figure 5 shows the design of accurate part of proposed method. The ripple carry adder is designed using 8 transistor full adder. 240
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME Figure 6: Design of Accurate Part of Proposed method Design of existing modified XOR block using conventional XOR gate is shown in Figure 7. Inthe modified XOR gate, three extra transistors, m1,m2, and m3, are added to a conventional XORgate. CTL is the control signal coming from the control block. 241
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July December (2012), © IAEME July-December Figure 7: Design of Existing Modified XOR Block using Conventional XOR Gate Figure 8 shows the waveform of existing modified XOR block using conventiona XOR gate ntionalthe wave form is viewed using tanner W-Edit. The inputs are A, B and CTL signal [6] andcorresponding SUM output is obtained. btained. 242
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME Figure 8 : Waveform of Existing Modified XOR Blok using Conventional XOR Gate Design of existing modified XOR block using conventional XOR gate is shown in Figure 9. Inthe modified XOR gate, three extra transistors, m1,m2, and m3, are added to a 3 transistor XORgate. Figure 10 shows the wave form of design of proposed modified XOR block using 3T XOR gate.The inputs are A, B and CTL [2] signal and corresponding SUM output is obtained[6]. The wave form isviewed using tanner W-Edit. Figure 9: Design of Proposed Modified XOR Block using 3T XOR Gate 243
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME Figure10: Waveform of Proposed Modified XOR Block using 3T XOR Gate Figure 11 shows the design of inaccurate part of existing method. The inaccurate partconsists of two blocks: the carry free addition block and the control block. The carry-free addition blockis made up of 40 modified XOR gates [8], [7]. Figure 11: Design of Inaccurate Part of Existing Method Waveform of inaccurate part of existing method is shown in figure 12. Among the total 64bits input, the last 40 bits are given as input to the inaccurate part and corresponding sum output isobtained. The wave form is viewed using tanner W- Edit. 244
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME Figure 12: Waveform of Inaccurate Part of existing method Figure 13 shows the design of inaccurate part of proposed method. The design is createdusing S-Edit in Tanner. The carry-free addition block is made up of 40 modified XOR gates. In themodified XOR gate, three extra transistors, M1, M2, and M3, are added to a 3 transistor XOR gate. Figure 13: Design of Inaccurate Part of Proposed method Figure 10 shows the wave form of inaccurate part of proposed method. Among thetotal 64 bits input, the last 40 bits are given as input to the inaccurate part and corresponding sumoutput is obtained. The input bits are A0 to A39, B0 to B39,CTL0 to CTL39[6] and the outputs are S0to S39.The wave form is viewed using tanner W-Edit. 245
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME Figure 14: Waveform of Inaccurate Part of Proposed method Table 1 shows the 64 bit error tolerant adder power comparison. The results of the comparativeanalysis reveal that the performance of the proposed Low Power Error Tolerant Adder consumes leastpower and acquires least area. Table 1: Power Comparison of 64 Bit Error Tolerant Adder Accurate Part Inaccurate Part (Ripplecarry adder) Power Transistor Power Transistor count count Existing 53.46 1454 11.923 672 Method 0mW mW Proposed 13.06 854 25.00 192 Method 8 mW nW 246
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME Chart 1: Power Comparison Chart of 64 bit Error Tolerant Adder Chart 1 shows the power comparison chart using the power results from tanner simulation. It is observedthat power is reduced when using proposed low power error tolerant; adder consumes low power consumptionand high-speed performance is more important than accuracy. Few such applications are in Digital Imageprocessing and DSP architectures for portable devices such as cell phones and laptops.REFERENCES [1] Ning Zhu, Wang Ling Goh, Weija Zhang, Kiat SengYeo, and Zhi Hui Kong,“ Design of low power high-speed truncation- error-tolerant adder and its application in digital signal processing ”.IEEE Trans. Very Large Scale Integrat., 18: 1225-1229. DOI: 10.1109/TVLSI.2009.2020591,August 2010. [2] A. B. Melvin, “Let’s think analog,” in Proc. IEEE Comput. Soc. Annu.Symp , pp. 2–5 ,VLSI, 2005. [3] J. E. Stine, C. R. Babb, and V. B. Dave, “Constant addition utilizing flagged prefix structures,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2005. [4] L.-D. Van and C.-C. Yang, “Generalized low-error area- efficient fixed width multipliers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 25,no. 8, pp. 1608–1619, Aug. 2005. [5] M. A. Breuer, S. K. Gupta, and T. M. Mak, “Design and error- tolerance in the presence of massive numbers of defects,” IEEE Des. Test Comput., vol. 24, no. 3, pp. 216–227, May-Jun. 2004. [6] J.-M. Wang, S.-C. Fang, and W.-S. Feng, “New efficient designs for XOR and XNOR functions on the transistor level,” IEEE J. Solid-State Circuits,vol. 29, no. 7, pp. 780– 786, Jul. 1994. [7] N. H. E. Weste, and K.Eshraghain, “PRINCIPLES OF CMOS VLSI Design,A Systems Perspective,” Pearson Education, 2010. [8] M. Morris Mano, “Digital Design” – Third Edition, Prentice Hall of India private limited, 2006. 247