Design & implementation of 3 bit flash adc in 0.18µm cmos
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Design & implementation of 3 bit flash adc in 0.18µm cmos

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    Design & implementation of 3 bit flash adc in 0.18µm cmos Design & implementation of 3 bit flash adc in 0.18µm cmos Document Transcript

    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME308DESIGN & IMPLEMENTATION OF 3-BIT FLASH ADC IN 0.18µMCMOSMd Noorullah KhanAssistant professor, ECEDMuffakham Jah college of engineering and technologyHyderabad, A.P.Dr Kaleem FatimaProfessor and Head ECEDMuffakham Jah College of engineering and technologyHyderabad, A.P.Khaja Mujeebuddin QuadryProfessor & Head Dept. of ECERoyal Institute of Technology and ScienceChevella, R.R.Dist, A.P.ABSTRACTThis paper describes the design and implementation of a 3-bit flash Analog to Digitalconverter (ADC). It includes 7 comparators and one thermometer to binary encoder. It is implementedin 0.18um CMOS Technology. The simulation result of ADC is done in Cadence environment.Index Terms: CMOS, Comparator, Thermometer code, Flash ADC, cadenceI. INTRODUCTIONApplications such as wireless communications and digital audio and video have created needfor cost-effective data converters that will achieve higher speed and resolution. The needs required bydigital signal processors continually challenge analog designers to improve and develop new ADCand DAC architectures. There are many different types of arc-hitectures, each with uniquecharacteristics and different limitations. Figure.1 shows the general block diagram of ADC.INTERNATIONAL JOURNAL OF ADVANCED RESEARCH INENGINEERING AND TECHNOLOGY (IJARET)ISSN 0976 - 6480 (Print)ISSN 0976 - 6499 (Online)Volume 4, Issue 3, April 2013, pp. 308-315© IAEME: www.iaeme.com/ijaret.aspJournal Impact Factor (2013): 5.8376 (Calculated by GISI)www.jifactor.comIJARET© I A E M E
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME309Fig. 1.Block diagram for 3-bit Flash ADCFlash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert ananalog signal to a digital signal. Flash ADCs are ideal for applications requiring very large bandwidth;however, they typically consume more power than other ADC architectures and are generally limitedto 8-bits resolution.II ADC ARCHITECTUREIII The 3-bit Flash ADC architecture is shown in Fig. 2. The entire ADC consists of threecomponents: the resistive ladder, the comparators, and the binary encoder.Each comparator compares the voltage difference between its positive input from VIN and its negativeinput from the Resistive ladder and then generates a digital output. The binary encoder generatescorresponding 3-bit binary codes based on the comparator outputs. As shown in figure 2.Fig. 2.Simple 3-bit Flash ADCThe encoder converts the thermometer code produced by the comparators to a binary code as shown inthe truth table in table II. As seen from the figure, the comparators all operate in parallel. Thus, theconversion speed is limited only by the speed of the comparator or the sampler. For this reason, theflash ADC is capable of high speed.
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEMEA) COMPARATOR CIRCUIT &ComparatorA comparator is used to detect whetherof one signal to another. It is in fact the second most widely used electronic components after amplifiers.A simple op-amp can be used as a comparator but this approach is too slow for practicalThe circuit that has been used as a comparator is a CMOS circuit, which consists of two stages. The firststage is a differential amplifier circuit and the second stage consists of a buffer formed by using twoinverter circuits. The output of the differential stage will neither rise exactly to vdd nor fall exactly tozero, hence this output is given to second stage consisting of two inverters which gives final outputwhich will be either vdd or zero depending on whether the input voltage is greference voltage respectively.Fig.3.Fig 3 shows the comparator circuit where two matched input transistors whose sources are joinedtogether and biased by a transistor which should always be maintained in saturation region. The MOSdifferential pair formed by the input transistors is loadedtransistors at the top. The input voltage is applied to the gate of the input transistor in the left leg ofthe circuit and reference voltage is applied at the gate of the input transistor in the right leg. If theinput voltage exceeds the reference voltage then the input transistor in the right leg goes into cutoffand the entire current from the source flows only into the left leg and thus the voltage at the outputnode will be nearly equal to vdd, which is then givenfinally makes output equal to vdd.Table 1: transistor sizes ofTransistorPM0PM1PM2PM3NM0NM1NM2NM3NM4International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN6499(Online) Volume 4, Issue 3, April (2013), © IAEME310& DESIGN SPECIFICATIONSA comparator is used to detect whether a signal is greater or smaller than zero, or to compare sizeof one signal to another. It is in fact the second most widely used electronic components after amplifiers.amp can be used as a comparator but this approach is too slow for practicalThe circuit that has been used as a comparator is a CMOS circuit, which consists of two stages. The firststage is a differential amplifier circuit and the second stage consists of a buffer formed by using twof the differential stage will neither rise exactly to vdd nor fall exactly tozero, hence this output is given to second stage consisting of two inverters which gives final outputwhich will be either vdd or zero depending on whether the input voltage is greater or less than theFig.3. Circuit Diagram of the ComparatorFig 3 shows the comparator circuit where two matched input transistors whose sources are joinedtogether and biased by a transistor which should always be maintained in saturation region. The MOSdifferential pair formed by the input transistors is loaded by a current mirror formed by two MOStransistors at the top. The input voltage is applied to the gate of the input transistor in the left leg ofthe circuit and reference voltage is applied at the gate of the input transistor in the right leg. If thet voltage exceeds the reference voltage then the input transistor in the right leg goes into cutoffand the entire current from the source flows only into the left leg and thus the voltage at the outputnode will be nearly equal to vdd, which is then given to the stage consisting of two inverters whichtransistor sizes of the proposed comparatorTransistor W (um) L (nm)PM0 10 180PM1 10 180PM2 2 180PM3 2 180NM0 6 180NM1 6 180NM2 1 180NM3 1 180NM4 10 180International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN6499(Online) Volume 4, Issue 3, April (2013), © IAEMEa signal is greater or smaller than zero, or to compare sizeof one signal to another. It is in fact the second most widely used electronic components after amplifiers.amp can be used as a comparator but this approach is too slow for practical applications.The circuit that has been used as a comparator is a CMOS circuit, which consists of two stages. The firststage is a differential amplifier circuit and the second stage consists of a buffer formed by using twof the differential stage will neither rise exactly to vdd nor fall exactly tozero, hence this output is given to second stage consisting of two inverters which gives final outputreater or less than theFig 3 shows the comparator circuit where two matched input transistors whose sources are joinedtogether and biased by a transistor which should always be maintained in saturation region. The MOSby a current mirror formed by two MOStransistors at the top. The input voltage is applied to the gate of the input transistor in the left leg ofthe circuit and reference voltage is applied at the gate of the input transistor in the right leg. If thet voltage exceeds the reference voltage then the input transistor in the right leg goes into cutoffand the entire current from the source flows only into the left leg and thus the voltage at the outputto the stage consisting of two inverters which
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME311On the other hand when the input voltage is less than the reference voltage the input transistor in theleft leg of the circuit goes into cutoff and the entire current from the source flows only into the rightleg and thus the voltage at the output node will be nearly equal to zero and the next stage will make itexactly zero. W/Ls of the transistors used in the comparator are shown in Table 1, The aboveproposed comparator circuit consists of total 9 (4 pmos and 5 nmos) transistors. The widths andlengths of each of these transistors are shown in table I.Fig 4 shows the transient responses of the comparator. In the transient response it can be seenthat whenever the input sinusoidal signal voltage is above the reference voltage (which is 1volt in thiscase) the comparator output is logic-1 and whenever it is below the reference voltage the comparatoroutput is logic-0.Fig.4. Comparator OutputThe ac response in fig 5 shows that the comparator can work efficiently up to 4G-HZ sincethis comparator circuit can provide sufficient gain up to this frequency after which the responsedegrades and circuit cannot be used as a comparator beyond this frequency.Fig.5. AC response of the comparatorB) THERMOMETER TO BINARY ENCODER DESIGNThe outputs of comparators form a thermometer code (TC) which is a combination of a seriesof zeros and a series of ones, e.g., 000…011…111 and are given to Thermometer to binary encodercircuit.
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEMEFig .6Because binary code is usually needed for digital signal processing, a thermometer code is thentransformed to a binary code through a (2kof ADCs. Truth table for thermometer to binary encoder is as shown in tabTable.2The logic that has been used in implementing the thermometer to binary encoder is that the outputbinary code is numerically equal to the number of 1s present in the input thermometer code.Fig.7.International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN6499(Online) Volume 4, Issue 3, April (2013), © IAEME312Fig .6. Block Diagram of Sub-ADCcode is usually needed for digital signal processing, a thermometer code is thentransformed to a binary code through a (2k-1)-to-k TC-to-BC encoder, where k is the resolution (bits)of ADCs. Truth table for thermometer to binary encoder is as shown in table2Table.2. Thermometer to binary codeThe logic that has been used in implementing the thermometer to binary encoder is that the outputbinary code is numerically equal to the number of 1s present in the input thermometer code.Fig.7. Thermometer to Binary EncoderInternational Journal of Advanced Research in Engineering and Technology (IJARET), ISSN6499(Online) Volume 4, Issue 3, April (2013), © IAEMEcode is usually needed for digital signal processing, a thermometer code is thenBC encoder, where k is the resolution (bits)The logic that has been used in implementing the thermometer to binary encoder is that the outputbinary code is numerically equal to the number of 1s present in the input thermometer code.
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEMEHence the output binary code can be obtained by simply adding all the bits of the inputthermometer code. This has been implemented by using the full adder circuits as shown in the fig 7FIG.8. OUTPUT OFFigure 8 shows the output of the comparators which are called as thermometer code, thebottom 3 wave forms are the converted 3 bit binary code. It can be seen from this result that as thenumber of input signals having thecircuit also increases by one in value.C) FINAL 3BIT FLASH ADCAfter having designed the comparator and the thermometer to binary converter circuits, thenext step is to arrange the seven comparators in parallel, where the one input to each of thecomparator is the input signal and the other input is the reference volfigure 9.Here the comparator used is that of the figure 3 and the reference voltages required arederived from a series of voltage sources each having a voltage of 250mV. Hence the voltage obtainedas reference for the bottom most comparator is 250mV and that of the top most seventh comparator is1.75V. Hence the reference voltages for the 3International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN6499(Online) Volume 4, Issue 3, April (2013), © IAEME313Hence the output binary code can be obtained by simply adding all the bits of the inputthermometer code. This has been implemented by using the full adder circuits as shown in the fig 7OF THERMOMETER TO BINARY CODE CONVERTERFigure 8 shows the output of the comparators which are called as thermometer code, thebottom 3 wave forms are the converted 3 bit binary code. It can be seen from this result that as thenumber of input signals having the value equal to logic-1 increases by one the binary output of thecircuit also increases by one in value.BLOCKAfter having designed the comparator and the thermometer to binary converter circuits, thenext step is to arrange the seven comparators in parallel, where the one input to each of thecomparator is the input signal and the other input is the reference voltages, which is shown in theFig.9. Final Flash ADCHere the comparator used is that of the figure 3 and the reference voltages required arederived from a series of voltage sources each having a voltage of 250mV. Hence the voltage obtainedas reference for the bottom most comparator is 250mV and that of the top most seventh comparator is1.75V. Hence the reference voltages for the 3-bit flash ADC is according to the table 2.International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN6499(Online) Volume 4, Issue 3, April (2013), © IAEMEHence the output binary code can be obtained by simply adding all the bits of the inputthermometer code. This has been implemented by using the full adder circuits as shown in the fig 7ONVERTERFigure 8 shows the output of the comparators which are called as thermometer code, thebottom 3 wave forms are the converted 3 bit binary code. It can be seen from this result that as the1 increases by one the binary output of theAfter having designed the comparator and the thermometer to binary converter circuits, thenext step is to arrange the seven comparators in parallel, where the one input to each of thetages, which is shown in theHere the comparator used is that of the figure 3 and the reference voltages required arederived from a series of voltage sources each having a voltage of 250mV. Hence the voltage obtainedas reference for the bottom most comparator is 250mV and that of the top most seventh comparator is
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME314Fig.10. Layout of Flash ADCIII.ADC OUTPUT WAVEFORMSFor the Flash ADC complete layout is prepared as shown in figure 10 where the most sensitiveparts are the comparators for which common centroid layout is carried out in order to overcome theerrors in the fabrication process.Fig.11. Final output of 3bit Flash ADCFigure 11 shows the output of final 3-bit flash ADC designed. It can be observed from thisfigure that the input signal applied to the flash ADC is a sinusoidal signal whose input voltage variesfrom 0V to 2V which generates a 3-bit binary output which varies from 000 to 111 as the inputsinusoidal voltage increases from 0V to 2V.
    • International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME315III. CONCLUSIONA 3-bit Flash ADC has been designed using the proposed comparator circuit. The implementationof this circuit hasBeen done in cadence environment and output waveforms have been obtained.IV. REFERENCES[1] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, Tata McGraw-Hill Edition,2002.[2] R.Jacob Baker, Harry W. Li & David E. Boyce, “CMOS circuit design, layout and simulation”,IEEE Press Series on Microelectronic Systems, Prentice-Hall of India Private Limited, 2004.[3] Klass Bult and Govert J. G. M. Geelen, “A Fast Settling CMOS OpAmp for SC Circuits with 90-dB DC Gain” , IEEE J. Solid-State Circuits, Vol.25, No.6, December 1990.[4] Thomas Byunghak Cho, Student Member, IEEE, and Paul R. Gray, Fellow, IEEE, “A 10 b, 20Msample/s, 35 mW Pipeline A/D Converter”, IEEE J. Solid-State Circuits, Vol.30, No.3, March1995.[5]. Mark Ferriss, Joshua Kang, “A 10-Bit 100-MHz Pipeline ADC”, University of Michigan, 598design project, 2004.[6]. Andrew M. Abo and Paul R. Gray, Fellow, IEEE, “A 1.5-V, 10-bit, 14.3-MS/s CMOS PipelineAnalog-to-Digital Converter”,IEEE J. Solid-State Circuits, Vol.34, No.5, March 1999.[7].Stephen H. Lewis, H.Scott Fetterman, George F. Gross, R. Ramachandran and T. R. Viswanathan,“A 10-b 20-Msample/s Analog-to-Digital Converter”, IEEE J. Solid-State Circuits, Vol.27, No.3,March 1992.[8]. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits: A DesignPerspective”, Prentice Hall, 2nd edition[9] Suhas. S. Khot, Prakash. W. Wani , Mukul. S. Sutaone and Saurabh.K.Bhise, “A 581/781 Msps 3-Bit Cmos Flash Adc Using Tiq Comparator” International Journal Of Electronics AndCommunication Engineering &Technology (IJECET) Volume 3, Issue 2, 2012, PP: 352 – 359ISSN PRINT: 0976- 6464, ISSN ONLINE: 0976 –6472[10]Rajinder Tiwari, R K Singh, “An Optimized High Speed Dual Mode Cmos Differential Amplifierfor Analog Vlsiapplications” International Journal of Electrical Engineering & Technology(IJEET) Volume 3, Issue 1, 2012, PP: 180 – 187, ISSN PRINT: 0976-6545, ISSN ONLINE:0976-6553[11] S. S. Khot, P. W. Wani,M. S. Sutaone and S.K.Bhise, “A 555/690 Msps 4-Bit Cmos Flash AdcUsing Tiq Comparator” International Journal of Electrical Engineering & Technology (IJEET)Volume 3, Issue 2, 2012, PP: 373 – 382, ISSN PRINT: 0976-6545, ISSN ONLINE: 0976-6553