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Design & characterization of high speed power efficient cmos comparator
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Design & characterization of high speed power efficient cmos comparator

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In this paper authors have design the High Speed Power Efficient CMOS Voltage …

In this paper authors have design the High Speed Power Efficient CMOS Voltage
Comparator which can be realized in A/D Converters. The simulation is carried out in 130nm
and 90nm technologies. The supply voltage for this comparator is 1v and 0.9v for 130nm and
90nm respectively. The Characterization of comparator is done in terms of offset, ICMR,
propagation delay, power dissipation in both the technologies and the result has been
compared for both the technologies. The simulation results shows that the speed of 1.92GHz
and 2.44GHz with the power dissipation of 9.19µW and 7.45µW was achieved in 130nm and
90nm technologies respectively.

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  • 1. International Journal of Electronics and Communication Engineering & Technology (IJECET),ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 3, May – June (2013), © IAEME24DESIGN & CHARACTERIZATION OF HIGH SPEED POWEREFFICIENT CMOS COMPARATORPriyesh P. Gandhi1, Dhanisha N. Kapadia2, N. M. Devashrayee31(EC Dept., Institute of Technology, Nirma University, Ahmedabad, India)2(EC Dept., L. C. Institute of Technology, Bhandu, Gujarat Technological UniversityAhmedabad, India)3(EC Dept., Institute of Technology, Nirma University, Ahmedabad, India)ABSTRACTIn this paper authors have design the High Speed Power Efficient CMOS VoltageComparator which can be realized in A/D Converters. The simulation is carried out in 130nmand 90nm technologies. The supply voltage for this comparator is 1v and 0.9v for 130nm and90nm respectively. The Characterization of comparator is done in terms of offset, ICMR,propagation delay, power dissipation in both the technologies and the result has beencompared for both the technologies. The simulation results shows that the speed of 1.92GHzand 2.44GHz with the power dissipation of 9.19µW and 7.45µW was achieved in 130nm and90nm technologies respectively.Index Terms: Buffer stage, Current Sensing Comparator, Latch Comparator.I. INTRODUCTIONA Comparator is a circuit which compares the two analog signal and depending on thecomparison gives the output either logic ‘1’ or logic ‘0’. The comparators are widely used inADC. In fact, comparator is also called as 1 bit ADC. In conventional design, in order toreduce the input offset voltage preamplifiers were added before the comparator, butultimately this increases the power consumption. Therefore, a latched comparator is a goodalternative for low power consumption and high-speed operation. There are three types ofcomparator which can provide high speed, such as multistage open loop comparator, thedynamic latch comparator, and the preamplifier-latch comparator. The multistage open loopINTERNATIONAL JOURNAL OF ELECTRONICS ANDCOMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)ISSN 0976 – 6464(Print)ISSN 0976 – 6472(Online)Volume 4, Issue 3, May – June, 2013, pp. 24-32© IAEME: www.iaeme.com/ijecet.aspJournal Impact Factor (2013): 5.8896 (Calculated by GISI)www.jifactor.comIJECET© I A E M E
  • 2. International Journal of Electronics and Communication Engineering & Technology (IJECET),ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 3, May – June (2013), © IAEME25comparator can meet high-speed and high-precision, but cannot provide the speed more than1Gbps, so the dynamic latch comparator is widely utilized to satisfy the need for high-speed.The paper is being divided into six sections. In section 2, current sensing comparatortopology and the buffer stage have been discussed. In section 3, authors have discussed aboutproposed architecture of comparator. In section 4, simulation results are presented. Section 5includes the comparison of the simulation results in both the technologies. Finally in section6, conclusion has been discussed.II. DIFFERENTIAL CURRENT SENSING COMPARATOR AND BUFFER STAGEA. Differential Current Sensing ComparatorFig. 1. Differential current sensing comparator[3]Figure-1 shows the schematic of the differential current sensing comparator.Whenever the Clk signal goes low, circuit enters in regenerative mode. Transistor M12 is onand M7 is off. Both nMOS M5 and M6 will start conducting when values of both the outputsOut+ and Out- increases above threshold voltage of both transistors, which will connect theoutputs with comparing circuit at the input side. Unless and until final state is reached boththe outputs have to drive common mode currents, hence it consumes more power.When the CLK signal goes high, the circuit enters in reset mode. The comparingcircuit used at the input side consisting of transistors M1, M2, M3 and M4 are used totransfer the difference of the input voltage into differential currents. A pass transistor M7 isused to connect both the outputs together.B. Buffer StageThe circuit diagram of output buffer circuit used in the comparator is shown inFigure-2[4]. The output buffer stage is also called post amplifier. This circuit is selfbiasing differential amplifier which has differential inputs as Vout+ & Vout- and does nothave any slew rate limitations. It is also useful in giving the output in proper shape.
  • 3. International Journal of Electronics and Communication Engineering & Technology (IJECET),ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 3, May – June (2013), © IAEME26Fig.2 The Output Buffer Circuit[4]III. PROPOSED CMOS VOLTAGE COMPARATORThe circuit diagram of the proposed high speed CMOS voltage comparator is asshown in Figure-3. Whenever the Clk signal goes high, the circuit enters in regenerativemode. Transistor M11 and M7 are off and M14 is on. When values of both the outputs Out+and Out- increases above threshold voltage of nMOS M5 and M6, both will start conductingwhich will connect the outputs with comparing circuit at the input side.The comparing circuit used at the input side consisting of transistors M1, M2, M3 andM4 are used to transfer the difference of the input voltage into differential currents. Duringreset interval, a pass transistor M11 is used to connect both the outputs together. Wheneverthe Clk signal goes low, transistor M7 and M8 are on. The two nodes which are connectedwith the drains of M7 and M8 will get reset to Vdd. These internal nodes are reset to Vddduring the phase when the comparator is not making a decision. This will ensure that all theinternal nodes are reset before the comparator goes into decision mode. So the problemassociated with previous code dependent biased decision which occurs due to the chargeimbalance left from previous decision at one of the nodes of the comparator which affectsnext decision is thus removed.The two outputs Out+ and Out- of the comparator are being converted into singleoutput with the output buffer circuit so that various analysis can be carried out. Table-I givenbelow shows different widths of the transistor to be used according to the chosen technology.The length for the transistor is 0.13um and 0.1um respectively for 130nm and 90nmtechnology.TABLE-1.CMOS TRANSISTOR WIDTHS FOR DIFFERENT TECHNOLOGIESTechnology Wp(um) Wn(um)130nm 0.15 0.1590nm 0.12 0.12
  • 4. International Journal of Electronics and Communication Engineering & Technology (IJECET),ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 3, May – June (2013), © IAEME27Fig.3 Proposed Design of ComparatorIV. SIMULATION RESULTS OF PROPOSED COMPARATORThe simulated results are obtained for two different technologies 130nm and 90nm. InTable-II, different voltage values are given for supply voltage VDD and VSS, referencevoltage Vref+ and Vref-, input voltage Vin+ and Vin- and ClkbTABLE-IIDIFFERENT VOLTAGE VALUES FOR DIFFERENT TECHNOLOGIESVoltageTerminalsTechnology130nm 90nmVDD 1v 0.9vVSS -1v -0.9vClkb -1v -0.9vVin+ 1v 0.9vVin- -1v -0.9vVref+ 0.43v 0.34vVref- -0.43v -0.34vWhen sine wave is applied to the comparator as an input, the output will be the squarewave as shown in Figure-5 and Figure-9.
  • 5. International Journal of Electronics and Communication Engineering & Technology (IJECET),ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 3, May – June (2013), © IAEME28A. Simulated waveforms in 130nm technologyFig. 5 Sine Wave as an InputFig. 6 Transient Response
  • 6. International Journal of Electronics and Communication Engineering & Technology (IJECET),ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 3, May – June (2013), © IAEME29Fig. 7 Input Common Mode RangeFig 8 Output Offset voltage
  • 7. International Journal of Electronics and Communication Engineering & Technology (IJECET),ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 3, May – June (2013), © IAEME30B. Simulated waveforms in 90nm technologyFig. 9 Sine Wave as an InputFig. 10 Transient Response
  • 8. International Journal of Electronics and Communication Engineering & Technology (IJECET),ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 3, May – June (2013), © IAEME31Fig. 11 Input Common Mode RangeFig.12 Output Offset VoltageV. COMPARISON OF DIFFERENT CHARACTERISTICS IN 130NM AND 90NMTECHNOLOGIESIn this paper, simulated results are presented for the comparator for two differenttechnologies, 130nm and 90nm. The summary of the comparison for the comparator in boththe technologies is given in the Table III.
  • 9. International Journal of Electronics and Communication Engineering & Technology (IJECET),ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 3, May – June (2013), © IAEME32TABLE IIISIMULATED RESULTS OF CURRENT SENSING COMPARATOR WITH BUFFER CIRCUIT FORDIFFERENT TECHNOLOGIESParameters Technology130nm 90nmPropagation Delay(ns) 0.46 0.34Speed(GHz) 2.17 2.94ICMR(V) -0.2 to 0.61 -0.2 to 0.5Offset 69mV 0.16Power Dissipation(uW) 21 10.22VI. CONCLUSIONSpeed of the comparator which is implemented in 90nm is more than speed ofcomparator in 130nm. The input common mode range is almost remaining same for both thetechnologies. With the reduction in technology, the offset voltage is getting increased due toincrease in the non-idealities of the transistors and the power dissipation is also reduced withthe reduction in the technology. Proposed Comparator has high speed which can be realizedin A/D Converters.REFERENCES[1] P. Uthaichana and E. Leelarasmee, "Low Power CMOS Dynamic Latch Comparators," IEEE,pp. 605-608, 2003.[2] Z. Huang and P. Zhong, "An Adaptive Analog-to-Digital Converter Based on Low-PowerDynamic Latch Comparator," IEEE conference, p. 6pp, 2005.[3] Christopher J. Lindsley “A Nano-Power Wake-Up Circuit for RF Energy HarvestingWireless Sensor Networks” , M.S. thesis, Dept. Electrical & computer. Eng., Oregon StateUniversity 2008.[4] Priyesh P. Gandhi “Design & Simulation of Low Power High Speed CMOS Comparator inDeep Sub-micron Technology”, M.Tech thesis, Dept. of electronics & communication Eng.Nirma University, 2010.[5] Philip E. Allen and Douglas R. Hallberg. CMOS Analog Circuit Design. Oxford UniversityPress, Inc USA-2002,pp.259-397, 2002[6] R. Jacob Baker Harry W. Li David E. Boyce. CMOS Circuit Design, Layout and Simulation.IEEE Press Series on Microelectronics Systems, 2005.[7] Dhanisha N. Kapadia and Priyesh P. Gandhi, “Design and Simulation of High Speed CMOSDifferential Current Sensing Comparator in 0.35 µm and 0.25µm 1 Technologies”,International journal of Electronics and Communication Engineering &Technology(IJECET), Volume 3, Issue 3, 2012, pp. 147 - 152, ISSN Print: 0976- 6464, ISSN Online:0976 –6472.[8] Rajinder Tiwari and R K Singh, “An Optimized High Speed Dual Mode CMOS DifferentialAmplifier for Analog VLSI applications”, International Journal of Electrical Engineering &Technology (IJEET), Volume 3, Issue 1, 2012, pp. 180 - 187, ISSN Print : 0976-6545, ISSNOnline: 0976-6553.