Design and implementation of reduced die area uwb 10 ghz_ current re-used casc

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Design and implementation of reduced die area uwb 10 ghz_ current re-used casc

  1. 1. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 140 DESIGN AND IMPLEMENTATION OF REDUCED DIE AREA UWB (10GHZ) CURRENT RE-USED CASCADED DEGENERATED LNA (0.18UM CMOS) 1 Miriyala venkata Pavan kumar, 2 Manoj nune, 3 Sadananda rao chowdary.Y 4 M.V.Maheshwara Reddy .M.tech Electronics and communication engineering ABSTRACT In this paper we introduced a new technique for effective wide band input impedance match- ing and small area for current reused cascaded LNA in band of (8-18GHz) X/KU band contrast to traditional LNA . The proposed circuit is designed in TSMC 0.18um technology. This is achieved by taking the advantage of shunt-shunt feedback and source degeneration topology. This is com- pletely contrasted to traditional LNA. By introducing the centre tapped inductor CTI at the inter stage of LNA. Appreciably high gain is obtained over entire the band width with small area. The in- put output return losses are less than -10db for entire band. Key words: cascade, centre tapped inductor, low noise amplifier (LNA), resistive feedback, X/Ku band. I. INTRODUCTION The demand for higher data rates has increased the desired operation frequency of RFICs. Among these applications X-Band (8 to 12 GHz) and Ku-Band (12 to 18 GHz) are of great interest to high data rate wireless communications and radars [1]. LNAs are an important building block in RF transceivers. To arrive at the acceptable receiver sensitivity the LNAs must have sufficient gain, ap- propriate input matching and low noise figure (NF), and at the same time has low power consump- tion and occupies small chip area. Satisfying all of the design goals for the wideband LNA over X/Ku-band is challenging, because of the high operating frequency and the broad bandwidth (BW). Different approaches have been offered for the design of wideband LNAs. A distributed amplifier (DA) is a typical choice to achieve high gain and good matching over such a broad bandwidth [2]. However, DAs typically take up substantial die area and also suffer from high noise figure (NF). Using Transformer at the input matching network of the common source (CS) LNA provides broadband input matching, while introducing less noise than resistive feedback. However, three stage cascade amplifiers are needed to provide high power gain which increase power consumption [3]. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) ISSN 0976 – 6464(Print) ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August, 2013, pp. 140-147 © IAEME: www.iaeme.com/ijecet.asp Journal Impact Factor (2013): 5.8896 (Calculated by GISI) www.jifactor.com IJECET © I A E M E
  2. 2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 141 A common-gate (CG) configuration was used which resulted in a Wide band input matching and good reverse isolation, and therefore good stability. However, the NF of the CG-LNA is consid- erably larger than that of the CS or cascade LNAs [4]. This paper demonstrates the design of an LNA which covers the entire X/Ku-band. Current-reused cascade configuration with CTI is used at the inter stage network to achieve high gain and small die area. The proposed LNA is described in section II. Simulation results are presented and dis- cussed in section III. A summary of the important results are Presented in section IV. II. CIRCUIT TOPOLOGY AND ANALYSIS Fig. 1 shows the schematic of the proposed LNA. The inter-stage network composed of the inductor Ls2 and capacitors Cs and C2 perform a current-reused function to save power consumption and also achieve high power gain. Inductors L2 and L1 are used for bandwidth enhancement. A source follower buffer composed of M3 and M4 is used to provide wideband output matching. Resis- tive feedback is employed at the input matching network but a different feedback path is used in this design to achieve wideband input matching and flat frequency response. Peaking inductors Lg2 and Lg1 are added to the gate terminal of M1 and M3 to increase the bandwidth of the circuit. The ca- pacitor C3 represents the equivalent load of the mixer or the buffer stage. A. Wideband Input Impedance Matching Design Fig. 2. Small signal equivalent circuit of the proposed LNA
  3. 3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 142 As is seen in Fig. 1 resistive feedback is employed at the input matching network. The feed- back signal is taken from the gate of M3, in contrast to some reported cascade LNAs in which the feedback signal is taken from left side node of Lg2 [5].The cascade combination of M1-M2 isolates the output from input alleviating the undesired feedback from output to input, and also eliminates the Miller effect of the gate- drain capacitance of M1. The isolation of drain and source of M2, however is not done completely due to its finite output resistance. Therefore, as will be explained later in this section, by connecting the feedback path Rf-Cf from gate of M3 to the LNA's input, a better match- ing is achieved. In order to prove the effectiveness of the proposed approach the parameters of the circuit for wideband input matching are derived first. Fig. 2 shows the small signal equivalent of the circuit. In this design Cs is a large capacitor (about 15pF) and is neglected in the small signal model. At first the coupling factor (k) of inductors is assumed to be zero and the effect of k on the circuit will be analyzed later. The input impedance of the circuit can be express as [5]. If the effect of the resistive feedback (RF) is negligible Zin1 represents the input impedance of the LNA. ZF is the impedance looking into the shunt–shunt RF feedback. A simplified expression of the Zin1 and ZF are given by In (3), ZL is the load impedance at node in which resistive feedback signal is taken. When the impact of ZF and Miller capacitance of transistors on the upper edge of the frequency band are ne- glected, from (2) the high frequency valley (ωH) and the quality factor of the input reflection coeffi- cient are derived as [5] Where Rs represents the source impedance. From (4) it is expected to achieve input imped- ance matching around H by adjusting Lg1, Ls1 and Cgs1. For this design goal of an LNA circuit ap- plicable to the frequency range from 8-18GHz, the upper edge and lower edge of frequency band are chosen as 8GHz and 18GHz, respectively. Assuming Cgs1 = 110fF, gives Lg1+Ls1=.6nH. Consider- ing Ls1=.15nH gives Ls1=.45nH. Unfortunately Ls2, Lg2, LL, L2 and L1 degrade the quality factor and thus input impedance matching throughCgd1 coupling but the impact of inductors (Ls2, Lg2, LL, L2, L1) on the quality factor of the input impedance matching can be decreased by properly choosing ZF. Bellow the upper edge of frequency band ZF in (3) can be simplified as [5]
  4. 4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 143 In the above equation CL and LL are the total equivalent drain capacitance and inductance seen at node in which resistive feedback signal is taken like A, B and C. CL and LL are derived as follow At node A, CL and LL are derived as: (6) At node B, CL and LL are derived as: (7) In which Assuming Cgs3=110fF and C2=1pF gives Lg2+ Ls2=1.5nH. Lg2 improves the bandwidth but also peaks the response. Thus Lg2 has small value. Considering Lg2=.55nH gives Ls2=.9nH. From (6),(7),(8),(9) it is clear that L for node A and B is approximately the same but QL for node A is lower than node B (LL at node A is larger than LL at node B). Therefore a wider input matching can be achieved (for node A) [5]. In order to show the difference of the resistive feedback path between node A and node B at the high frequency of the input matching, we should calculate ZL and ZF for node A and B. If feed- back signal is taken from node A, ZL is obtained as If feedback signal is taken from node B, ZL is obtained as [5]. Where C'gs3 is defined in (8). Using the above values for Ls2, Cgs3, C2 and Lg2, ZLA and ZLB around the upper edge of the frequency band are simplified as By substituting (12) in (3), ZF for node B is given by Z FB ≈ RF (13)
  5. 5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 144 Deriving ZFA is a little complicated. Using small signal model and (12), ZFA is given by: Around ωH, ZFA can be simplified as (because s2 Cgs1(Lg1 + Ls1) +1 approximately equals to zero) As mentioned earlier at high frequencies (near H) Ls2, Lg2, LL, L2 affect the Zin1 and Zin1 becomes inductive. We must choose ZF such that compensates this inductive term and therefore good input matching is achieved. We compare phase of ZFA and ZFB. From (15), it is clear that the numerator of ZFA is ca- pacitive and for frequency above the denominator of ZFA is less than zero. Therefore in comparison to ZFB, ZFA has lower phase. ZFA can compensate the inductive feature of Zin1. If resistive feed- back signal is taken from node A, better matching is achieved. The analysis of input impedance matching at node C is very similar to node B. The mentioned technique has the additional advantages that it simultaneously improves the gain flatness and stability of the design (according to the simula- tions). B. Center-tapped inductor at the Inter Stage Network Center-tapped inductor (CTI) is used to save die area and reduce the loss associated with the inductors. The inter stage network of the proposed circuit incorporating the CTI with coupling coefficient (k) between L1 and Ls2 is shown in Fig.3(a). The equivalent small-signal model of the inter stage network is shown in Fig. 3(b) [6]. Note that, under similar bias conditions, the amplifier gain can be further enhanced by increasing the L1, Ls2 and Lg2. From the small signal model it is obvious that if positive sign for k and thus M is chosen, larger Lg2 (L’g2=Lg2-M) and smaller L1 (L’1=L1+M) and L’s2(L’s2=Ls2+M) can be used. Using CTI (with positive k) leads to low inductors value and low area. M is the mutual inductance and equals . The CTI was implemented and simulated using TSMC 0.18µm CMOS technology with 6 metal layers. Fig. 4 shows the schematic of CTI. S-parameters of CTI were extracted using An soft HFSS simulation tools. III. RESULTS AND DISCUSSIONS In order to arrive at the best performance of the circuit, values of all elements were optimized using the genetic algorithms (GA). An automated technique was used to optimize circuit perform- ance. The proposed CAD was based on the multi objective GAs. In this work 16 of the circuit parameters shown in Table I were chosen as the optimization variables, to optimize the bandwidth, average power gain, NF, power consumption, stability and the S11. The finally optimized component values are derived and listed in Table I. Fig.3(a) Inter stage network of the proposed LNA. (b) Simplified small-signal equivalent circuit of the inter stage network.
  6. 6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 145 TABLE.1 VALUES OF PARAMETERS The LNA with the bandwidth of 8–18GHz has been simulated with Advanced Design System (ADS) simulation software using 0.18µm CMOS RF model. With 1.8V power supply the amplifier core consumes about 7.6mW and the dissipated power in the buffer stage is about 2.73mW. The out- put buffer is a source follower and cascaded with the second stage for simulation purpose. The simu- lated power gain and NF versus frequency are plotted in Fig. 5. The power gain varies from 17.5- 18.5dB across the entire band. NF of 3.4}0.6dB is achieved over the X/Ku-band. The S11 and re- verse isolation are presented in Fig. 6. S11 and S22 are less than -10dB and S12 is less than -34dB. The third order input intercept point (IIP3) is simulated. Two-tone test is used to simulate the IIP3 with 1MHz frequency pace between the tones. Simulation shows an IIP3 of -13dBm at 13GHzfrequency. Based on the simulation result, group delay variation is 25ps across the whole band. Fig.7 shows the simulated S21 with k=0 and k=0.8. It can be seen that, the power gain increases 3dB with k=.8 which shows the effect of proposed approach. S11 is also simulated for different resistive feed- back path (node A and node B). As seen in Fig. 8. wider bandwidth for S11 is achieved when the resistive feedback signal is taken from node A. To examine the stability the stability factor (µ) [9] of the circuit is calculated. µ is above 2.5 over the 8-18GHz, which shows good stability. In order to compare the proposed LNA with other works, a figure of merit is defined as: Based on the FOM calculated in Table I, the. Proposed LNA shows a performance better Fig. 4. Representation of CTI using HFSS (W/L)1 94/.18 (W/L)2 135/.18 (W/L)3 88.5/.18 C2 7p LL .75n L2 .45n Ls1 .13n L1 .15n RL 62ohms Cs 16p Rf 360 ohms k .8 Cf 3p Lg2 .4n Ls2 .8n Lg1 .3n Outer dimension Metal Width CTI 78µm ×84µm 6µm
  7. 7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 146 Fig. 5. Simulated NF and S21 of the Fig. 6. Simulated S12 and S11 of the proposed LNA proposed LNA Fig.7 Simulated S21 with k=0 and k=.8 Fig. 8 Simulated S11 for two different feedback path (node A and B) IV. CONCLUSION In this paper, a LNA for X/Ku band applications was demonstrated using 0.18µm CMOS technology. Modified resistive feedback cascade topology was used to provide wideband input matching and flat frequency response across 8-18GHz band. CTI at the inter stage network of the circuit was used to attain small chip area and reduce the loss associated with inductors. V. REFERENCES [1] B. Afshar, Ali M. Niknejad, “X/Ku Band CMOS LNA design techniques,” IEEE Custom Integrated Circuits Conference, pp. 389--392, 2006. [2] P. Heydari, “Design and Analysis of a performance- Optimized CMOS UWB Distributed LNA,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp.1892--1905, September 2007. [3] P.-Y. Chiang, C.F. Jou, H.-I Wu, Z.-Y. Huang “A 10~18GHz Wide-band Transformer feed- back LNA,” in Proc. IEEE Int. Workshop RFIT, 2007,pp. 66–69. [4] Y. Shim, C.-W. Kim, J. Lee, and S.-G. Lee, ‘‘Design of full band UWB common-gate LNA,’’ IEEE Microw. Wireless Compon. Lett., vol. 17, no. 10, pp. 721--723, Oct. 2007. [5] Y.-S. Lin, C.-Z. Chen, H.-Y. Yang, C.-C. Chen, J.-H. Lee, G.-W. Huang and S.-S. Lu, “Analysis and Design of a CMOS UWB mLNA With Dual- RLC- Branch Wideband Input Matching Network,”IEEE Trans. Microw. Theory and Tech., vol. 58, no. 2, pp. 287--296, February 2010.
  8. 8. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 147 [6] A. Meaamar, C.-C. Boon, K.-S.Yeo, M.-A. Do, “Wideband Low Power Low-Noise Ampli- fier in CMOS Technology,” IEEE Tran. on Circuit &System, vol. 57, no. 4, pp. 773--782, April 2010. [7] M. Chen, and J. Lin, “A 0.1--20 GHz Low-Power Self-Biased Resistive Feedback LNA in 90 nm Digital CMOS,’’ IEEE Microwave & Wireless Component Letters, vol. 19, no. 5, pp. 323--325, May 2009. [8] H. W. Chiu, S. S. Lu, and Y. S. Lin, ‘‘A 2.17 dB NF, 5 GHz band monolithic CMOS LNA with 10 mW DC power consumption,’’ IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 813--824, Mar. 2005. [9] M. L. Edwards and J. H. Sinsky, “A new criterion for linear 2-port stability using geometri- cally derived parameters," IEEE Transactions on Microwave Theory and Techniques, vol. 40, no. 12, pp. 2303—2311 , Dec. 1992. [10] S. Shekhar, J. S. Walling, and D. J. Alstot, “Bandwidth extension technique for CMOS amplifier,” IEEE J. solidState Circuits, vol. 41, no. 11, pp. 2424--2438, Nov. 2006. [11] Archana Agarwal, Manish Kumar, Priyanka Jain and Shagun Maheshwari, “Tapered Circular Microstrip Antenna with Modified Ground Plane for UWB Communications”, International Journal of Electronics and Communication Engineering & Technology (IJECET), Volume 4, Issue 3, 2013, pp. 43 - 47, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472. [12] P.Sreenivasulu, Krishnna veni, Dr. K.Srinivasa Rao and Dr.A.VinayaBabu, “Low Power Design Techniques of CMOS Digital Circuits”, International Journal of Electronics and Communication Engineering & Technology (IJECET), Volume 3, Issue 2, 2012, pp. 199 - 208, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472. [13] Vikas Kumar and R. S. Gamad, “Design of a UHF Band LNA using Active Inductor with FFP Noise Cancelling Technique”, International Journal of Electronics and Communication Engineering & Technology (IJECET), Volume 4, Issue 3, 2013, pp. 124 - 131, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.

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