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  • 1. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME188DATA TRANSMISSION WITH GBITS SPEED USING CMOS BASEDINTEGRATED CIRCUITS FOR OPTO-ELECTRONIC INTERFACESAND APPLICATIONSR. K. Singh, Ashish DixitDepartment of Electronics & Comm. Engineering,Kumaon Engineering College (KEC),Dawarahat (Almora), UttarakhandABSTRACTThe performance of the data transmission using the principle of the opticalcommunication can be enhanced further simply by increasing both the wavelength count andbit rate per channel, so as to improve the utilization of the optical fiber bandwidth. Thisapproach in turn requires the most suitable device structures and the technologies for bothopto-electronic transducers and the associated driving electronics circuitry. The numberof transistor stages required between the power and ground rails is only two so that theminimum supply voltage required is one threshold voltage plus one pinch-off voltage. Thepre-amplifier is a balanced two-stage configuration such that the effect of bias-dependentmismatches is minimized. A new inductive series-peaking technique has been introduced soas to enhance the bandwidth by utilizing the resonance characteristics of LC networks. Inaddition to this arrangement, a new negative differential current feedback technique has beenput forward for the discussion so as to boost the bandwidth of the system and to reduce thevalue of peaking inductors. This pre-amplifier circuit has been implemented in TSMC 0.18µm, 1.8 V, 6-metal mixed mode CMOS technology and is analyzed using Spectre fromCadence Design Systems with BSIM3v3 device models. For an optical front-end with a 0.3pF photodiode capacitance, simulation results demonstrate that the pre-amplifier hasbandwidth of 3.5 GHz and provides a trans-impedance gain of 66 dB. The total chip area isapproximately 1 mm2and the DC power consumption is about 85 mWINTERNATIONAL JOURNAL OF COMPUTER ENGINEERING& TECHNOLOGY (IJCET)ISSN 0976 – 6367(Print)ISSN 0976 – 6375(Online)Volume 4, Issue 3, May-June (2013), pp. 188-203© IAEME: Impact Factor (2013): 6.1302 (Calculated by GISI)www.jifactor.comIJCET© I A E M E
  • 2. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME189Keywords: Optical fiber transmission, Optoelectronic device, Integrated circuit, Highrate, State of the art, Two-dimensional electron gas transistor, Gallium arsenide, Indiumphosphide current-mode circuits, preamplifier, inductive peaking, current feedbackI. INTRODUCTIONThe Optical communications is one of the corner stones of today’s revolution in theinformation technology. The vast distances of optical fiber span the globe, connecting theworld together in an intricate communications infrastructure. With the drive towards portableand multimedia communications, the system has increasingly faced with the challenge ofbringing the capacity of our communications infrastructure directly to the user, providingseamless access to vast quantities of information, any where and anytime. Whether it is thetransfer of an image from a digital camera to a laptop computer or the communication of datawithin a massively parallel computer, there is an urgent need to develop new methods of highspeed data communications. Light offers many advantages as a medium for communication.Whether travelling through free space or through optical fiber, light enjoys unequalled channelbandwidth, and is capable of data rates in the terabits per second. This immense capacity isdue to the nature of the photons that constitute an optical signal. As such, the optical signalsneither generate nor are sensitive to electromagnetic interference (EMI), parasitic coupling,and other problems faced by electrical. Given their advantages, optical links are rapidlyexpanding into application areas beyond traditional fiber-optic links. Three simple applicationsof so-called “carrier” applications that are concerned with transporting information across thegreatest possible distance are free-space inter satellite links, fiber-to-the-home (FTTH) andterrestrial free-space links for inter-building [01-03]. The shorter distance applications includethe optical-based local area networks (LANs) as represented by Asynchronous Transfer ModePassive Optical Networks (ATMPON and Gigabit Ethernet standards based applications thatinvolve the optical communications within digital systems or in large computers i.e. generallyreferred to as optical interconnect that include smart pixel arrays, opto-coupler arrays andoptical backplanes [06]. In particular, the short-range “point-and-shoot” systems in accordanceto the Infrared Data Association (IrDA) provide a simple solution for transferring informationto and from portable devices, offering high data rates at low cost and with a small form factorthat is not prone to mechanical wear. The success of such short-range systems is particularlytelling of how optical communication systems are likely to proliferate in the future: as of 1998,over 100 million laptops, digital cameras, and other devices were shipped equipped withIrDA-compatible serial ports, and currently over 40 million new devices are being producedyearly. The IrDA wireless link has overshadowed both the Universal Serial Bus (USB) andIEEE 1394 FireWire to become the leading serial-port alternative for connectivity [04-07].Figure 1.1 shows the basic elements of an optical link. On the transmit side, an informationsource produces a data stream that is encoded and sent to the appropriate drive circuitry usedto modulate the optical signal generated by either a light emitting diode (LED) or laser. Thesignal propagates through free space or through a waveguide such as optical fiber until itreaches the photo detector on the receiver end. The photo detector converts the optical signalinto an electric current that is sensed by the optical pre-amplifier and regenerated to asufficiently strong voltage signal from which the original data can be recovered by thedemodulator.
  • 3. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME190Figure 1 Block diagram of a typical optical link.The expansion of optical communications into new applications has created excitingopportunities for the research and innovation of optical receivers. While the growth of fiber-optic networks in the last few decades has refined our understanding of optical receivers, itsprimary focus has been on speed and sensitivity. With the expansion of opticalcommunications come new requirements on receiver designs. Probably the most widespreadtrend has been that of increased system integration and the drive to reduce systemcomponents, cost, and size. Traditionally, optical receivers have not been subject to manysystem level constraints since optical receivers for long-haul fiber-optic networks areprincipally designed for performance rather than cost. As such, they have typically usedadvanced high-speed semiconductor technologies such as GaAs and Si bipolar processes.Increasingly, the new optical receiver designs are being implemented in low-cost, high-integration technologies such as CMOS. However, the desire to implement in CMOS implies aneed to design receivers that keep pace with developments in CMOS technology. One of thedominant trends is the continuous reduction of the system supply voltage as shown in Figure1.2. The upper and lower boundary lines are drawn to highlight the fact that the ‘industrystandard’ voltage is disappearing, being replaced instead by a range of voltages encompassingdifferent applications. Increasingly, the supply voltage is seen as an adaptable designparameter used to optimize performance and minimize power. The logic circuits that operatewith supply voltages near or even below the threshold voltage are being reported alongsideanalog circuits that do the same. The low-voltage operation is partly driven by the desire forlow power in portable applications and in applications that require battery back-up such asfiber-to-the-home (FTTH). In the end, low-voltage operation will be crucial to the long-termviability of integrated optical receivers [08-10].Figure 2 Projected trends in system supply voltages.The recent advance in CMOS technology, mainly driven by the low-powerapplications, has significantly lowered supply voltage. The reduction in threshold voltages,however, is rather moderate in order to minimize the static power consumption arising from
  • 4. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME191sub-threshold conduction. As a result, the performance of voltage mode circuits, such asdynamic range, is affected greatly. CMOS current-mode circuits offer many attractiveadvantages over their voltage-mode counterparts. The key performance feature of current-mode circuits is their inherent wide bandwidth. The other advantages include low supplyvoltage requirement, large dynamic range, and tunable input impedance. These characteristicsmake current-mode circuits particularly attractive for high-speed interface circuitry. Theanalog amplifiers are susceptible to power and ground fluctuations caused by the switching ofdigital portion of mixed-signal circuits, such as clock and data recovery circuits in opticaltransceivers. The accuracy of current-mode circuits is severely affected by the errors due todevice mismatches. Low-voltage current-mode circuits that are insensitive to devicemismatches and switching noise are highly desirable. In addition, a main drawback of current-mode circuits is their low current gain. To increase the current gain, the size of the transistor inthe output branch can be made large, how-ever, at the cost of reduced bandwidth. Thetechnique introduced increases the bandwidth of current-mirror amplifiers by cancelling outthe dominant pole with a compensating zero obtained by inserting a resistor between the gatesof the input and output transistors of the amplifiers. In this system, an adjustable gain opticalamplifier is used in front of the photo receiver, so as to reduce both the requirement inreceiver sensitivity and the amount of gain required from the electronic amplifier. A flip-flopis then used so as to perform the decision making part. In the present scenario, the decision isusually not performed at the Gbit/s signal level because of the very limited availabilityof circuits clocked at GHz range. The signal transmission over the fiber suffers from a numberof impairments such as chromatic dispersion enhanced by the chirp characteristics of thesource, polarization mode dispersion, nonlinear channel interaction. Such impairments aregetting more and more detrimental as the bit rate increases, most often they can becompensated at the optical signal power level or electronically at the receiver level [10-12].The detailed schematic of the transmitter and receiver has been shown in figures 3 and 4respectively.Figure 3 Schematic diagram of a TransmitterFigure 4 Schematic diagram of a ReceiverII. REQUIREMENTS FOR THE GBIT/S OPTOELECTRONIC INTERFACE ICSAs discussed in the introduction of the problem, both the analog (e.g. amplifiers) anddigital ICs (e.g. MUXES) are needed for assembling the design of the optoelectronictransmitters and receivers, calling for specific requirements in terms of microelectronic
  • 5. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME192technology characteristics. For the analog parts, what matters first is the gain available overthe required bandwidth from a given technology; much attention is then paid to thepower gain cut-off frequency FMAX, known as the maximum oscillation frequency i.e.higher the FMA X, higher the available gain over a given, large, bandwidth. For thebandwidths required at a specific data transmission rate in Gbit/s range depending on theapplication requirements, only the technologies offering FMAX can be envisioned. Forexample, For a given technology, the distributed amplifier structures help getting the better interms of gain-bandwidth product: actually, assuming identical impedance for both input andoutput lines and loss-less lines, the total voltage gain (Gv) is set by both the stage(transistor) gain (Gs) with Gs = gm Z, where gm is the transistor trans-impedance, and thenumber of stages (N); a situation to be contrasted with conventional lumped amplifiers [13]:Gv ≈ Gs × N/2 (distributed amplifier) (1)Gv ≈ GsN (lumped amplifier) (2)These above mathematical expressions indicate that even with a stage gain closeto one, that is with a stage bandwidth close to FT, a large total gain can be obtainedwith distributed amplification (although limited by the line losses which set a limit to thebandwidth as well as to the number of stages), while the lumped amplifier requires the stagegain to be sensitively larger than one to provide a large total gain.Figure 5 Gain vs. bandwidth characteristics of single chip amplifiers.Thus, based on the discussion to a larger extent, the performance of theinterconnection depends on the receiver’s gain, bandwidth, power consumption, and arearequirements. These four parameters can be traded off against each other. By adjusting thenumber of amplifying stages, the transistor sizes, and the bias voltages, the receiver circuitcan be designed to optimize the link performance i.e.1) Bit Rate: The location of the poles in the receiver transfer function determines the 10–90% rise time in response o a step input. The bit rate of the overall receiver can bedetermined from the rise times of each of the components BR [14](3)where ζ determines what percentage of the bit period makes up he rise time. The rise times forthe receiver components are given in Table I. The TIA is designed to have a response thatclosely approximates a maximally flat magnitude (MFM) response, i.e. the two poles closest to
  • 6. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME193the origin are at 45. This is achieved with an appropriate value feedback resistor. It can be seenfrom Table I that receivers with a three-stage TIA are significantly slower than ones with aone-stage TIA, when both are constructed from identical amplifying stages. In general, it canbe shown that when the number of stages in a feedback loop increases, the bandwidthdecreases. However, in order to determine when three-stage TIA based receivers arecompetitive, the trans-impedance gain must be examined as well [15].Table 1 10–90% rise time formulas2) Transimpedance Gain: The trans-impedance of the receiver determines its sensitivity. Inorder to ensure stability and eliminate resonance peaking in the receiver transfer function, thetrans-impedance of the amplifier is adjusted to approximate a maximally flat magnituderesponse. The trans-impedance can then be calculated based on the gain, bandwidth, inputcapacitance and transconductance of the amplifying stages, the total number of stages, and thephotodiode capacitance. For the one-stage TIA to have a maximally flat magnitude response,the input open-loop pole must be smaller than the second open-loop pole by a ratio of [16](4)Cpd is the photodiode capacitance plus any parasitic capacitance, and is taken as 100 fF in theanalysis. This corresponds to a flip-chip bonded 400 m MQW detector. Since opticalalignment and spot sizes are not expected to scale as the gate length of the technology, thisvalue is constant for all three technologies considered in this paper. The value of Rf obtainedby solving (2) is used to determine the trans-impedance of the one-stage TIA, which is givenby [17](5)The three-stage TIA has four open-loop poles, one at fin and three overlapping poles at fout. Inorder for the three-stage TIA to approximate a maximally-flat magnitude transfer function, theinput open-loop pole must be related to the other three open-loop poles by [18](6)
  • 7. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME194The trans-impedance of the three-stage TIA is given by equation 6, with 1+ Av-1replaced with 1+ Av-3, since there are now 3 stages providing gain in the TIA. The overalltrans-impedance gain, TZ, is the receiver’s output voltage divided by the input current, and isgiven by the voltage gain of the -stage post amplifier times the trans-impedance of the TIA[19](7)3) Noise: The circuit noise introduced by the receiver and detector is referred to the receiverinput for signal to noise ratio determination.4) Power: The electrical power dissipation of the (N+P) stage receiver is determined from thebias current Ids, and the power supply voltage Vdd, and can be written:(8)There is additional power dissipation due to the switching of the node capacitances inthe receiver, but this component is orders of magnitude less than the power dissipation due tothe bias current [20]. The low frequency noise is another feature of importance, as itimpacts the spectral purity of oscillators and multipliers (the jitter tolerances are quitestringent for the various circuits, as the peak to peak jitter should be lower than 2 ps).Digital lCs operating in the range of Gbit/s are often thought of as mixed-signal lCs as theirmicrowave/analog features have a major impact on their digital operation. Whenconsidering a basic assembly of logic gates, the operating speed is often quoted through thegate propagation delay time (xr, o), which depends on both the switching transistor intrinsicspeed and the response time of the surrounding circuit, as shown in the following expression:TpD = (2riFT)-1 + n(Cp +CI) AV/I (9)where n is the gate fan-out (usually small in very high-speed ICs), C~ and Cpstand for the input capacitance of a gate and the parasitic (wiring) capacitance respectively;AV and I are the voltage swing and the active load current respectively. To keep withgeneral statements, one could point out the following requirements [21-25]:• high current density, so as to reduce CIfI: this obviously implies smalldimension transistors in order to avoid thermal problems, as well as a highcurrent density;• low wiring capacitance: this calls for a compact layout, and thick enoughdielectric layers to reduce interconnection capacitance. This is especiallyimportant for FET technologies as they are usually characterized by lower C I(and lower currents) than bipolar processes as shown in figure 6.
  • 8. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME195Figure 6 Digital circuits speed vs. device performance,III. CURRENT STATUS OF III-V ELECTRONIC TECHNOLOGIES FOR 40GBIT/S ICSThe semiconductor technologies considered presently for the fabrication of 40 Gbit/sICs include SiGe bipolars, GaAs pseudomorphic and metamorphic HEMTS and HBTS(Heterojunction Bipolar Transistors), InP HEMTS and HBTS. Together these technologieshave already produced los able to allow the demonstration of first generation 40 Gbit/ssystems, even though further developments are obviously needed to obtain chip sets able to fitthe requirements of commercial optical systems. These various technologies keep evolvingand make continuous progress in terms of high-speed performance, consumption and/orcost. As an example, during the last 10 years, the speed of static frequency dividers has beenimproved by a factor of 2.5 to 5 for the InP and SiGe bipolar technologies respectively [26].With this evolution in mind, one can also envision Si CMOS to be finding applications in a40 Gbit/s chip set, in particular as transmission impairments mitigation will require rathercomplex circuits. Shrinking the gate length below 100 nm, introduction of SiGe p-MOSFETstructure and other developments presently in progress may bring new openings for CMOSin 40 Gbit/s applications [27]. The main factors that will decide which technologies will bechosen are probably the following, their respective weight depending on the application:• Performance i.e. the key factor even though the specifications are not yetfully defined and some margin will be appreciated to overcome dispersion,aging, characteristics degradation after packaging,• Target specifications i.e. as the optoelectronic components or even thetransmission fiber characteristics evolve, specifications may change, making itmore appropriate to use another technology for a given function.• DC power consumption i.e. as the wavelength-multiplexing capability is asystem requirement, low consumption is an important factor to reduce footprintof terminal equipments. A total power consumption of 10-12 W is presentlytargeted for a transmitter-receiver pair.• Gate count is another important aspect, since signal processing is becomingmost useful (FEE, impairment mitigation) as bit rate increases.• Cost is obviously an issue and this applies to the complete transponder.
  • 9. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME196TABLE 2: Figure of merit for various materials [28]III.1. GaAs ICs for 40 Gbit/s applications:The GaAs microelectronics device has long been a choice of the technology for thedesign of high-speed circuits for optical transmission, in particular with MESFETS used asphoto receiver preamplifiers and in digital ICs. As bit rates kept increasing, the MESFETtechnology ran out of performance, leaving the field to hetero-junction technologies thatare now exclusively used in 40 Gbit/s high-speed interfaces [29].IILI.1. GaAs HEMTS and 40 Gbit/s analog circuits:Since the GaAs HEMT was invented in 1980, many improvements have beenbrought to the structure, in particular with the introduction of the so-called k-doping of thebarrier layer and the pseudomorphic strained InxGal_xAS channel, with an In content of x= 0.25. This pseudomorphic channel is characterized by a smaller band gap than GaAs,which increases the conduction band discontinuity with the barrier (hence a higher electronsheet density in the channel), and higher electron mobility than GaAs as shown in figure 7.These characteristics translate into a higher current density, hence larger FT and FMAX, whileretaining very attractive break- down behavior [30]. However, this is not possible since thecritical strained channel thickness beyond which dislocations appear would become too smallto accommodate a large enough carriers density. To overcome this limit, a new concept wasintroduced with the metamorphic HEMT (M-HEMT) characterized by an InGaAs channelwith a much higher In content (usually 0.3 <x< 0.5). The InGaAs channel and its lattice-matched AllnAs barrier are grown on a strain-relaxed thick buffer that accommodates thelattice mismatch and absorbs dislocations originating from the GaAs substrate.Figure 7 GaAs P-HEMT and InP composite channel HEMT structures [31]
  • 10. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME197IIl.l.2. GaAs HBTS and mixed signal circuits:The potential of GaAs HBTS for the fabrication of optical telecommunications ICS hasalso been explored. Worth noting is the successful development of a 10 Gbit/s chip set byNortel some years ago [32]. Pushing further this technology towards 40 Gbit/s applications hasbeen an objective for a few research domains, and 20 Gbit/s-class digital circuits have beenalso produced to some extent [34-35]. More recently, using a highly doped re-grown extrinsicbase structure, which helps reducing the access base resistance and allows high FMA X (closeto 200 GHz for an F T above 100 GHz), the research demonstrated a 43 Gbit/s receiver chipset including a decision circuit [36]. However, the most developments in GaAs HBTtechnology are focused on microwaves applications, such as power amplifiers for handsets, with little development effort left for adjusting to the requirements of very high bit ratecircuits i.e. reducing the emitter width and the base-collector junction area to improve cut-offfrequencies, demonstrating a new base material to lower the turn-on voltage and reduce thepower consumption [37].III.2. 40 Gbit/s ICs on InP substrates:InP and its related compounds, AlInAs and InGaAs, have produced transistorswith record high frequency performances for quite a few years; with the projecteddevelopment of optical transmission at 40 Gbit/s, first commercial microelectronicsapplications have been envisioned for those materials, in spite of both the brittle substratesmaking processing more difficult than with GaAs wafers and the limited substrate size (3to 4 inch semi-insulating wafers are presently used; but one should notice that some 3-4inches GaAs foundries are still profitable) [38]. However, the broad variety of availablehetero structures in the InP family offers the device designer a full range of combinations tooptimize HEMTS and HBTS, in terms of high-speed and high-output voltage [39].III.2.1. InP-based HEMT circuits:A record cut-off frequencies have been reported since the early 90s for InGaAs-channel InP-based HEMTS, with values of 350 GHz for F T and 600 GHz for FMA x for0.1 lain gate length, recently increasing to 560 GHz for F T at 25 nm gate length [40].These figures actually translate the high electron saturation velocity in InGaAs and the highconfinement energy of the InA1As/InGaAs hetero junction (about 0.5 eV). Such highfrequency performances have led to record high bit rate operation of digital ICs, such asMUXes, DMUXeS and decision circuits, and a complete 40 Gbit/s AllnAs/GaInAs HEMTchip set a few years ago [41]. The first and foremost circuits have been fabricated,including arrays of monolithically integrated photodiode/preamplifiers (designed for 10Gbit/s applications and wide-band (90 GHz) distributed amplifiers as shown in figure 8,characterized by a state of the art 410 GHz gain-bandwidth product and a promisingoutput swing of 2 V [42-45].
  • 11. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME198Figure 8 InP composite channel HEMT 10 stage distributed amplifier [46]III.2.2. InP-based HBT circuits:An InP-based HBT static frequency divider operating at 39 GHz has been discussedquite earlier. However, it is only in recent years that the InP-based HST technology wasidentified as a choice technology for assembling a 40 Gbit/s digital chip set. The HSTtechnology can be considered as a maturing technology and different InP structures andprocesses are still investigated worldwide: single or double hetero structure (D-HBT), AlInAsor InP emitter, InGaAs or GaAsSb base, Zn, Be or C doping of the base, now takingadvantage of both of the selective etching properties of the emitter-base and base-collector hetero junctions, and the low recombination velocity of InGaAs (or GaAsSb)surface, small dimension HBTS (emitter width below 1 lam) can be processed, as neededfor high frequency / low power consumption performances [47].Figure 9 Schematic band diagrams of lnP D-HBT structuresIn the InP HBT technology, this is competing with the SiGe one i.e. MUX andDMUX ICs have also been developed in the later technology, as well as wide bandamplifiers, and further improvements with the performances are likely to result fromcontinuous progress in cut-off frequencies (an F T > 200 GHz has recently beenreported at an emitter width of 0.12 ~tm. The static frequency dividers operating above80 GHz have been discussed, at a frequency close to the best InP. However, very thincollectors are required to produce such fast devices, which sets a limit to the output voltagethey can sustain. The InP D-HBT process developed at or, to+ is based on a structurewith a graded base grown by using the chemical beam epitaxial approach [48-52].
  • 12. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME199Figure 10 Evolution of InP HBTS cut-off frequencies with emitter width [53]A mixed dry and wet chemical etching allows for an undercut collector, which isinstrumental in reducing the base-collector capacitance and reaching high cut-offfrequencies (F T = 180 GHz; FMA x = 220 GHz), suitable for designing 40 Gbit/s ICS.A number of 40 GbitJs-class circuits, such as a 2.2 V selector-driver and more recently afamily of D Flip-Flops aimed at 3R regeneration or Decision characterized by a highsensitivity, a large phase margin and a low jitter well below 1 ps as shown in figure 11[54].Figure 11 Eye diagrams illustrating the regenerating characteristics of InP D-HBT flip-flops[55]CONCLUSIONWith the first 10 Gbit/s WDM systems now in full operation, the focus of theresearch laboratories has now shifting towards more efficient systems with denserwavelength multiplex or higher bit rate. The transmission of the data at a rate of 40 Gbit/sper channel has motivated the development of new components for dispersionmanagement, faster optoelectronic devices and lCs enable to operate at such high bitrate. In the last few years, ICs were reported in various technologies, able to operate at theproper speed, then offering the required functionality with the possible further improvementneeded in terms of power consumption, most circuits needed for the fabrication oftransmitters and receivers operating at 40 (or 43 Gbit/s). Large signal models able todescribe accurately the operation of active devices and specific circuit design tools andmethodologies which have been purposely developed also contributed largely to thedemonstration of circuits suitable to 40 Gbit/s transmission, that is offering some speedmargin with respect to system specifications. Now in order to make 40 Gbit/s transmissiona reality, it is mandatory to demonstrate its cost effectiveness, which applies to the costof both transmission and terminal equipments. For that reason, it is still questionable toidentify short reach or long haul transmission as the first market for 40 Gbit/s transmissions.
  • 13. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME200ACKNOWLEDGEMENTSThe authors are thankful to Prof. D. S. Chauhan (Vice Chancellor, UTU) for providingthe environment for this work, Mr. Aseem Chauhan (Additional President, RBEF), MajorGeneral K. K. Ohri, AVSM, Retd. (Pro VC, AUUP, Lucknow Campus), Prof. S. T. H. Abidi(Director, ASET) and Brig. Umesh K. Chopra, Retd. (Dy. Director, ASET) for their kindcooperation, motivation, kind and most valuable suggestions.REFERENCES[1] Sitch (j.) Integrated circuits for fiber systems, (2002) digest of ieee gaas icsymposium, pp. 19-22.[2] Tsai (h.s.), kopf (r.), melendes (r.), melendes (m.), tate (a.), ryan (r.), hamm (r.),chen (y.k.) 90 ghz baseband lumped amplifier, (20001, electron. Let., 36, pp. 1833-1834.[3] Wooten (e.l.), kissa (k.m.), yi-yan (a.), murphy (e.j.), lafaw (d.a.), halemeier (p.e),maack (d.), atranaslo (d.v.), fritz (d.j.) mcbrien (g.j.), bosst (d.e.), a review oflithium niobate modulators for fiber-optic communications systems, (2000), ieeejournal selec.topics quant. Electron., 6, pp. 69-82.[4] Scavennec (a.), giraudet (l.) Optical photodetectors, in fiber optic communicationdevices, springer 2001, editors norbert grote, herbert venghaus.[5] Green (m.m.), momtaz (a.), vakilian (k.), wang (x.), jen (h-c.), chung (d.), cao (j.),carerosa (m.), hairapetian (a.), fujimori (1.), car (y.) Oc-192 transmitter in standard0.18/am cmos, (20021, techn. Digest teee tsscc, 1, pp. 248-249.[6] Razavi (b.) Prospects of cmos technology tot high-speed optical communicationcircuits, (2002), ieee journ. Solid-state circuits, 37, pp. 1135-1145.[7] Johnson (e.o.) physical limitati•ns on frequency and power parameters oftransistors, ( 1965)• rca review, 26, pp. 163-177.[8] Delage (s.) Heterojunction bipolar transistors for millimeter-wave applications :trends and achievements, (2001), annales tall(com., 56, n ° 1-2, pp. 5-14.[9] Bollaert (s.), cordier (y.), zaknoune (m.), parenty (t.), happy (h.), cappy (a.),hemts capability tbr millimeter-waves applications, (2001), annales tdldcom., 56,n ° 1-2, pp. 15-26.[10] Virk (r.s.], camargo (e.), hajji (r.), parker (s.), benelbar (r.), notomi (s.), ohnishi(h.) 40-ghz mmics for optical modulator driver applications, (2002), teee mtr-symposium, pp. 91-94.[11] Yuen (c.), laursen (k.), chu (d.), mar (k.), 50 ghz high output voltage distributedamplifiers for 40 gbit/s eo modulator driver application, (20(/2), teee mrr-symposium,pp. 481-484.[12] Lefevre (r.), mouzzanar (w.), lestra (a.), vuye (8.), ferling (d.), jorge (f.), pillet(o.), idler (w.), double distributed gaas p-hemt ics lor 40 gbit/s high output voltagedriver modules, (2001), techn. Digest gaas mantech, pp. 134-136.[13] Nowotny (u.), lao (z.), thiede (a.), lienrlart (h.),hornung(j.), kaufel (g.), kohler (k.),glorer (k.), 44 gbit/s 4:1 multiplexer and 50 gbit/s multiplexer in pseudomorphica1gaas/gaas hemt technology, (1998) ieee tscas, technical dig. Ii, pp. 201-203.
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