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Analysis and design of ultra low power adc for wireless sensor networks 2
1. INTERNATIONAL JOURNAL OF ELECTRONICS AND International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEMECOMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)ISSN 0976 – 6464(Print)ISSN 0976 – 6472(Online)Volume 4, Issue 1, January- February (2013), pp. 264-275 IJECET© IAEME: www.iaeme.com/ijecet.aspJournal Impact Factor (2012): 3.5930 (Calculated by GISI) ©IAEMEwww.jifactor.com ANALYSIS AND DESIGN OF ULTRA LOW POWER ADC FOR WIRELESS SENSOR NETWORKS 1 2 Sandeep Mehra , CN Khairnar 1 (ECE, JJTU, Jhunjhunu, Rajasthan, India) 2 (FCE, MCTE, Mhow, M.P., India) ABSTRACT In the past 10 years, Wireless Sensor Networks (WSN) have grown from a theoretical concept to a burgeoning modern technology. WSN consists of thousands of cubic millimeter sized nodes(mote) which have the capability to independently sense, compute and communicate. These motes are energy autonomous and are deployed in ad-hoc manner at places where the replacement of batteries is not possible. Because of the small size of the mote, energy management is a key constraint of the design. Energy consumption must therefore be minimized in every part of the system. This paper briefly examines every part of a mote and carries out an in depth study of architectural and circuit design techniques for ultra low power ADC for maximizing the battery life of a mote and thereby improving system survivability. We compare various available ADC architectures and propose most power efficient architecture and specifications for achieving the required ultra-low energy operation. Keywords: ADC, Motes, Ultra low power 1. INTRODUCTION WSNs consists of tens to thousands of distributed motes that sense and process data and relay it to the end-user. Applications for WSNs range from military target tracking to industrial monitoring and home environmental control. The distributed nature of micro sensor networks, capacity of the power source and small size of the mote places an energy constraint on the sensor nodes and hence energy management is a key constraint of the design. An AA- sized battery contains roughly 250 µA-years of charge or about 12000J . The average power consumption of an inch-scale mote, then, must be in the range of tens to hundreds of microwatts or just a few joules per day. Research into energy scavenging  suggests that 264
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEME Januarymicro sensors can utilize energy harvested from the environment. Energy harvesting schemesconvert ambient energy into electrical energy, which is stored and utilized by the node. The bientmost familiar sources of ambient energy include solar power, thermal gradients, radio radio-frequency (RF), and mechanical vibration. TABLE1 gives a comparison of power densities ofsome energy harvesting technologies . Table 1: Power Densities of Energy Harvesting Mechanisms . Technology Power Density (µW/cm2) Vibration - electromagnetic 4.0 Vibration - piezoelectric 500 Vibration - electrostatic 3.8 Thermoelectric (50C difference) 60 Solar – direct sunlight 3700 Solar – indoor 3.2The key challenge of next generation motes is minimizing energy requirement throughaggressive optimization in all layers of design. This paper examines architectural and circuitdesign techniques for ADC, which is one critical component of a large scale WSN  and ,propose most power efficient architecture with specifications for WSN. Section 2 describestypical architecture of a WSN. Sections 2 and 4 examines the architecture and circuit designof the various ADCs and propose architecture and specifications required for ultra ultra-lowenergy operation of ADC finally, Section 5 provides a short conclusion.2. COMPONENTS OF A WIRELESS SENSOR NODE WSN are comprised of a number of mm3 sized spatially distributed sensor nodeswhich cooperate to monitor the physical qualities of a given environment. A wireless sensornode is composed of four basic components (Fig.1): a sensing unit, a processing unit :(microcontroller), a transceiver unit and a power unit. In the following sub sections we will an .explain the hardware components of a sensor mote. Each of the components should bedesigned from both operation performance and energy efficiency viewpoint. Fig.1: Components of a typical Wireless Sensor Node. omponents 265
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEME2.1 Sensing Unit A sensor is a device that measures some physical quantity and converts it into a signalto be processed by the microcontroller. A wide range of sensor types exist including seismic,thermal, acoustic, visual, infrared and magnetic. Sensors may be passive (sensing withoutactive manipulation of the environment) or active (using active manipulation/probing of theenvironment to sense data, e.g. radar) and may be directional or Omni-directional. TABLE2lists some common micro-sensors and their main features .A wireless sensor node mayinclude multiple sensors providing complimentary data Table 2 : Power consumption and capabilities of commonly available Sensors  Sensor Type Current Time Requirement Manufacturer Photo 1.9 mA 330 µS 2.7 - 5.5V Taos Temperature 1 mA 400 mS 2.5 - 5.5V Dallas Semiconductor Humidity 550 µA 300 mS 2.4 - 5.5V Sensiron Pressure 1 mA 35 Ms 2.2 - 3.6V Intersema Magnetic Fields 4 mA 30 µS Any Honeywell Acceleration 2 mA 10 mS 2.5 - 3.3V Analog Devices Acoustic 0.5 mA 1 mS 2 - 10V Panasonic Smoke 5 µA -- 6 - 12V Motorola Passive IR (Motion) 0 mA 1 mS Any Melixis Photosynthetic Light 0 mA 1 mS Any Li-Cor Soil Moisture 2 mA 10 mS 2 - 5V Ech2oThe sensing of a physical quantity such as those described typically results in the productionof a continuous analog signal, for this reason, a sensing unit is typically composed of anumber of sensors and an analog to digital convertor (ADC) which digitizes the signal. Asbrought earlier ADC is one the major power consuming component of a mote especially inlow power mode. TABLE 3 brings out the average power consumption for the maincomponents of Micro-LEAP node. Table 3: Average power consumption for the main components of Micro-LEAP node  Active Low-power Component Power (mW) % Power (mW) % Processor 2.69 1.95% 2.81 19.93% Radio 72.74 52.70% 9.40 66.57% Flash memory 0.029 0.02% 0.027 0.19% Sensor, MEMS 1.18 0.86% 0.001 0.01% Sensor, ECG 55.41 40.14% 0.24 1.70% 16-bit ADC 5.97 4.33% 1.64 11.60% Total 138.04 14.122.2 Processing Unit A microcontroller provides the processing power for, and coordinates the activity of amote. Unlike the processing units associated with larger computers, a microcontrollerintegrates processing with some memory provision and I/O peripherals; such integrationreduces the need for additional hardware, wiring, energy and circuit board space. In addition 266
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEMEto the memory provided by the microcontroller, it is not uncommon for a mote to include someexternal memory, for example in the form of flash memory. When we select a commercialmicrocontroller family for a WSN application, we need to consider some of the applicationrequirements including power consumption, voltage requirements, cost, support for peripherals, andthe number of external components required. Some of these are explained in following subsections.2.2.1 Power consumption Different microcontrollers have very different power consumption levels. For instance, 8 or16 bit microcontrollers have varied power consumption between 0.25 to2.5 mA per MHz. Such awide difference (over 10 times) between low-power and standard microcontrollers determines theWSN system performance significantly. The power consumption in sleep mode also varies from 1µAto 50 µA across various CPUs available which makes considerable difference as the CPU is expectedto be idle for more than 99% of time. Energy consumption in microcontroller also depends on howmuch time the operation of entering / exiting sleep mode takes.2.2.2 CPU speed In a WSN, the CPU needs to execute the wireless communication protocols and perform localdata processing. Those operations do not need a high-speed CPU. That’s why most of today’s WSNCPUs have a speed of less than 4MHz. Some WSN CPUs can dynamically change the operatingfrequency as per the requirement and reduce power consumption.2.3 Transceiver A transceiver unit allows the transmission and reception of data to other devices connecting amote to a network. A micro-sensor radio shares the same key design constraints as the other circuitblocks, including (a) low standby power consumption, (b) fast switching into and out of standby, and(c) energy efficient operation when active. However, since radios operate at significantly higherfrequencies than the rest of the micro-sensor node and consume milliwatts of power when on, theyhave their own specific constraints and limitations and for short range transmission. At GHzfrequencies, the modulator components (frequency synthesizers, mixers, etc.), rather than the poweramplifier, dominate power consumption. Hence, for short packet sizes, the start-up energysignificantly increases the overall transmission energy . Fig.2 illustrates the effect of start-up timeon energy efficiency by plotting the energy to transmit a bit versus packet size. The inefficiencyintroduced for short packet sizes can only be improved by reducing the start-up time. Therefore,implementing an energy efficient transmitter for a micro sensor implies designing a high data rate,low power, and fast start-up transmitter. Fig.2: Impact of start-up time on transmitter’s energy consumption 267
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEME2.4 Power Source and its conservation As an untethered computing platform, mote must be supported by a power unit whichis typically some form of storage (battery). At present there are three common batterytechnologies are used in WSNs, i.e., Alkaline, Lithium, and Nickel Metal Hydride. An AAAlkaline battery is rated at 1.5 V, but during operation it ranges from 1.65 to 0.8 V. With avolume of 8.5 cm3, it has an energy density of approx 1500 Joules/cm3. While providing acheap, high capacity energy source, the major drawbacks of alkaline batteries are the widevoltage range that must be tolerated and their large physical size. Additionally, lifetimesbeyond 5 years cannot be achieved because of battery self-discharge. In comparison, Lithiumbatteries provide an incredibly compact power source. With a volume of 1 cm3, it has andenergy density of 2400 J/cm3. Additionally, they provide a constant voltage supply thatdecays little as the battery is drained. One of the drawbacks of lithium batteries is that theyoften have very low nominal discharge currents. Nickel Metal Hydride batteries are the thirdmajor battery type. They have the benefit of being easily rechargeable. The downside torechargeable batteries is a significant decrease in energy density. An AA size NiMH batteryhas approximately half the energy density of an alkaline battery at approximately 5 times thecost and produce 1.2V. Because many system components require 2.7 volts or more, they itmay not be possible to operate directly off of rechargeable batteries . Fig. 4 illustrates thebattery characteristics for Lithium and Alkaline batteries . The life of power source of amote can be increased by power scavenging components (for example, solar cells) and powerconservation techniques such as dynamic voltage scaling. Energy from power scavengingtechniques may only be stored in rechargeable (secondary) batteries and this can be auseful combination in WSN environments where maintenance operations like batterychanging are impractical, such as military and security applications. TABLE4 lists a fewexample application domains with an estimate of their deployment lifetimes and computationrequirements . Fig.3: Battery characteristics for Lithium and Alkaline batteries . 268
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEME Table 4: Application domains of WSN with an estimate of their deployment lifetimes and computation requirements . Computation Desired requirements ExampleApplication domain lifetimes (Sample rates)Scientific applications • Habitat/weather Months/decades Very low Great Duck Island monitoring • Volcanic eruption detection Months/decades mid Volcano WSNMilitary and securityapplications • Building/border Years/decades low intrusion detection • Structural and earthquake Years/decade low/mid monitoring • Active battlefield Sniper sensing Months Mid/high detection/localizationMedical applications • Long-term health Days low monitoring (pulse) • Untethered medical instruments (ECG) Days Med EKG moteBusiness applications • Supply chain Months low management • Expired/damaged Months low goods tracking • Factory/fab monitoring Months/years Med/high Industrial WSN3. ADC ARCHITECTURES AND THEIR APPLICATION AREAS Depending upon different applications different versions of converter topologies havecome into the world of mixed signal design. Most ADC applications today can be classifiedinto four broad market segments i.e. data acquisition, precision industrial measurement,voice-band and audio, and high speed (implying sampling rates greater than about 5MSPS).A very large percentage of these applications can be filled by successive-approximation 269
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEMEregister (SAR), sigma-delta (∑−∆), and pipelined ADCs. The successive-approximation ADCis by far the most popular architecture for data-acquisition applications, while Sigma-DeltaADC is preferred in precision measurementAnd pipelined ADC is chosen for video-audio and high speed applications. The resolution-speed comparison among the popular ADC architectures along with their primary applicationareas is shown in Fig.4 . Fig.4: ADC architectures, applications, resolutions and sampling rates .A comparative study of above listed ADC architectures is presented in followingsubsections:-3.1 Pipelined ADC A pipelined ADC employs a parallel structure (Fig.5) in which each stage works onone to a few bits (of successive samples) concurrently. The inherent parallelism increasesthroughput, but at the expense of power consumption and latency. Pipelined ADCs frequentlyhave digital error correction logic to reduce the accuracy requirement of the flash ADCs (i.e.comparators) in each pipeline stage. A pipelined ADC generally takes up significant siliconarea and for more than 12 bits of accuracy usually requires some form of trimming orcalibration. Fig.5 : Simplified block diagram of pipelined ADC. 270
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEME3.2 Sigma-Delta ADC The Sigma-Delta (∑−∆) converter is a primitive, one-bit ADC (Fig.6) operating at a very highsample rate which averages the results, to obtain a high-resolution result. The digital representation ofthe input signal is determined by the percentage of ones in the high-speed bit stream. This isaccomplished by a circuit called a decimation filter to determine the final conversion value. Sigma-Delta converters have the innate advantage of requiring no special trimming or calibration, even toattain 16 bits of resolution. But, the process of sampling many times (at least 16 times and often more)to produce one final sample dictates that the internal analog components in the Sigma-Deltamodulator operate much faster than the final data rate making the architecture more power hungry.Moreover, the digital decimation filter is also a challenge to design and consumes a significantamount of silicon area. Fig.6: Continuous-time 3rd order Σ ∆-modulator block diagram .3.3 Successive Approximation Register (SAR) ADC SAR ADC is the architecture of choice for nearly all multiplexed data acquisition systems, aswell as many instrumentation applications. The SAR ADC containing an internal DAC, comparatorand a fully digital block, called successive approximation register as shown in Fig.7, is relatively easyto use, has no pipeline delay, and is available with resolutions up to 18 bits and sampling rates up to 3MSPS. In summary, the primary advantages of SAR ADCs are low power consumption, highresolution and accuracy, and a small form factor. Because of these benefits, SAR ADCs can often beintegrated with other larger functions. The main limitations of the SAR architecture are the lowersampling rates and the requirements for the building blocks (such as the DAC and the comparator) tobe as accurate as the overall system. Fig.7 : Simplified block diagram of SAR ADC. 271
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEME4. COMPARISON, SELECTION AND SPECIFICATIONS OF SUITABLE ADCFOR WSN4.1 Comparison of ADC architecture When designing ultra-low-power circuits, energy considerations drive the designprocess from the choice of architecture all the way to the actual circuit Implementation.Choosing architecture is a critical point in the design process for such systems. A properchoice of architecture can lead to dramatic energy savings compared with alternatives.Conversely, a poor architectural decision can result in a sub-optimal design regardless of howwell the individual circuit blocks are designed. While energy consumption is paramount inthis application space, there are many other considerations driving the choice of ADCarchitecture. Fig.8 groups various ADC architectures that vary roughly by their achievableresolution, speed and power consumption . Since low-power consumption is the primarydesign goal, Fig.8 shows that much architectures are poor choices. Fig.8: Common ADC architectures grouped by resolution, sampling rate and power consumption Time interleaved ADCs require multiple sets of analog hardware, leading to high powerconsumption but very fast sampling rates. Flash converters use a large number ofcomparators for a given resolution, making them impractical in most applications requiringmore than 8 bits of resolution. Folding and/or interpolation can help reduce the number ofcomparators required, but the architecture is still not well suited for low-power applications.Multi-step ADC also requires a relatively large amount of analog hardware, resulting inexcessive power consumption for application in distributed sensor networks. Some of theother ADC architectures, such as Delta-Sigma, Successive Approximation, Integrating andAlgorithmic, have been reported to work with low-power consumption, low supply voltageand with moderate resolution and speed . A comparative of reported low power ADCs ofvarious architectures reported is given at TABLE 5. Oversampled converterssuch as sigma-delta converters are potentially viable for this application. Sigma-delta ADCscan be made to be low-power for a given resolution and sampling rate, however they arecomplex, requiring sophisticated clocking and filtering. In addition, the oversampled clockneeds to be much faster than the desired sampling rate. Generating the oversampled clock oneach sensor node would likely offset any energy savings achieved in the rest of the ADC. 272
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEMETable 5 : Summary of performances of some of the reported ADCs of various architectures. Architecture Technology Supply Sampling Rate Power(µW) voltage Delta-Sigma 0.35-µm 1.8 V 1.4 MS/s 108 CMOS Successive 0.25-µm 1V 100 KS/s 3.1 Approximation CMOS Successive 0.18-µm 1V 150KS/s 30 Approximation CMOS 0.5 V 4.1 KS/s 0.85 Successive 0.18 µm 1V 12 bit, 100 KS/s 25 Approximation CMOS 12 bit, 500 S/s 200nW 8 bit, 100KS/s 19 Pipeline 0.18-µm 1.8V 16 bit, 125Ms/s 385mW CMOS Logarithmic 0.18-µm 1.8V 8 bit, 100KS/s 89-271 CMOS Integrating 1-µm CMOS 3.3 V -- -- Algorithmic AMS Bi- 2.8 V 2.9 KS/s 8.18 + 9.71 CMOS 2V 0.7 KS/s 1 + 1.3 0.8-µm BYQ4.2 Selection and specification of suitable ADC Selection of suitable ADC architecture for a particular system depends on the application.Low-power sensor networks and biomedical applications often work with low frequency datawhich is less than 50 kHz. The TABLE6 lists the range of sampling rates for different physicalphenomena. Table 6 : Sensor sampling rates of different phenomena.. Phenomena Sample rate (in Hz) Very low frequency • Atmospheric temperature 0.017-1 • Barometric pressure 0.017-1 Low frequency • Heart rate 0.8-3.2 • Volcanic infrasound 20-80 • Natural seismic vibration 0.2-100 Mid frequency (100 Hz – 1000 Hz) • Earthquake vibrations 100-160 Hz • ECG (heart electrical activity) 100-250 High frequency (>1 kHz) • Breathing sounds 100-5 k • Industrial vibrations 40 k • Audio (human hearing range) 15-44 kBy studying potential applications for large sensor networks , the critical applicationconstraints were determined to be : 273
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEME • Resolution of 8 to 10 bits; • Max sampling rate of at least 100 kHz (application dependent); • Rail-to-rail conversion range—accommodate a variety of Sensors; • Algorithmic flexibility—reduced resolution samples, data thresholding, data binning.A survey of ADC architectures reveals that both algorithmic and successive approximationADCs are well suited to meet the above listed design specifications. These architectures canbe realized using very low power due to the minimal amount of analog hardware required.However, the successive approximation architecture offers greater flexibility to performgeneral operations on the input. Shown in Fig. 7, the successive approximation architectureuses only one comparator, along with simple digital logic and a switching network toimplement the search algorithm. Assuming a binary search, reduced resolution samples canbe obtained by simply ending the search algorithm early. Thus, an N-bit successiveapproximation ADC can produce outputs ranging from 1 to bits of resolution with no circuitmodifications, using less energy for less resolution. While algorithmic ADCs also providethis feature, the successive approximation architecture offers an additional layer of flexibilitythrough direct modification of the successive approximation register (SAR) itself. In theSmart Dust system, the SAR is implemented by a custom microprocessor, and can bereconfigured easily. For example, the microprocessor (which now acts as the SAR) couldchange the search to simply threshold the input, bin the input into an arbitrary number ofbins, or start the search at the value of the last output code. By implementing these SARmodes with dedicated hardware in the microprocessor, the energy overhead is minimized.This arbitrary control is programmable by the user at the application level, making thesuccessive approximation ADC extremely flexible and most suitable for WSN .5. CONCLUSION Designing hardware for WSN requires a holistic approach looking at all areas of thedesign space. Researchers all over the world are contributing to improve the life time ofmotes employed in WSN. In this paper a comparison of all ADC architectures was done andSAR ADC has been found to be best suited architecture for WSN. The specificationsincluding resolution, sampling rate and others of the same has been suggested for designimplementation.REFERENCES Ben W. Cook, Steven Lanzisera and Kristofer S. J. Pister, “SoC Issues for RF SmartDust,” Proceedings of the IEEE, Vol 94, No. 6, June 2006. Shad Roundy, Eli S. Leland, Jessy Baker, Eric Carleton, Elizabeth Reilly, Elaine Lai,Brian Otis, Jan M. Rabaey, V. Sundararajan and Paul K. Wright, "Improving Power Outputfor Vibration-Based Energy Scavengers," IEEE Pervasive Computing, vol. 4, no. 1,pp. 28-36, Jan.-March 2005. Shad Roundy, Paul K. Wright and Jan Rabaey. "A Study of Low Level Vibrations asa Power Source for Wireless Sensor Nodes".Computer Communications, vol. 26, no. 11,2003, pp.1131–1144. 274
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