A new approach for design of cmos based cascode current mirror for asp applications


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A new approach for design of cmos based cascode current mirror for asp applications

  1. 1. International JournalElectronics and Communication Engineering & Technology (IJECET), ISSNInternational Journal of of Electronics and Communication IJECETEngineering & Technology (IJECET) Volume 2, Issue 2, May-July (2011), © IAEME0976 – 6464(Print), ISSN 0976 – 6472(Online)ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online)Volume 2, Issue 2, May – July (2011), pp. 01-07 ©IAEME© IAEME, http://www.iaeme.com/ijecet.html A NEW APPROACH FOR DESIGN OF CMOS BASED CASCODE CURRENT MIRROR FOR ASP APPLICATIONS Rajinder Tiwari1, R. K. Singh1, Ganga Ram Mishra2 1 Department of Electronics & Communication Engineering, Kumaon Engineering College, Dawarahat (Almora), Uttarakhand 2 Department of Electronics & Communication Engineering, Amity School of Engineering & Technology, Amity University Uttar Pradesh, Lucknow trajan@rediffmail.com rksinghkec12@rediffmail.com grmishra@rediffmail.comABSTRACTThe current mirror is the core structure for analog, digital and mixed signal circuitsand thus, the performance of the analog devices mostly depends on it’s characteristicsi.e. for low voltage analog CMOS circuits, a low voltage current mirror circuit isrequired. The topology of the circuit is an upgraded structure of the constant currentsource that provides a highly precise output operating over a wide range of powersupply. This circuit basically operates on the principle that if the gate-source voltageof the two identical MOS transistors is equal, then the channel currents should beequal. The current mirror circuit plays a dominant role in the design procedure of theactive elements and devices like operational amplifiers, current conveyors, currentfeedback amplifiers and differential amplifier. In the present work, we propose aninnovative cascode current mirror circuit that can be used in the design of variousactive devices for better and enhanced performance. This circuit has been simulatedusing pSPICE software simulator with level 3 parameters for 0.13 micron CMOStechnology.KEYWORDSCurrent Mirrors, CMOS Integrated Circuits, Analog CMOS Circuits, Analog Devices,MOS Transistor, Novel CM, Channel Current).1. INTRODUCTIONA current mirror is a circuit that is designed to provide a mirror image of thecurrent flowing through one active device simply by controlling the current in anotheractive device, keeping the resultant output current as constant regardless of changes inthe load. Due to this property, it is considered as the main building blocks of analogand mixed-signal integrated circuits. The current mirror can be configured as a simplecurrent mirror circuit and a cascode current mirror circuit. The cascode current mirrorcircuit is more commonly used in the various integrated circuits since this provides abetter performance in terms of the operating voltage, output swing, etc. It is normallydesired that the input voltage drop should be minimum at the input terminals of thecircuit particularly in case of current sensing circuits [1]. The dynamic biasingtechniques are used so as to keep the cascoded active devices always operate in thesaturation region so that the high precision and high output impedance can bemaintained over a large operating range. It means that in the process of biasing of the 1
  2. 2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 2, Issue 2, May-July (2011), © IAEMEcircuit and active devices, the performance of current mirror must be focused on theaccuracy and output impedance of the circuit performance [2]. In case of high speedapplications, the settling time of current mirror circuit plays an important role in orderto enhance the overall efficiency of the application in addition to the accuracy and theoutput impedance. It means that in case of the analog circuits design, the majority ofthe research works is mainly focused on the accuracy, output impedance and thesettling time. Thus, based on this, one can have the cascode current mirror [3] as thetraditional current mirror that is used to increase the output impedance of the circuit,the regular-gate cascode (RGC) current mirror [4] uses active-feedback circuit so as toincrease the output impedance and the improved active-feedback cascode currentmirror (IAFCCM) [5] that also enhances the output impedance, accuracy. Thelinearity of the CMOS current mirror circuit has got the fundamental limitation in theoperation of the current mode signal processing applications due to the matchingproperties of the transistors in the mirror i.e. mismatch in geometric sizes, in thetransconductance parameter of the transistors and the operating conditions of thecurrent mirror transistors particularly, the differences in the drain-source voltages ofthe input transistor and output transistor. This mismatch can be removed with propercircuit techniques of cascading that ensures the identical operating conditions for thetransistors [6].2. BASIC CURRENT MIRROR CONFIGURATIONSThe basic need of a current mirror circuit is to provide a constant voltage at the inputof an active device so as to avoid the errors introduced in the signal due to thefluctuation of the input signal, thereby, lowering the mirror input impedance which inturn minimizes the loading effect on the previous stage of the circuit. If the loadimpedance of the device is not sufficiently low, the device will suffer large drain-to-source voltage variations, which through the channel length modulation effect willcause a systematic mismatch error between the input and output currents of themirror [7]. This sort of problem can be avoided by using the cascode configuration ofthe current mirror circuit. The idea behind cascode structure is to convert the inputvoltage to a current and apply the resultant signal to the common source stage [6-10].The overall effect on the performance of the cascode circuit with one device operatingin the sub threshold and the other device operating in the active region could result ina very high gain stage with low power dissipation [13, 14]. The basic advantage offolded structure is that it provides the choice of the voltage levels because it does not“stack” the cascoded active device on top of the input device but with a little higherpower consumption [16]. Fig. 1 Basic cascode configurations of current mirror: Active, Cascode, Regulated cascode output, Active regulated cascode, basic circuit and basic cascode 2
  3. 3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 2, Issue 2, May-July (2011), © IAEMEThe figure 1 shows the various configurations of the current mirror circuit which isquite frequently used in the analog signal processing (ASP) applications. The conceptof the active cascode current mirror has been used simply to maintain a constantvoltage at the input of the circuit so as to avoid the current subtraction error [15]. Thistechnique results in making the voltage (VGS) of the input transistor of the currentmirror independent of the voltage (VDS) that is biased to remain constant which inturn reduces the input impedance and minimize the loading effect of the circuit. Thesystematic mismatch introduced between the input and output currents of the circuitcan be avoided with the use of the cascode current mirror configuration shown in fig1(b) but with a smaller output voltage swing which in turn requires a high inputvoltage drop for better accuracy [16 - 18]. The regulated-cascode current mirrorconfiguration as shown in fig l(c) is used to keep the voltage (VDS) of the transistor ofthe circuit as constant thereby, enhances the output impedance of the circuit with aprecise voltage swing at the input of the circuit. The configuration shown in fig 1(c) isbasically a combination of the two different configurations with the desired featuresi.e. low input impedance and very high output impedance [15-16]. The operationalanalysis of the current mirror circuit is basically required to ensure that equal drainvoltages are provided for the input and output transistors for a better performance ofthe circuit i.e. the circuit is highly stable with low input and high out impedance andhigh output voltage swing [19 - 22]. The mathematical analysis of the cascodedcurrent mirror circuit can be easily determined with the use of the followingexpressions and the formulae of the active devices of the circuit voltages and thecurrents [23]. 2iD1 vGS =VT1 + => β1(1+λ1vDS1) β2 iD2 = (vGS −V 2)2(1+λ2vDS2) T 2 β2 2iD1 iD2 = (VT1 −V 2 + T )2(1+λ2vDS2) 2 β1(1+λ1vDS1) β2 2iD1 2iD1 iD2 = ( +∆VT2 −2∆VT )(1+λ2vDS2) 2 β1(1+λ1vDS1) β1(1+λ1 +vDS1) ∆β iD2 (1+ )iD1 −∆VT 2βiD1 βThe output current of the circuit can be determined with the below given formula i.e.[24] 2 I out = 1 2 µ n C oxW / L N R 2 S (1 − ) KWhere K is the ratio of the size the two active devices used to provide the cascodedpath to the circuit. In addition to these, there are certain more parameters that affectthe performance of the current mirror circuit i.e. by putting λVDS1= 0, one can solvethe equations as W ( )2 IOut = I Re f L (1 + λV ) DS 2 W ( )1 L 1 rout = rds 2 = λ I Out W 2 I Out ( µCox)2 ( L )2 (VGS − VTh 2 ) (1 + λVDS 2 ) = I Re f W (µ Cox)1 ( )1 (VGS − VTh1 )2 (1 + λVDS1 ) LThus, with this discussion one can easily put forward that the parameters affecting theperformance of the circuit are channel length modulation, offset between the thresholdvoltages, imperfect geometrical matching of the active devices, technological 3
  4. 4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 2, Issue 2, May-July (2011), © IAEMEparameters mismatch and stray resistances. It means that the scope of the study of thecascoded current mirror is based on the performance of these parameters which inturn determine the output efficiency of the circuit in various ASP applications [25 -30].3. PROPOSED CMOS CASCODE CURRENT MIRROR CIRCUITThe proposed CMOS based CCM circuit is shown in the below fig (3). The basicconcept of the cascode structure is to convert the input voltage to a current, and thenfed this current to a common source with one device operating in sub threshold andthe other device operating in active region. This approach in turn offers a very highgain in addition to low dissipation. It basically consists of the transistors M1 to M12,with the transistors M5 and M6 provides the cascode structure desired for this circuit.The transistors are biased in such a way that it has got less effect on the output swingof the circuit with an enhancement in the output impedance operating in the sub voltregion [31 - 35]. The proposed circuit is simulated for 0.13 µm technology with level3 parameters. The input voltage (V1) and the biasing current (I3) are assumed in therange of 5 volts and 1nA so that it can assured a low input operating voltage in therange of fraction of volt. As shown in the fig (3), this proposed CCM circuit improvesthe output impedance, stability and accuracy without any biasing and externalcompensation of the transistors that in turns reduces the power dissipation of thecircuit. The resultant output impedance of the CCM circuit can be estimated with theuse of following equations i.e. with the use of the transconductance and the channelconductance of the active devices. 1 V 1 = io u t g d n 4 io u t = g m n 3 v g s , n 3 + g d n 3 v d s , n 3 g m n 7 io u t = g m n 3 ( − 1 ) v 1 + g d n 3 ( v o − v 1 ) g d n 7 g m n 3 g d n 3 g m n 3 g m n 7 io u t (1 + + + ) = g d n 3 v o g m n 4 g d n 4 g d n 4 g d n 7 g m n 3 g d n 3 g m n 3 g m n 7 (1 + + + ) v o g m n 4 g d n 4 g d n 4 g d n 7 = io u t g d n 3 v o g m n 3 g m n 7 ≅ io u t g d n 3 g d n 7 g d n 4 g m n 3 g m n 7 1 R o u t = g d n 3 g d n 7 g d n 4 Fig. 2 Proposed Cascode Current Mirror 4
  5. 5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 2, Issue 2, May-July (2011), © IAEME4. SIMULATION RESULTS & CONCLUSIONThe simulation results of the proposed CCM circuit are shown in the fig (3) and fig(4). The D.C. performance of the circuit is simulated with the level 3 modeledparameters and the desired behaviour of the current mirror has been depicted i.e. theinput has been copied at the output with minimum delay in the range of µsec. Theinput operating voltage is applied to the transistor M7 and the output has beenobtained across the gate terminal of the transistor M11. Based on the same modeledparameters of the transistors, the transient analysis i.e. the performance of theproposed circuit has been studied with respect to the time in the presence of theamount of noise contributed, and the simulated result of the same is shown in fig (4).Thus, based on the results obtained for this proposed CCM circuit, it has beendeduced that this circuit provides a better accuracy with high output swing and lowpower dissipation. This proposed circuit requires fraction of volt signal to operatesatisfactorily. The transient analysis of the proposed circuit in fig (4) shows that itdepicts the exact behaviour of the current mirror or source i.e. provides the mirrorimage of the input with minimum possible delay and distortion introduced due thepresence of noise. The performance of the proposed CMOS based CCM circuit can besupported to the best with the help of the fig (5) that provides the input and outputsignal behaviour with minimum distortion.Fig. 3 D.C. Analysis Fig. 4 Transient Analysis Fig. 5 Performance AnalysisACKNOWLEDGEMENTSThe authors are thankful to Prof. D. S. Chauhan (Vice Chancellor, UTU) forproviding the environment for this work and Mr. Aseem Chauhan (AdditionalPresident, RBEF), Major General K. K. Ohri, AVSM, Retd. (Director General,AUUP, Lucknow campus) and Prof. S. T. H. Abidi (Director, ASET), Brig. Umesh K.Chopra, Retd. (Dy. Director, ASET) for their kind cooperation, motivation, kind andmost valuable suggestions.REFERENCES[1]. M. J. Catlahan, Jr., “Charts speed the designing of constant current sources,” Electronics, pp. 92-95, Aug. 17, 1970.[2]. P. E. Allen, “Graphical analysis of matched transistor current sinks/sources,” IEEE J. Solid-State Circuits (Corresp.), vol. SC-9, pp. 31-35, Feb. 1974.[3]. E. A. Vittoz, “Dynamic analog techniques,” in VLSl Circuits for Telecommunications, Y. P. Tsividis and P. Antognetti, Eds. Englewood Cliffs, NJ: Prentice Hall, 1985. 5
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  7. 7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 2, Issue 2, May-July (2011), © IAEME Requirements,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. (USA), vol. 51, no. 3, pp. 124–9, 2004.[22]. E. Sackinger and W. Guggenbuhl, “A High-Swing, High-Impedance MOS Cascode Circuit,” Solid-State Circuits, IEEE Journal of, vol. 25, no. 1, pp. 289–298, Feb 1990.[23]. Garimella, L. Garimella, J. Ramirez-Angulo, A. Lopez-Martin, and R. Carvajal, “Low-Voltage High Performance Compact All Cascode CMOS Current Mirror,” Electronics Letters, vol. 41, no. 25, pp. 1359– 1360, 2005.[24]. Foty and E.J.Nowak: “MOSFET technology for low-voltagellow-power applications,” IEEE Micro, 14, 3,[25]. T. Hanyu, S. Kazama and M. Kameyama, “Design and implementation of a low-power multiple-valued current- mode integrated circuit with current- source control,” lElCE Trans. Electron., Vol. E80-C, No.7, pp.941-947, July 1997.[26]. T. Hanyu, T. Ike and M. Kameyama: “Low-power dual-rail multiple-valued current-mode logic circuit using multiple input-signal levels,” Proc. 30th IEEE Int. Symposium on Multiple-Valued Logic, 110.30, pp.382-387, Portland, Oregon, May 2000.[27]. Toumazou, F. Lidgey, D. Haigh (Eds.), Analogue IC design: the current-mode approach, Peter Peregrinus, 1990.[28]. S. Kawahito, Y. Tadokoro “CMOS Class-AB Current Mirrors for Precision Current-Mode Analog-Signal- Processing,” IEEE Trans. on Circuits and Systems, part I1 Vo1.43, No.12, pp.843-845, Dec. 1996.[29]. G. Palmisano, G. Palumbo, S. Pennisi, “High Linearity CMOS Current Output Stage,” Electronics Letters, Vol. 3 I, No. 10, pp. 789-790, May 1994.[30]. G. Palmisano, G. Palumbo, S. Pennisi, “Class AB CMOS Current Output Stages with Reduced Harmonic Distortion,” IEEE Trans. on Circuits and systems - part I1 vol. 45, no.2, pp. 243-250, Feb. 1998.[31]. G. Palumbo, S. Pennisi, “A Class AB CMOS Current Mirror with Low- Voltage Capability,” Electronics Letters ~01.35n,. 16, pp.1329-1330, Aug. 1999.[32]. Silckinger and W. Guggenbuhl, “A high-swing, high-impedance MOS circuit,” IEEE I. Solid-State Circ., vol. 25, pp. 289-298, Feb. 1990.[33]. Shouli Yan and Edgar Sanchez-Sinencio, “Low Voltage Analog Circuit Design Techniques: A Tutorial,” IEICE Transactions on Analog Integrated Circuits and Systems, vol. E00-A, no. 2, February, 2000.[34]. S.S. Rajput and S.S. Jamuar, “Low Voltage Analog Circuit Design Techniques,” IEEE Circuits and Systems Magazine, vol. 2, no. 1, pp. 24-42, First Quarter, 2002. 7