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  • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 65-71 © IAEME 65 A NEW CIRCUIT MODEL OF LOW VOLTAGE HIGH CURRENT GAIN CMOS COMPOUND PAIR AMPLIFIER Raj Kumar Tiwari, Gaya Prasad Department of Physics & Electronics Dr. R.M.L. Avadh University, Faizabad (U.P.), India ABSTRACT In the Present paper we have studied about a new circuit CMOS Compound pair Amplifier. Proposed new circuit model has been analysed and it is found that proposed circuit has very high current gain and good temperature stability for low voltage applications. CMOS Compound pair can be use as an audio as well as radio frequency tuned amplifier. It is investigated that voltage gain increases from 206.379 to 1740.50 with suitable load values. Gain variations with load resistance from 1K to 100K have been studied in present paper. Variation of input and output impedances have been also studied and it found that CMOS compound pair (Proposed Model) has high input impedance and low output impedance as compare to transistor Sziklai Pair. Key Words: Transistor Sziklai Pair, CMOS Compound Pair, Current Gain, Input and Output, Impedance, Temperature Stability. INTRODUCTION In modern time high bandwidth and gain is a challenging problem of small signal amplification in electronics. Literature surve shows existence of various types of amplifier in which Darlington pair is randomly used for various purposes due its few unique properties. Darlington pair was invented by Bell Laboratories Engineer Sidney Darlington in 1953[1]. It is seen that Darlington pair having large value of β is suitable for small signal and low frequency but not suitable for higher frequency applications [2, 3]. For ready reference value of β is given by equation (1) β= 2121 * QQQQ ββββ ++ (1) Where, symbols have their usual meaning. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) ISSN 0976 – 6464(Print) ISSN 0976 – 6472(Online) Volume 5, Issue 4, April (2014), pp. 65-71 © IAEME: www.iaeme.com/ijecet.asp Journal Impact Factor (2014): 7.2836 (Calculated by GISI) www.jifactor.com IJECET © I A E M E
  • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 65-71 © IAEME 66 Sziklai pair was named after Hungarian born inventor, George Sziklai. If a compound pair is made with an NPN deriver and PNP output device, then the overall devices behave as NPN bipolar transistor. If a compound pair is made with a PNP deriver and NPN output device, then the overall devices behave as PNP bipolar transistor. Darlington Pair, Sziklai pair having super β value given by equation (2) and CMOS compound pair (proposed new model) is shown in fig.1(a), fig.1(b) and fig.1(c) respectively. 121 * QQQ ββββ += (2) (a) (b) (C) Fig. 1: Basic Configuration of Devices; (a) and (b) reference devices and (c) proposed device Complementary metal–oxide–semiconductor (CMOS) uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Literature surve[4-18] shows that CMOS devices have high noise immunity and low static power consumption because CMOS devices do not produce as much waste heat as other forms of logic families, like transistor–transistor logic (TTL) or NMOS logic. So in present investigation we proposed a new CMOS compound pair model that works for low voltage and high speed application having high current gain with good temperature stability as compare to reference devices. EXPERIMENTAL CIRCUITS The reference transistor sziklai pair circuit shown in Fig.2 have been simulated having an a.c. input signal 1nVac, Ri=500 ohm, Ci=1µf, R1=47k, R2=5k, Re=2k, Ce=10µf, Co=10uf, Rl=10k, Rc=10k, Vd=5Vdc, and npn transistor Q1=2N2222 and Q2= 2N2904 is used as an active component to design the circuit. Proposed new CMOS circuit shown in the Fig.3 in which the active component transister Sziklai pair is replaced by CMOS compound pair and other passive components are same as taken in fig.2 for ready comperision. Base Collector PNP Base Emitter Collector Darlington Pair NPN NPN NPN Emitter PNP PNP PNP Base Collector PNP NPN Base Sziklai Pair Emitter Collector Emitter NPN PNPNPN NMOS CMOS Gate CMOS Compound Pair M1 NMOS M3 Source M4 Drain M2 PMOS PMOS
  • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 65-71 © IAEME 67 Fig. 2: Transistor Sziklai pair Circuit (Reference Circuit) Fig. 3: Proposed CMOS Compound pair Circuit RESULTS AND DISCUSSIONS Proposed amplifier circuit provides high current gain and wide bandwidth in comparison to reference circuit as shown in fig.4. Proposed new circuit model can be also used as a tuned amplifier for radio frequency application as shown in fig.5. Input Impedance for CMOS compound pair amplifier (proposed model) is found to be higher than transistor sziklai pair as shown in fig.6 fig.7 shows low output impedenceas compare to transistor Sziklai pair amplifier. Fig.8 shows good temperature stability. Present investigation for proposed model shows variation of the gain with load resistance and it is found that gain for proposed model varies from 206.374 to 1740.50 for typical load 1K to 100K respectively which is shown in table 1 for ready reference. Table2 shows variation of gain with respect to the capactancefor fixed load resistance Rl=10k. Analysis shows that for particular value of Co=10pf gain is found to be very high equal to 9606.0. Vd 5Vdc M1 MbreakP M2 MbreakP M4 MbreakN Rl 10k 2 1 R1 47k 2 1 M3 MbreakN V1 1nVac 0Vdc Rs 2k 2 1 Ri 500 21 Cs 10uf1 2 Co 10m R2 5k 2 1 Ci 1uf 1 2 Rd 10k 2 1
  • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 65-71 © IAEME 68 Fig. 4: Current gain of transistor Sziklai pair(+ symbol) and CMOS compound pair(x symbol) Fig.5: Voltage gain of transistor Sziklai pair(+ symbol) and CMOS compound pair(x symbol) Fig.6: Input Impedance of transistor Sziklai pair(+ symbol) and CMOS compound pair(x symbol)
  • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 65-71 © IAEME 69 Fig.7: Output Impedance of transistor Sziklai pair(+ symbol) and CMOS compound pair(x symbol) Fig.8: Temperature stable for - 5 to 10 range of CMOS Compound pair TABLES Table 1: Variation of gain with load resistance for capacitance 10uf for CMOS Compound Pair Value of Load Resistance Rl in kiloohm Voltage gain Av in mili 1 206.379 5 279.329 10 369.004 47 984.434 100 1740.50 Table 2: Variation of frequency response with output capacitor for fixed load resistance 10k for CMOS Compound Pair Value of Co 10 Hz 100 Hz 1Khz 10Khz 1 Mhz 1Ghz 1Thz 100Thz 10p 314.0 2934.7 9606.0 9543.0 471.3 369.04 369.04 369.04 10n 316.6 4113.5 474.8 369.04 369.04 369.04 369.04 369.04 10u 85.5 340.11 368.6 369.04 369.04 369.04 369.04 369.04 10m 84.9 339.86 368.6 369.04 369.04 369.04 369.04 369.04
  • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 65-71 © IAEME 70 CONCLUSION The proposed model can be used for various application due to its high current gain high input impedance and low output impedance and due to its good temperature stability in various analog and digital circuit for low voltage and high speed applications. REFERENCES [1] www. Wikipedia, the free encyclopedia. [2] Robert L. Boylested and Louis Nashelsky Electronic devices and circuit theory Prentice Hall is an imprint of Pearson, tenth edition p.p. 578-582 (2009). [3] Raj Kumar Tiwari and Jyotsna Mishra, “Simulation Study of High Frequency Small Signal Amplifier”, Ultra Scientist Vol.22(2), 419-424 (2010). [4] Nail H.E. Weste and Kamran Eshraghian, “Principles of CMOS VLSI Design A systems Perspective” Addison-Wesley Publishing Company. Reprint june1988, pp63-94. [5] Hassan O. Elwan and Ahmed M. Soliman, “Low-Voltage Low-Power CMOS Current Conveyors”, IEEE Transactions on Circuits and Systems—I: Fundamental Theory And Applications, Vol. 44, No. 9, September 1997 [6] Y.K. Seng, “New current conveyor for high-speed low-power current sensing”, IEE Procc. Circuits Devices Syst., Vol. 145, No. 2. April 1998, pp.85-89. [7] Christophe PrBmont, Stkphane Cattet, Richard Grisel, Nacer Abouchi, “A CMOS Multiplier/Divider based on Current Conveyors’, Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 1, pp. 69-71, 1998. [8] Raj Kumar Tiwari, Anil Kumar Shukla and Ganga Ram Mishra, “Noise Analysis Of Class AB CMOS Current Conveyor”, Journal of Ultra Scientist of physical sciences, Vol. 23, No.1, 2011, pp. 155-161. [9] Raj Kumar Tiwari and Anil Kumar Shukla, “Gain Enhancement in Folded Cascode Op-Amp with Class AB Output Buffer”, International Journal of Electronics, Electrical and Communication Engineering, Vol.3, No.2, 2011, pp. 163-167. [10] Raj Kumar Tiwari and Anil Kumar Shukla, “Operational Amplifier Design with Rail-to-Rail Supply Voltage Output Having Reduced Power Dissipation” in International Journal of VLSI design, Vol.3, No. 1, 2012, pp. 11-14. [11] Raj Kumar Tiwari and Anil Kumar Shukla, “Design of A 100mhz Highly Linear Source- Coupled CMOS Voltage Controlled Oscillator”, International Journal of Electronics Engineering, Vol. 4, No. 1, 2012, pp. 113-115. [12] R. K. Tiwari, A. K. Shukla and G. P. Tiwari, “Double Differential-Pair CMOS Transconductor Under Nano-Scale CMOS Technology” Abstracts of the 3rd National Conference on Nanomaterials & Nanotechnology held at ASET Lucknow during December 21-23, 2010, P59. [13] Anil Kumar Shukla, Ganga Ram Mishra, Raj Kumar Tiwari and N.K. Mishra, “Highly Linear Transconductor Structure For Nano-Scale CMOS Technology”, Proceedings of the 2nd National Conference on Nanomaterials & Nanotechnology held at Department of Physics, University of Lucknow, Lucknow during December 21-23, 2009, pp. 304-308. [14] Takashi Kurashina, Satomi Ogawa, and Kenzo Watanabe, “A High Performance Class AB Current Conveyor”, Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, Vol. 3, pp. 143-146, 1998. [15] A.M. Isinail and A.M. Soliman, “Low-power CMOS current conveyor”, Electronics Letters, Vol. 36, 2000, pp.7-8.
  • International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 65-71 © IAEME 71 [16] Antonio J. Lopez-Marlin Jaime Ramirez-Angulo , and Ramon G. Carvaja, “Low-Voltage Low-Power Wideband CMOS Current Conveyors Based On The Flipped Voltage Follower”, Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 1, pp. 801- 804, 2003. [17] Samir Ben Salem, Ahmed Fakhfakh, Mourad Loulou, Patrick Loumeau and Nouri Masmoudi, “A 2.5V 0.35ptm CMOS Current Conveyor and High Frequency High-Q Band- Pass Filter”, Proceedings of the IEEE International Conference on Microelectronics, pp. 328- 333, 6-8 Dec. 2004. [18] Debashis Dutta, Ritesh Ujjwal and Swapna Banerjee, “Design of Low-Voltage Low-power Continuous-Time Filter for Hearing Aid Application using CMOS Current Conveyor based Translinear loop”, Proceedings of the IEEE International conference on VLSI Design, 3-7 Jan. 2006. [19] Muhammad H. Rashid, Introduction to Pspice using Or CAD for circuits and electronics, Pearsion Education, 3rd Edition p.p. 150-153 (2004). [20] Rajinder Tiwari and R K Singh, “An Optimized High Speed Dual Mode CMOS Differential Amplifier for Analog VLSI applications”, International Journal of Electrical Engineering & Technology (IJEET), Volume 3, Issue 1, 2012, pp. 180 - 187, ISSN Print : 0976-6545, ISSN Online: 0976-6553. [21] G. Ramesh, J. Paul Richardson Gnanaraj, M. Velvizhi and G. Jesly Marsha, “Low Power CMOS Binary Counter using Conventional Flip - Flops”, International Journal of Electronics and Communication Engineering &Technology (IJECET), Volume 4, Issue 2, 2013, pp. 243 - 249, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472. [22] Rajinder Tiwari, R. K. Singh and Ganga Ram Mishra, “A New Approach for Design of CMOS Based Cascode Current Mirror for ASP Applications”, International Journal of Electronics and Communication Engineering &Technology (IJECET), Volume 2, Issue 2, 2011, pp. 1 - 7, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472. [23] P.Sreenivasulu, Krishnna Veni, Dr. K.Srinivasa Rao and Dr.A.Vinayababu, “Low Power Design Techniques of CMOS Digital Circuits”, International Journal of Electronics and Communication Engineering &Technology (IJECET), Volume 3, Issue 2, 2012, pp. 199 - 208, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.