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  1. 1. International Journal of Electronics and JOURNALEngineering & Technology (IJECET), ISSN 0976 – INTERNATIONAL Communication OF ELECTRONICS AND 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November-December (2013), © IAEME COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) ISSN 0976 – 6464(Print) ISSN 0976 – 6472(Online) Volume 4, Issue 6, November-December, 2013, pp. 21-28 © IAEME: www.iaeme.com/ijecet.asp Journal Impact Factor (2013): 5.8896 (Calculated by GISI) www.jifactor.com IJECET ©IAEME SWITCHED CAPACITOR BASED LOG – ANTILOG AMPLIFIER USING CDTA (A CURRENT MODE IMPLEMENTATION) Indu Prabha Singh1, Meeti Dehran2, Kalyan Singh3 1, 2 3 Deptt. of Electronics and Comm. Engg. SRMGPC, Lucknow-227105, India Deptt. of Physics and Electronics Engg. , Dr. RML Avadh University, India ABSTRACT The paper presents Log and Antilog Amplifier using Current Differencing Transconductance Amplifier (CDTA).The proposed circuit configuration consists of a single CDTA. Owing to its current mode operation it consumes less power. Furthermore, the instability problem found in OpAmp based log-antilog amplifiers due to the presence of an active element in the feedback loop is absent in the CDTA log-antilog amplifier. It provides the advantage of using switched capacitor instead of a resistor that is beneficial to IC implementation in terms of space consideration. The simulation results confirm the logarithmic and anti-logarithmic behavior with very low-error. Keywords: Logarithmic Function, Current Mode Circuits, CDTA, Logarithmic Amplifier, Anti-Log Amplifier and Analog Signal Processing. 1. INTRODUCTION Log and Antilog Amplifiers are non-linear circuits in which the output voltage is proportional to the logarithmic and exponential value of the input respectively [1-3]. They have numerous applications in medical equipments, electronic communication, instrumentation and control systems such as amplitude modulation, frequency multiplier, frequency divider, automatic gain control, phase lock loop, adaptive filtering, powers and roots compression and decompression, true RMS detection and process control. Logarithmic circuits need to have high input dynamic range to compress the large amplitude of the signals in the radar receivers input, high accuracy for arithmetical operation functions and low power consumption. Log-antilog amplifiers use the exponential property of a forward bias p-n junction, using either a diode or bipolar transistor, to provide the necessary log and antilog function [4]. Typically, conventional log-antilog multipliers could be realized using Operational Amplifiers, bipolar transistors and resistors for its multiplication function [5]. However, using Operational Amplifiers as 21
  2. 2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November-December (2013), © IAEME building blocks to synthesize the multiplication function will limit the high frequency operation of the multiplier. Moreover, it will also increase the cost, power consumption, and chip areas. For these reasons, it is useful to apply the translinear log-antilog multipliers/dividers avoiding Operational Amplifiers and introducing current-mode signal processing [6, 7]. However, log-antilog multiplier/divider configurations in [6, 7] are only suitable for bipolar technology. The current-mode techniques provide large benefits in practical circuits and systems, and give elegant solutions for many above discussed problems [8]. Current Differencing Transconductance Amplifier (CDTA) introduced in 2003, has been acknowledged to be a versatile current-mode active building block in designing analog circuits [9]. This device with two current inputs and two kinds of current output provides an easy implementation of current-mode log – antilog amplifier. It also exhibits the ability of electronic tuning by the help of its transconductance gain (gm). All these advantages together with its current-mode operation nature make the CDTA a promising choice for realizing the current-mode log – antilog amplifier. As a result, a variety of CDTA applications has also been considered by various researchers [10-14]. In this paper, a new current-mode log-antilog amplifier based on CDTA is proposed. The circuit employs one CDTA and two diodes for log amplifier and one switched capacitor, one diode and one CDTA for antilog amplifier. This circuit enjoys excellent temperature stability and is very suitable for implementation in CMOS technology. The theoretical results are verified by PSPICE simulations. 2. CURRENT DIFFERENCING TRANSCONDUCTANCE AMPLIFIER (CDTA) Although many types of signal processing have indeed moved to digital domain, analog circuits are fundamentally necessary in many of today’s complex, high performance systems. This is caused by the reality that naturally occurring signals are analog. Therefore analog circuits act as a bridge between the real world and digital systems. In the beginning, Operational Amplifiers were the main building blocks for analog circuit design. Unfortunately, their limited performance such as bandwidth, slew-rate etc. led the analog designer to search for other possibilities and other building blocks. As a result, new current-mode active building blocks receive considerable attention due to their larger dynamic range and wider bandwidth. The proposed circuits are based on CDTA. The CDTA is composed of translinear elements, mixed loops and complementary current mirrors. The electrical symbol of the CDTA is shown in Fig.1. The terminal relation of the CDTA can be characterized by the given matrix. Fig.1: CDTA electrical symbol 22
  3. 3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November-December (2013), © IAEME ܸ 0 ௣ ‫ۍ ې ۍ‬ ‫0 ێ ۑ ܸێ‬ ௡ ‫ۑ ێ‬ൌ‫ێ‬ ‫ܫ ێ‬௭ ‫1 ێ ۑ‬ ‫ێ ۑ ێ‬ ‫ܫ ۏ‬௫ ‫0 ۏ ے‬ 0 0 െ1 0 0 0 0 േ݃௠ 0 ‫ې‬ 0‫ۑ‬ ‫ۑ‬ 0‫ۑ‬ ‫ۑ‬ 0‫ے‬ ‫ܫ‬௣ ‫ې ۍ‬ ‫ܫ ێ‬௡ ‫ۑ‬ ‫ۑ ێ‬ ௭ ‫ۑ ܸێ‬ ‫ے0 ۏ‬ ሺ1ሻ Where p and n are input terminals, z and ±x are output terminals, gm is the transconductance gain, And Vz is the voltage produced due to external impedance connected at the terminal z. According to above equation, the current flowing out of the terminal z (iz) is a difference (ipin) between the currents through the terminals p and n. The voltage drop at the terminal z is transferred to a current at the terminal x (ix) by a transconductance gain (gm), which is electronically controllable by an external bias current (IB). Hence the product of transconductance (gm) and the voltage at the z terminal gives the magnitudes of output currents. These currents, which are copied to a general number of output current terminals x, are equal in magnitude but may flow in opposite directions. Figure 2 shows a CMOS realization of the CDTA element [15]. The transistors M1 to M16 form the input difference current controlled current source stage and M21 to M28 form the dualoutput transconductor stage. Quiescent current of the circuit flowing over MOSFET MB is chosen as 40µA. Aspect ratios of the transistors in the Figure 2 are given in Table 2. Table 2. Aspect ratios of the transistors M1= 70µm/0.7µm M15= 35µm/0.7µm M2= 70µm/0.7µm M16= 35µm/0.7µm M3= 70µm/0.7µm M17= 35µm/0.7µm M4= 28µm/0.7µm M21= 28µm/0.7µm M5= 28µm/0.7µm M22= 16µm/0.7µm M6= 28µm/0.7µm M23= 28µm/0.7µm M7= 42µm/0.7µm M24= 16µm/0.7µm M8= 10.5µm/0.7µm M25= 56µm/0.7µm M9= 10.5µm/0.7µm M26= 59µm/0.7µm M10= 42µm/0.7µm M27= 56µm/0.7µm M11=10.5µm/0.7µm M28= 56µm/0.7µm M12= 98µm/0.7µm MB= 7µm/0.7µm M13= 10.5µm/0.7µm M30= 50µm/0.7µm M14= 10.5µm/0.7µm M31= 50µm/0.7µm 3. PROPOSED CIRCUIT The proposed current-mode log amplifier employing CDTA and two diodes is shown in Fig.3. In this circuit, the input applied is a current source connected directly to the p-terminal. The I-V relationship of the diode is approximated by: ‫ ܫ‬ൌ ‫ܫ‬ୱ ݁‫ ݌ݔ‬ቀܸൗܸ ቁ (2) ் Where Is is the reverse saturation current and VT is the thermal voltage. 23
  4. 4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November-December (2013), © IAEME Vdd M12 M08 M06 M11 M04 M09 M26 M27 M05 M07 M21 M10 P M03 M01 n x+ x– M02 M17 M23 M15 M16 z M22 M24 IB VSS M14 M13 M28 M25 MB VSS Fig.2. CDTA CMOS implementation from [15] Routine analysis of the circuit shown in Fig. 3 leads to the following expression of Vz (with In set to zero): ‫ܫ‬ ܸ ൌ ்ܸ ݈݊ ൭ ௉ൗ‫ ܫ‬൱ ௭ (3) ௌ And hence, ‫ܫ‬ ‫ܫ‬଴ ൌ ݃௠ ்ܸ ݈݊ ൭ ௉ൗ‫ ܫ‬൱ (4) ௌ Fig. 3: Proposed current-mode Log-Amplifier 24
  5. 5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November-December (2013), © IAEME If Input current Ip is DC in nature, only diode D1 is required. In case of AC input, both diodes D1 and D2 are needed for the logarithmic amplification. If the input is a voltage instead of current, it can be applied to the p-terminal of CDTA through a resistor. Consequently, (3) and (4) will contain Vi/R in place of Ip. If a voltage output is required then it may be taken at z-terminal. However, as z-terminal is a high impedance node, a buffer will be required to avoid loading effect. Fig. 4 shows the circuit of Antilog amplifier. For antilog amplifier, input voltage is applied to the p-terminal through a diode and a switched capacitor is required at Z terminal. The switched capacitor (SC) functions as a resistor and reduces the required space for the fabrication. The SC is compatible with CMOS technology. The value of the capacitor C1 used in switched capacitor is calculated using the formula given as: ‫ܥ‬ଵ ൌ 1ൗܴ ݂ ሺ5ሻ Where, R is the equivalent resistance value of the switched capacitor and f is the frequency of clock signal (Φ1) and (Φ2), applied at two MOSFETs (M30, M31) of switched capacitor.A routine analysis shows that output current is given by ܸ ‫ܫ‬଴ ൌ ݃௠ ܴ ‫ܫ‬௦ ݁‫ ݌ݔ‬൭ ௜ൗܸ ൱ ் ሺ6ሻ Ip Vi I in Io X+ P CDTA N Z IZ ɸ ɸ ɸ ɸ 1 C1 ɸ 2 Fig. 4: Proposed switched capacitor Antilog-Amplifier 4. SIMULATION RESULTS The performance of the proposed log-antilog amplifier is verified using the simulation in PSpice. The CDTA model from [15] is used; employing the n-well CMOS process TSMC 0.35mm. The transconductance was set to 888mS via a bias current of 40mA. Fig. 5 shows the simulated DC transfer characteristics of the log amplifier circuit. Here Ip is varied from 0 to 100µA and In is kept at 0. Response of log amplifier for AC signal applied at P terminal is shown in Fig.6 25
  6. 6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November-December (2013), © IAEME 240uA 200uA I(X+) 160uA 120uA 80uA 40uA 0 A0 A 10uA 20uA 30uA 40uA 50uA 60uA 70uA 80uA 90uA 100uA IP Fig. 5: Simulated DC transfer characteristics of the Log Amplifier for In = 0 200uA I(X+) IP 100uA 0A -100uA -200uA 5u 0 10u 15u 20u 25u s 30u 35u 40u 45u 50u Time Fig. 6: Simulated logarithmic output for AC signal input 40uA I(X+) 0A -40uA -80uA -120uA -160uA -200uA 0 10uA 20uA 30uA 40uA 50uA 60uA 70uA 80uA IN 90uA 100uA Fig. 7: Simulated DC transfer characteristics of the Log Amplifier for Ip = 0 26
  7. 7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November-December (2013), © IAEME 200uA I(X+) IN 100uA 0A -100uA -200uA 0 5us 10u 15u 20u 25u 30us 35u 40u 45u 50u Time Fig. 8: Simulated logarithmic output for AC signal at n input terminal The amplified output current corresponding to the DC and AC input current signal at n terminal is shown in Fig. 7 and Fig. 8 respectively. The transfer characteristic of the antilog amplifier is shown in Fig. 9. In this figure, the current Ip is also swept from 0 to 200µA. Default value of temperature is assumed at 260C (room temperature). The results are obtained with Vdd = – Vss = 1.8V, and bias current IB = 40 µA. 150µA I0 100µA 50µA 0µA 20µA 60µA 140µA 100µA 180µA 200µA IP Fig.9: Simulated antilog output 5. CONCLUSION A new log-antilog current amplifier has been presented. The proposed circuit employs single CDTA, diodes and a switched capacitor, which is very much suitable for implementation in CMOS technology. The switched capacitor (SC) reduces the required space in IC implementation. This circuit will be a useful sub circuit for analog signal processing system. As there is no feedback in both circuits, it is free from well recognized problem of instability found in op-amp based logarithmic amplifiers. 27
  8. 8. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November-December (2013), © IAEME 6. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] Chris D. Holdenried, James W. Haslett, John G. Mc Rory, R. Douglas Beards, A. J. Bergsma J. ”A DC–4-GHz True Logarithmic Amplifier: Theory and Implementation,” IEEE Journal of Solid-State Circuits, Vol.37, No. 10, October 2002. Sanchi Harnsoongnoen, Chiranut Sangiamsak, Poonsak Intarakul, Rardchawadee Silapunt, “Logarithmic and Antilogarithmic Circuit with Gate-to-Substrate Biasing Technique”, ITC-CSCC, 2008. R. F. Wolffenbuttel, “Digitally programmable accurate current sources for logarithmic control of the amplification or attenuation in a gain cell”, IEEE J. of solid-st. circ, V23, pp.767-773, 1988. P. E. Allen and D. R. Holberg, CMOS Analog circuit design, Holt Rinehart, Winston, Inc., 1987. A. J. Peyton and V. Walsh, Analog electronics with op amps: a source book of practical circuits, Cambridge University Press, New York, 1993. C. Toumazou, F. J. Lidgey, D. G. Haigh, Analog IC design: the current-mode approach, Stevenage, U.K.: Peregrinus, 1990. N. Tadic, “A β-error elimination in the translinear reduction of the log–antilog multiplier/divider,” Proc., IEEE Instrument and Measurement Technology Conference, Venice, Italy, May 24-26, 1999, pp 525-530. G. W. Roberts and A. S. Sedra, “All-current-mode frequency selective circuits,” Electronics Letters, vol. 25, pp. 759-761, 1989. D. Biolek, "CDTA-Building block for current-mode analog signal processing", Proceeding of ECCTD 2003, Poland, 2003, pp.397-400. D. Biolek, V. Biolkova, "Universal biquad using CDTA elements for cascade filter design", Proc., CSCC 2003, Athens Greece, 2003,5706 pp. 8-12. A. T. Bekri, F. Anday, "Nth-order low-pass filter employing current differencing transconductance amplifiers", Proc., European Conference on Circuit Theory and Design, vol. 2,pp.193-196, 2005. D. Biolek, V. Biolkova, "CDTA-C current-mode universal 2nd_order filter", Proc.,5th WSEAS International Conference on Applied Informatics and Communications, Malta, September 15-17, pp.411-414, 2005. W. Tanjaroen, T. Dumawipata, S. Unhavanich, W. Tangsrirat, W. Surakampontorn, "Design of current differencing transconductance amplifier and its application to current-mode KHN biquad filter", Proc., ECTI-CON 2006, Ubon-ratchathani, Thailand, May 10-13, pp.497-500, 2006 A. Uygur, H. Kuntman, “Design of a Current Differencing Transconductance Amplifier (CDTA) and Its Application on Active Filters” SIU'2005: IEEE 13th Signal Processing and Communication Applications Conference, 16-18 May 2005, Kayseri. D. Biolek, E. Hanciouglu, A.U. Keskin, “High-performance current differencing transconductance amplifier and its application in precision current-mode rectification”, Int. J. Electron. Commun, 62, 2008, pp-92-96. Prashant S. Patel and Mehul L. Patel, “Implementation of CMOS 3.8 Ghz Narrow Band Pass (High Q) Switched Capacitor Filter in 180 Nm Technology”, International Journal of Electronics and Communication Engineering & Technology (IJECET), Volume 4, Issue 1, 2013, pp. 256 - 263, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472. Mohammed Arifuddin Sohel, Dr. K. Chennakeshava Reddy and Dr. Syed Abdul Sattar, “Linearity Enhancement of Operational Transconductance Amplifier using Source Degeneration”, International Journal of Advanced Research in Engineering & Technology (IJARET), Volume 4, Issue 3, 2013, pp. 257 - 263, ISSN Print: 0976-6480, ISSN Online: 0976-6499. 28