International Journal of Wisdom Based Computing, Vol. 1 (2), August 2011 28
Design of Operational Transconductance
Amplifi...
International Journal of Wisdom Based Computing, Vol. 1 (2), August 2011 29
possible values of the input common-mode volta...
International Journal of Wisdom Based Computing, Vol. 1 (2), August 2011 30
Tabel 1 shows that the aspect ratios of all tr...
International Journal of Wisdom Based Computing, Vol. 1 (2), August 2011 31
Figure. 4 Vdd=3.3V OTA gain and phase plot
TAB...
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OTA Test Case

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OTA Circuit Optimization

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  1. 1. International Journal of Wisdom Based Computing, Vol. 1 (2), August 2011 28 Design of Operational Transconductance Amplifier Using 0.35µm Technology Mr. Bhavesh H. Soni(1) , Ms. Rasika N. Dhavse (2) Department Of Electronics Engineering Sardar Vallabhbhai National Institute of Technology, Surat, India-395007 Email : bhaveshsoni.ec@gmail.com(1) , rsk@eced.svnit.ac.in(2) Abstract- Operational transconductance amplifier (OTA) is one of the most significant building-blocks in integrated continuous-time filters. Here we design a two stage amplifier in TSMC 0.35µm technology with all the transistor in the saturation region. It has a output swing of VDD-2VDS, sat. The simulated output frequency response is shown for a supply voltage of 3.3V and 1.8V using IC studio in Mentor Graphics. DC gain is 48dB and 46dB, power consumption is 3.4mW and 23µW and slew rate is 26 V/µs and 2 V/µs for 3.3V and 1.8V respectively. Keywords- OTA, CMOS analog integrated circuits, Operational amplifier I. INTRODUCTION The OTA is an amplifier whose differential input voltage produces an output current. Thus, it is a voltage controlled current source (VCCS). There is usually an additional input for a current to control the amplifier's transconductance. The OTA is similar to a standard operational amplifier in that it has a high impendence differential input stage and that it may be used with negative feedback. Portable electronics with low- voltage operation finds big markets [3]. However, the threshold voltage is not reduced proportionally with the supply voltage. Thus, the threshold voltage is becoming a restraint for many analog circuits. Some special techniques are used to overcome the size of the threshold voltage, e.g. floating gate transistors [1], bulk-driven transistors [2], continuous-time filters [7] and low threshold transistors. They suffer from several drawbacks or need special fabrication steps, which increases the cost. It is preferred to implement low- voltage circuits using a standard CMOS technology. OTA is the most important building block in analog circuits; the amplifier faces another difficulty in the low-voltage design, providing high gain and high output swing with low-power consumption. The usual way to boost the gain, cascading of transistors, is not possible in low-voltage design due to its output swing limitation. Alternatively, cascading transistor, i.e. the multi-stage amplifier, is adopted[3]. However, a cascade structure, which boosts gain with more than one amplifying stage, normally increases the power consumption and needs frequency compensation [3]. Besides, there are also other methods to enhance the OTA gain, e.g. positive feedback [4] and a use of replica amplifier [5]. Among all these methods, a rather high amount of power and chip area is used for the gain enhancement circuitry. In this work the OTA is design, its simulation results indicates that a slew rate of 26 V/µs and GBW of 10MHz is sufficient to design modulator circuit design in Sigma-Delta Modulator[9]. II. OTA AT SYSTEM LEVEL AND RELATED DESIGN ISSUES As shown in fig. 1 that is basic circuit diagram of two stage OTA. In which M1and M2 use for differential input pair, M3 and M4 forms current mirror. Figure 1. Basic Two Stage OTA[10] III. DESIGN ISSUES The setup for deriving the bias conditions is as follows. The input terminals are the same DC potential, the common-mode input voltage Vcm. We assume that the common-mode input voltage is allowed to range between a minimum value Vcm;min and maximum value Vcm:max, which are given. Similarly, we assume that the output voltage is allowed to swing between a minimum value Vout;min and a maximum value Vout;max(which takes into account large signal swings in the output).The bias conditions are that each transistor M1….M8 should remain in saturation for all
  2. 2. International Journal of Wisdom Based Computing, Vol. 1 (2), August 2011 29 possible values of the input common-mode voltage and the output voltage. • Tansistor M1: The lowest common-mode input voltage, Vcm; min imposes the toughest constraint on transistor M1 remaining in saturation • Transistor M2: The systematic offset condition makes the drain voltage of M1 equal to the drain voltage of M2. Therefore, the condition for M2 being saturated is the same as the condition for M1 being saturated. Note that the minimum allowable value Vcm; min is determined by M1 and M2 entering the linear region. • Transistor M3: Since Vgd3=0 transistor M3 is always in saturation and no additional constraint is necessary. • Transistor M4: The systematic offset condition also implies that the drain voltage of M4 is equal to the drain voltage of M3. Thus M4 will be saturated as well. • Transistor M5: The highest common-mode input voltage, Vcm;max, imposes the tightest constraint on transistor M5 being in saturation the maximum allowable value of Vcm;min is determined by M5 entering the linear region. • Transistor M6: The most stringent condition occurs when the output voltage is at its minimum value Vout;min • Transistor M7: For M7, the most stringent condition occurs when the output voltage is at its maximum value Vout;max • Transistor M8: Since Vgd8=0, transistor M8 is always in saturation; no additional constraint is necessary.M9, M10, M11, M12 forms cascade current biasing circuit. In summary, the requirement that all transistors remain in saturation for all values of common-mode input voltage between Vcm;min and Vcm;max, and all values of output voltage between Vout;min and Vout;max We start by considering some very basic constraints involving the device dimensions, e.g., symmetry, minimum or maximum dimensions, and area limits. A. Symmetry and matching W1=W2, L1=L2, W3=W4, L3=L4 ( 1 ) The biasing transistor M5 and M8 must match, i.e. have same length: L5=L8 ( 2 ) The five equality constraints in (1) and (2) have monomial expressions on the left and right hand sides. B. Systematic input offset voltage To reduce offset voltage, the drain voltages of M3 and M4 must be equal, ensuring that the current from M5 is split equally between transistor M1 and M2[8]. This happens the current densities of M3, M4 and M6 are equal. These two conditions are equality constraints between monomials, and are therefore readily handled by geometric programming. C. Bias conditions, signal swing, and power constraints In this section we consider constraints involving bias conditions, including the effects of common-mode input voltage and output signal swing. We also consider the quiescent power of the op-amp (which is determined by the bias conditions). In deriving these constraints, we assume that the symmetry and matching conditions (1) and (2) hold. To derive the equations we use a standard long channel, square-law model for the MOS transistors, which is described in detail [8]. In order to simplify the equations, it is convenient to define the bias currents I1, I5 and I7 through transistors M1, M5 and M7 respectively. Transistors M5 and M7 form a current mirror with transistor M8. Their currents are given by [10] 5 8 5 5 8 W L I Ibias L W ⎛ ⎞ = ⎜ ⎟ ⎝ ⎠ (3) 7 8 7 7 8 W L I Ibias L W ⎛ ⎞ = ⎜ ⎟ ⎝ ⎠ (4) Thus I5 and I7 are monomials in the design variables. The current through transistor M5 is split equally between transistor M1 and M2.Thus we have [10] 5 5 8 1 5 82 2 I W L I Ibias L W = ⎛ ⎞ = ⎜ ⎟ ⎝ ⎠ (5) Since these bias currents are monomials, we can include lower or upper bounds on them or even equality constraints, if we wish. We will use I1, I5 and I7 in order to express other constraints, remembering that this bias current can simply be eliminated. D. Gate overdrive: It is sometimes desirable to operate the transistors with a minimum gate overdrive voltage[8]. This ensures that they operate away from the sub threshold region, and also improves matching between transistors E. Quiescent power: The quiescent power of the op-amp is given by P= (Vdd) (Ibias+I5+I7) (6)
  3. 3. International Journal of Wisdom Based Computing, Vol. 1 (2), August 2011 30 Tabel 1 shows that the aspect ratios of all transistor to operate in saturation. TABLE I . TRANSISTOR ASPECT RATIOS Transistor W/L ratio M1,M2 10/0.35 M3,M4,M5 1.4/0.35 M6 34/0.35 M7 12/0.35 M8,M9,M10,M11,M12,M13 1.4/0.35 IV. OP-AMP SIMULATIONS A practical version of the two stage op-amp is shown in the fig. 2 the gain of the op-amp is mainly depends on input differential stage the DC gain is largely unaffected by choice of P-channel or N-channel input pair maximizes the slew rate [5]. Having a p-channel input first stage implies that the second stage has an n-channel input drive transistor of the second stage, which maximizes the transconductance of the drive transistor of the second stage which is critical when high frequency operation is important. Typically, p-channel transistors have less 1/f noise than n-channel transistors since their majority carriers (holes) have less potential to be trapped in surface state [7]. The second stage gain stage is simply a common source gain stage with the p-channel active load. Here pole-zero compension is used. Bias circuit is actively designed. The simulated output frequency response is shown in fig. 3 and 4 here 0.35µm TSMC IC studio is used for simulation. By operating all transistor in to saturation region power consumption and slew rate is reduced but GBW product remain constant. Figure 2. Two stage OTA The simulated output frequency response is shown in fig. 3 and 4 here 0.35µm TSMC IC studio is used for simulation. By operating all transistor in to saturation region power consumption and slew rate is reduced but GBW product remain constant. V. CONCLUSION Design of OTA is vital importance in integrated continuous-time filters. An 350nm OTA with gain of ~48Db for both 3.3V and 1.8V without using gain boosting technique and it consume less power for low voltage. This OTA can further be used for analog portable devices. Behavioral simulation indicates that slew rate is 25V/µs, GBW of 10MHz is sufficient to design modular circuit of Digital-Audio Sigma-Delta modulator. Figure 3 Vdd=1.8V OTA gain and phase plot
  4. 4. International Journal of Wisdom Based Computing, Vol. 1 (2), August 2011 31 Figure. 4 Vdd=3.3V OTA gain and phase plot TABLE II. SIMULATED PARAMETERS OF OP-AMP Parameters VDD=3.3V VDD=1.8V DC gain 48dB 46dB Power consumed 3.4mW 23µW Gain Margin 50dB 36dB Phase Margin 61º 63º Slew Rate(V/µs) 26 2 GBW(Hz) 10M 10M ACKNOWLEDGMENT The authors would like to thank Prof. (Mr.)Anand D.Darji Assistant Professor, Electronics Department of Sardar Vallabhbhai National Institute of Technology Surat co-incharge of SMDP-II project, facility for providing at VLSI Design Laboratory. The authors would also like to thank Dr. (Mrs.) Suprava Patnaik,Associate Professor and Head of Electronics Engineering Department, Sardar Vallabhbhai National Institute of Technology Surat and Prof. Mr. Jignesh Sarvaiya Assistant Professor & PG In-charge at Sardar Vallabhbhai National Institute of Technology, Surat for their support. REFERENCES [1] J. Ramrez-Angulo, S. C. Choi, and G. Gonzlez-AltamiranoG, “Low-voltage circuits building blocks using multiple-input floating-gate transistors”, IEEE Transactions on Circuits and Systems—Part I: Fundamental Theory and Applications, 29:971 – 974, November 1995 [2] B. J. Blalock and P. E. Allen, “A One-Volt, 120-µW, 1-MHz OTA for Standard CMOS Technology”, In Proceedings IEEE International Symposium on Circuits and Systems (ISCAS), pages 305 – 307, May 1996. [3] Libin Yao, Michiel Steyaert and Willey Sassen “Low Power Low Voltage Sigma Delta Modulators In Nanometer Cmos ” Springer,2006 [4] E. Seevinck, M. du Plessis, T.-H. Joubert, and A. E. Theron, “Active bootstrapped gain-enhancement technique for low- voltage circuits”, IEEE Transactions on Circuits and Systems—Part II: Analog and Digital Signal Processing, 45:1250 – 1254, September 1998. [5] P. Yu and H. Lee, “A high-swing 2-V CMOS operational amplifier with replica-amp gain enhancement”, IEEE Journal of Solid-State Circuits, 28:1265–1272, December 1993. [6] Jirayuth Mahattanakul, and Jamorn Chutichatuporn “Design Procedure for Two-Stage CMOS Opamp With Flexible Noise- Power Balancing Scheme” IEEE Transactions on circuits and systems -I: Regular Papers, Vol. 52, No. 8, August- 2005. [7] D. Johns and K. Martin, “Analog Integrated Circuit Design” New York: Wiley, 1997. [8] B. Razavi,” Design of Analog CMOS Integrated Circuits.”New York: McGraw-Hill, 2000 [9] S.Rabbi and B.A. Wooley “A 1.8V Digital-Audio Sigma-Delta Modulator in 0.8µm CMOS”,IEEE Journal of solid-State circuits. pp. 783-795 Vol.32,1997 [10] Paul R. Gaul and Robert G.Mayer “MOS Operational Amplifier Design-a tutorial overview” IEEE Journal of solid- State circuits, Vol. SC-17, No. 6, December 1982

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