AgO Product Overview


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Analog Circuit Optimization

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  • Ago is an EDA company focused on Analog and RF optimization. I’d like to go briefly into the company background, to go over the challenges that we see in analog and RF design, then introduce AnXplorer and its optimization approach.
  • The company was founde in 2007. Founders were previously in senior CAD development positions at National Semiconductor. In that time, they had a strong track record for innovation with 8 patent awards and 15 research papers and of course experience in developing industrial quality software. Headquarters was established in Silicon Valley with the AgO brand in 2009. The AnXplorer product was announced and the worldwide sales channel was established during the first quarter of 2010.
  • Total cost of ownership is addressed in this slide
  • Before looking AnXplorer at let’s take a step back and look at classic Analog design methodology. A design project typically starts with the design specification and constraints. The analog designer would typically use a schematic based tool to define the topology of the circuit. Then, an iterative approach is taken using a transistor level simulator to evaluate performance of that topology with particular device sizes and then devices are resized in order to try to fulfill the requirements and constraints of the design and the process is repeated. Then the sized schematic is used to layout and further adjustments and iterations can take place after the layout and extraction phases.
  • AgO has assumed that the definition of the topology is something that requires real expertise from the analog designer. However, AnXplorer aims to automate the more tedious tasks of device resizing and running and evaluating Spice simulations. Once the optimization is complete then the design activity can progress to physical layout and extraction.
  • The inputs to AnXplorer follow well known industry standards making them quite compatible with existing design flows. To begin with the design team will start with an Un-sized circuit schematic. They will define design variables which would be used in the optimization and the objectives of the design. As a result of the optimization by AnXplorer, there will be a sized and centered net list, and additionally an Exploration Database for tradeoff analysis is available. This allows designers to investigate intermediate points during the optimization. So the output is an optimized and centered net list which should meet or exceed the objectives that are specified in the design objectives.
  • AnXplorer has been conceived to work with existing environments. Today, Cadence Spectre, Synopsys HSpice, Legend Design MSim are fully supported. The operating systems that are supported are Red Hat Enterprise Linux 5 32b and 64b and Ubuntu 10
  • So in conclusion, we see Analog and RF design is rapidly growing in importance. We see that managing the risk of a respin is a major challenge for design teams. With AnXplorer, we automate the resizing and simulation activities which are normally a tedious, iterative task for the designer. The AnXplorer high-performance optimizer should produce designs that meet objectives and constraints thus improving the productivity of the design team, improving yield, and reducing the probability of respins.
  • AgO Product Overview

    1. 1. Analog Circuit Synthesis enable Carrier-Grade QoS Services
    2. 2. Agenda <ul><li>Company Background </li></ul><ul><li>Challenges in Analog and RF design </li></ul><ul><li>Overview of AnXplorer </li></ul><ul><li>Competitive Differentiation </li></ul>
    3. 3. Company Background <ul><li>Focus on Analog & RF optimisation for improved production yield </li></ul><ul><li>Founded by expert CAD developers in 2007 </li></ul><ul><li>Previously in senior CAD development positions at National Semiconductor </li></ul><ul><ul><li>Strong track record 8 patent awards and 15 research papers published </li></ul></ul><ul><li>AgO - A dvanced G eneration O ptimization </li></ul><ul><li>Global Sales & Marketing Presence Q2 2010 </li></ul>
    4. 4. Challenges in Analog & RF Design <ul><li>Respin avoidance </li></ul><ul><li>Analog circuits are responsible for ~ 50% of IC design re-spins </li></ul><ul><li>Re-spins can mean missing market windows and unbudgeted costs </li></ul><ul><li>Achieving design specification </li></ul><ul><li>Meeting or beating performance while minimising cost of implementation </li></ul><ul><li>Managing greater complexity in operating and power saving modes </li></ul><ul><li>Maximising yield </li></ul><ul><li>Validating greater numbers of process, voltage and temperature corners </li></ul><ul><li>Efficiently centering design across all PVT corners </li></ul><ul><li>Design porting </li></ul><ul><li>Moving existing circuit designs to similar technologies </li></ul><ul><li>Re-centering design to meet constraints of new technology </li></ul>
    5. 5. Classic Analog Design Methodology <ul><li>Design methodology has changed little over the years </li></ul><ul><li>Manual, iterative design with many SPICE runs </li></ul>Define topology & resize devices Physical layout & adjust Extraction Layout verification Design specification & constraints Spice Spice
    6. 6. AnXplorer Goals <ul><li>Quickly size and bias a circuit in a given technology </li></ul><ul><li>Explore suitability of different design options for a given purpose in a short time </li></ul><ul><li>Re-target designs from one process to another </li></ul><ul><li>Robust design in the face of process and temperature variation </li></ul><ul><li>Support all types of devices </li></ul><ul><ul><li>Not limited to CMOS </li></ul></ul><ul><li>Give designer opportunity to explore results </li></ul>
    7. 7. AgO Design Methodology <ul><li>AnXplorer automates device resizing using SPICE runs </li></ul>Define topology Physical layout & adjust Extraction Layout verification Design specification & constraints Feasibility analysis Global optimization AnXplorer Centering
    8. 8. Porting of Existing Circuits AnXplorer Circuit in technology X Circuit sized for technology Y Porting mode <ul><li>Common challenge </li></ul><ul><li>Port existing design in technology X (say 180 nm) to technology Y (in 180 nm) </li></ul><ul><li>Ensure that original design goals are met </li></ul><ul><li>AnXplorer approach </li></ul><ul><li>Start with original sized circuit </li></ul><ul><li>Define variable ranges for target circuit </li></ul><ul><li>“ One click” command </li></ul><ul><ul><li>Optimises and centers with new PVT corners </li></ul></ul>
    9. 9. Implicit Objectives <ul><li>Imposes implicit objectives on conditions of devices at DC operating point </li></ul><ul><li>Customizable objectives </li></ul><ul><li>Detects common sub-circuits and imposes constraints on their operating conditions </li></ul><ul><li>Ensures a robust DC operating point </li></ul><ul><li>Feature only available for MOS devices </li></ul><ul><li>Examples of sub-circuits: </li></ul><ul><li>transistors in saturation </li></ul><ul><li>transistors in linear region </li></ul><ul><li>current mirrors </li></ul><ul><li>level shifters </li></ul><ul><li>differential pairs </li></ul><ul><li>voltage reference </li></ul><ul><li>current mirror banks </li></ul><ul><li>etc </li></ul>
    10. 10. Hierarchical Design Objectives <ul><li>Most tools support a weight-based prioritisation for multiple objectives </li></ul><ul><ul><li>Designer is often unsure of relative weights </li></ul></ul><ul><li>AnXplorer supports hierarchical design objectives </li></ul><ul><ul><li>User defines relative priority of different objectives </li></ul></ul><ul><li>AnXplorer achieves more important objectives before optimizing others </li></ul>
    11. 11. Core Optimization Technology <ul><li>Early Optimisation tools </li></ul><ul><li>Frequently relied on traditional convex/gradient methods </li></ul><ul><li>These are known to have difficulty with multiple local minima </li></ul><ul><li>AnXplorer </li></ul><ul><li>Based on Evolutionary algorithm </li></ul><ul><li>Capable of finding global minimum in presence of many local minima </li></ul><ul><li>Successfully optimised tough tests e.g. Rastrigin’s function </li></ul><ul><li>Optional logarithmic partitioning of design space </li></ul>Supports both simulation-based optimization & equation-based optimization
    12. 12. Trade-off Analysis <ul><li>Finds multiple design points satisfying design objectives </li></ul><ul><li>Creates exploration database for post-optimization analysis </li></ul><ul><ul><li>Database stores all explored design points </li></ul></ul><ul><ul><li>Query language or GUI </li></ul></ul><ul><li>Useful for trade-off analysis with conflicting objectives </li></ul><ul><li>Useful for “what-if” analysis </li></ul>
    13. 13. Industry Standard Formats AnXplorer Design objectives Un-sized circuit Schematics Sized and centered net list Exploration database for Trade off analysis Definition of Design variables Compatible with existing design flows
    14. 14. Design Environment <ul><li>Spice Simulators </li></ul><ul><ul><li>Cadence Spectre </li></ul></ul><ul><ul><li>Synopsys HSpice </li></ul></ul><ul><ul><li>Legend Design Technology MSim </li></ul></ul><ul><ul><li>Mentor Eldo </li></ul></ul><ul><ul><li>Silvaco SmartSpice </li></ul></ul><ul><li>Multi-threading support </li></ul><ul><li>Operating system </li></ul><ul><ul><li>Red Hat Enterprise Linux </li></ul></ul>
    15. 15. Competitive Differentiation <ul><li>One product, four optimization strategies </li></ul><ul><li>Robust centering to maximise yield </li></ul><ul><li>Implicit objectives for stable DC operation (CMOS) </li></ul><ul><li>Hierarchical design objectives </li></ul><ul><li>User can perform trade-off analysis </li></ul><ul><li>Industry standard formats and simulators </li></ul><ul><li>Core based on Evolutionary Algorithm </li></ul><ul><ul><li>Solves tough optimization tests </li></ul></ul><ul><ul><li>Performs better than traditional Gradient Algorithms </li></ul></ul>
    16. 16. Promotion <ul><li>EE Times Global Coverage </li></ul><ul><li>Document Download 300 per month </li></ul><ul><li>No of customers engagement 50 in 2011 </li></ul><ul><li>Trade Show: DATE 2011 Grenoble France </li></ul>
    17. 17. AnXplorer New generation Analog & RF Circuit Synthesis David Wood David, Hillol Sarkar [email_address] [email_address]