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AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
AgO Analog Circuit Optimization
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AgO Analog Circuit Optimization

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Analog and RF Circuit Optimization …

Analog and RF Circuit Optimization
30% Leakage current reduction

Published in: Devices & Hardware
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  • 1. Analog & RF Circuit Optimization 10X Faster & Max Yield Hillol Sarkar Hillol.Sarkar@ago-inc.com
  • 2. What we will talk about • Company Background • Challenges in Analog and RF design © Copyright AgO Inc 20112 • Overview of AnXplorer • Competitive Differentiation
  • 3. Company Background • Founded in 2007 • Held senior positions at National • Held senior position in GE and Toshiba • Awarded 8 Patents and 15 papers -National © Copyright AgO Inc 20113 • AgO - Advanced Generation Optimization • Global Sales & Marketing Presence Q4 2011
  • 4. Challenges in Analog & RF Design Achieving design specification • Meeting or beating performance while minimising cost of implementation • Managing greater complexity in operating and power saving modes Maximising yield • Validating greater numbers of process, voltage and temperature corners • Efficiently centering design across all PVT corners using Monte Carlo © Copyright AgO Inc 20114 Respin avoidance • Analog circuits are responsible for ~ 50% of IC design re-spins • Re-spins can mean missing market windows and unbudgeted costs • Managing greater complexity in operating and power saving modes Design porting • Moving existing circuit designs to similar technologies • Re-centering design to meet constraints of new technology
  • 5. Classic Analog Design Methodology • Design methodology has changed little over the years • Manual, iterative design with many SPICE runs Define topology & resize devices Design specification & constraints Spice © Copyright AgO Inc 20115 Physical layout & adjust Extraction Layout verification Spice
  • 6. Optimization StrategyOptimization Strategy Feasibility Global Optimization Centering Database Description • DC Operation • Increase Margin Description • Single Corner • Meet performance Description • All Corners • Rapid Size Description • Conflict • Change Priority © Copyright AgO Inc 20116 • Increase Margin • Quick check • Best Design Space • Meet performance • Monte Carlo • Ready for Center • Rapid Size • Ready for P&R • Change Priority • System Analysis AgO Optimization Strategy
  • 7. AnXplorer Goals • Quickly size W/L a circuit in a given technology • Explore suitability of different design options • Robust design over PVT & Monte Carlo • Support all types of devices © Copyright AgO Inc 20117 • Explore results using database • Optimize production yield
  • 8. AgO Design Methodology AnXplorer automates device sizing Define topology Design specification & constraints Feasibility Global © Copyright AgO Inc 20118 Physical layout & adjust Extraction Layout verification Centering
  • 9. Porting of Existing Circuits Vendor X Common challenge • Port existing design in technology X (say 180 nm) to technology Y (in 180 nm) • Ensure that original design goals are met © Copyright AgO Inc 20119 Vendor Y AnXplorer approach • Start with original sized circuit • Define variable ranges for target circuit • “One click” command • Optimises and centers with new PVT corners Same Node Porting
  • 10. Prioritized Design Objectives • Most tools support a weight-based prioritisation for multiple objectives – Designer is often unsure of relative weights • AnXplorer supports hierarchical design objectives – User defines relative priority of different objectives © Copyright AgO Inc 201110 – User defines relative priority of different objectives • AnXplorer achieves important objectives before optimizing others
  • 11. Implicit Objectives • Imposes implicit objectives on conditions of devices at DC operating point • Customizable objectives • Detects common sub-circuits and imposes constraints on their Examples of sub- circuits: • transistors in saturation • transistors in linear region © Copyright AgO Inc 201111 imposes constraints on their operating conditions • Ensures a robust DC operating point • Feature only available for MOS devices region • current mirrors • level shifters • differential pairs • voltage reference • current mirror banks • etc
  • 12. Core Optimization Technology Early Optimisation tools • Frequently relied on traditional convex/gradient methods • These are known to have difficulty with multiple local minima AnXplorer © Copyright AgO Inc 201112 AnXplorer • Based on Evolutionary algorithm • Capable of finding global minimum in presence of many local minima • Successfully optimised tough tests e.g. Rastrigin’s function • Optional logarithmic partitioning of design space Supports both simulation-based optimization & equation-based optimization
  • 13. Multiple Local Minimum © Copyright AgO Inc 201113
  • 14. Trade-off Analysis • Finds multiple design points satisfying design objectives • Creates exploration database for post- optimization analysis – Database stores all explored design points © Copyright AgO Inc 201114 – Database stores all explored design points – Query language or GUI • Useful for trade-off analysis with conflicting objectives • Useful for “what-if” analysis
  • 15. Industry Standard Formats Design objectives Un-sized circuit Schematics Definition of Design variables Compatible with existing design flows © Copyright AgO Inc 201115 AnXplorer Sized and centered net list Exploration database for Trade off analysis
  • 16. Design Environment • Spice Simulators – Cadence Spectre – Synopsys HSpice – Mentor Eldo – Multi-threading support © Copyright AgO Inc 201116 – Multi-threading support • Operating system – Red Hat Enterprise Linux RHEL 5
  • 17. Competitive Differentiation • One product, four optimization steps • Robust centering to maximise yield –Monte Carlo • Implicit objectives for stable DC operation (CMOS) • Hierarchical design objectives • User can perform trade-off analysis © Copyright AgO Inc 201117 • User can perform trade-off analysis • Industry standard formats and simulators • Core based on Evolutionary Algorithm
  • 18. Analog and RF Optimization New generation Analog & RF Circuit Optimization Hillol Sarkar Hillol.Sarkar@ago-inc.comHillol.Sarkar@ago-inc.com

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