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Maximum difference between partition sizes is usually specified as a percentage. For example, if 5% is the maximum allowable imbalance, then a partition cannot have more than 55% of the vertices (or sum of vertex weights) in a 2-way partitioning solutionWhat does cutsize mean?It refers to the number (sum of weights) of the edges that are “cut”, i.e., connect two vertices from two different partitions
Transcript
1.
VLSI Physical Design Automation
Introduction , partitioning
Hemant kumar
Roll No: 2910207
Cont no. 09992440824
Dept. of Electronics &
Communication Engg.,
KITM, KURUKSHETRA.
2.
• VLSI CAD (also known as EDA – electronic design
automation) students, in particular for chip implementation
(physical design)
• Circuit designers to understand how tools work behind
the scene
• Process engineers to tune process that is more
circuit/physical design friendly
• Mathematical/Computer Science majors who want to find
tough problems to solve
– Lots of VLSI physical design problems can be
formulated into combinatorial optimization or
mathematical programming problems.
– Actually, most CAD problems are NP-complete ->
heuristics
Intended Audience
3.
Objective of this Lecture
To review the materials used in fabrication of VLSI devices.
To review the structure of devices and process involved in
fabricating different types of VLSI circuits.
To review the basic algorithm concepts.
Understand the process of VLSI layout design.
Study the basic algorithms used in layout design of VLSI
circuits.
Learn about the physical design automation techniques used
in the best-known academic and commercial layout systems.
4.
Physical Design
• Converts a circuit description into a geometric
description.
– This description is used for fabrication of the chip.
• Basic steps in the physical design cycle:
1. Partitioning
2. Floorplanning
3. placement
4. Routing
5. Compaction
5.
6
System Level Partitioning
Board Level Partitioning
Chip Level Partitioning
System
PCBs
Chips
Subcircuits
/ Blocks
So, what is Partitioning?
6.
7
Why partition ?
• Ask Lord Curzon
– The most effective way to solve problems of high
complexity : Parallel CAD Development
• System-level partitioning for multi-chip designs
– Inter-chip interconnection delay dominates system
performance
• IO Pin Limitation
• In deep-submicron designs, partitioning defines local
and global interconnect, and has significant impact on
circuit performance
7.
Importance of Circuit Partitioning
Divide-and-conquer methodology
The most effective way to solve problems of high complexity
E.g.: min-cut based placement, partitioning-based test
generation,…
System-level partitioning for multi-chip designs
inter-chip interconnection delay dominates system
performance.
Circuit emulation/parallel simulation
partition large circuit into multiple FPGAs (e.g. Quickturn), or
multiple special-purpose processors (e.g. Zycad).
Parallel CAD development
Task decomposition and load balancing
In deep-submicron designs, partitioning defines local and
global interconnect, and has significant impact on circuit
performance
…… ……
8.
9
Objectives
• Since each partition can correspond to a chip, interesting
objectives are:
– Minimum number of partitions
• Subject to maximum size (area) of each partition
– Minimum number of interconnections between partitions
• Since they correspond to off-chip wiring with more
delay and less reliability
• Less pin count on ICs (larger IO pins, much higher
packaging cost)
– Balanced partitioning given bound for area of each
partition
9.
Partitioning:
Partitioning is the task of dividing a circuit into smaller parts .
The objective is to partition the circuit into parts, so that the size
of each component is within prescribed ranges and the number of
connections between the components is minimized .
Different ways to partition correspond to different circuit
implementations . Therefore, a good partitioning can significantly
improve circuit performance and reduce layout costs .
• Decomposition of a complex system into smaller subsystems
– Done hierarchically
– Partitioning done until each subsystem has manageable size
– Each subsystem can be designed independently
• Interconnections between partitions minimized
– Less hassle interfacing the subsystems
– Communication between subsystems usually costly
10.
Partitioning of a Circuit
Input size: 48
Cut 1=4
Size 1=15
Cut 2=4
Size 2=16 Size 3=17
11.
Hierarcahical Partitioning
• Levels of partitioning:
– System-level partitioning:
Each sub-system can be designed as a single PCB
– Board-level partitioning:
Circuit assigned to a PCB is partitioned into sub-circuits
each fabricated as a VLSI chip
– Chip-level partitioning:
Circuit assigned to the chip is divided into manageable sub-
circuits
NOTE: physically not necessary
12.
13
Delay at Different Levels of Partitions
A
B
C
PCB1
D
x
10x
20x
PCB2
13.
14
Partitioning: Formal Definition
• Input:
– Graph or hypergraph
– Usually with vertex weights
– Usually weighted edges
• Constraints
– Number of partitions (K-way partitioning)
– Maximum capacity of each partition
OR
maximum allowable difference between partitions
• Objective
– Assign nodes to partitions subject to constraints
s.t. the cutsize is minimized
• Tractability
- Is NP-complete
14.
Circuit Representation
• Netlist:
– Gates:A, B, C, D
– Nets: {A,B,C}, {B,D}, {C,D}
• Hypergraph:
– Vertices: A, B, C, D
– Hyperedges: {A,B,C}, {B,D}, {C,D}
– Vertex label: Gate size/area
– Hyperedge label:
Importance of net (weight)
A
B
C D
A
B
C D
15.
16
Circuit Partitioning: Formulation
Bi-partitioning formulation:
Minimize interconnections between partitions
• Minimum cut: min c(x, x’)
• minimum bisection: min c(x, x’) with |x|= |x’|
• minimum ratio-cut: min c(x, x’) / |x||x’|
X X’
c(X,X’)
16.
17
A Bi-Partitioning Example
Min-cut size=13
Min-Bisection size = 300
Min-ratio-cut size= 19
a
b
c e
d f
mini-ratio-cut min-bisection
min-cut
9
10
100
100 100
100100
100
4
Ratio-cut helps to identify natural clusters
18.
19
Restricted Partition Problem
• Restrictions:
– For Bisectioning of circuit
– Assume all gates are of the same size
– Works only for 2-terminal nets
• If all nets are 2-terminal, hypergraph graph
a
b
c d
Hypergraph
Representation
Graph
Representation
a
b
c d
19.
20
Problem Formulation
• Input: A graph with
– Set verticesV (|V| = 2n)
– Set of edges E (|E| = m)
– Cost cAB for each edge {A, B} in E
• Output: 2 partitions X &Y such that
– Total cost of edge cuts is minimized
– Each partition has n vertices
• This problem is NP-Complete!!!!!
20.
21
A Trivial Approach
• Try all possible bisections and find the best one
• If there are 2n vertices,
# of possibilities = (2n)! / n!2 = nO(n)
• For 4 vertices (a,b,c,d), 3 possibilities
1. X={a,b} & Y={c,d}
2. X={a,c} & Y={b,d}
3. X={a,d} & Y={b,c}
• For 100 vertices, 5x1028 possibilities
• Need 1.59x1013 years if one can try 100M
possbilities per second
21.
Definitions
• Definition 1: Consider any node a in block X. The
contribution of node a to the cutset is called the external cost
of a and is denoted as Ea, where
Ea =Σcav (for all v in Y)
• Definition 2: The internal cost Ia of node a in X is defined
as follows:
Ia =Σcav (for all v in X)
22.
Example
• External cost (connection) Ea = 2
• Internal cost Ia = 1
a
b
c
d
X Y
23.
Idea of KL Algorithm
• Da = Decrease in cut value if moving a = Ea-Ia
– Moving node a from block X to block Y would decrease the
value of the cutset by Ea and increase it by Ia
a
b
c
d
X Y
a
b
c
d
X Y
Da = 2-1 = 1
Db = 1-1 = 0
24.
Idea of KL Algorithm
• Note that we want to balance two partitions
• If switch A & B, gain(A,B) = DA+DB-2cAB
– cAB : edge cost for AB
A
B
C
D
X Y
A
B
C
D
X Y
gain(A,B) = 1+0-2 = -1
25.
• Start with any initial legal partitions X and Y
• A pass (exchanging each vertex exactly once) is described
below:
1. For i := 1 to n do
From the unlocked (unexchanged) vertices,
choose a pair (A,B) s.t. gain(A,B) is largest
Exchange A and B. Lock A and B.
Let gi = gain(A,B)
2. Find the k s.t. G=g1+...+gk is maximized
3. Switch the first k pairs
• Repeat the pass until there is no
improvement (G=0)
Idea of KL Algorithm
26.
Example
1
X
2
3
4
5
6
Y
Original CutValue = 9
4
X
2
3
1
5
6
Y
Optimal CutValue = 5
A good step-by-step example in SY book
27.
Time Complexity of KL
• For each pass,
– O(n2) time to find the best pair to exchange.
– n pairs exchanged.
– Total time is O(n3) per pass.
• Better implementation can get O(n2log n) time per pass.
• Number of passes is usually small.
28.
Recap of Kernighan-Lin’s Algorithm
Pair-wise exchange of nodes to reduce cut size
Allow cut size to increase temporarily within a
pass
Compute the gain of a swap
Repeat Perform a feasible swap of max gain
Mark swapped nodes “locked”;
Update swap gains;
Until no feasible swap;
Find max prefix partial sum in gain sequence g1,
g2, …, gm
Make corresponding swaps permanent.
Start another pass if current pass reduces the
cut size
(usually converge after a few passes)
u v a
v u
locked
29.
Other Partitioning Methods
• KL and FM have each held up very well
• Min-cut / max-flow algorithms
–Ford-Fulkerson – for unconstrained
partitions
• Ratio cut
• Genetic algorithm
• Simulated annealing
30.
References and Copyright
Textbooks referred (none required)
[Mic94] G. De Micheli
“Synthesis and Optimization of Digital Circuits”
McGraw-Hill, 1994.
[CLR90] T. H. Cormen, C. E. Leiserson, R. L. Rivest
“Introduction to Algorithms”
MIT Press, 1990.
[Sar96] M. Sarrafzadeh, C. K. Wong
“An Introduction to VLSI Physical Design”
McGraw-Hill, 1996.
[She99] N. Sherwani
“Algorithms For VLSI Physical Design Automation”
Kluwer Academic Publishers, 3rd edition, 1999.
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