Hush…tell you something novel about flash memory

1,646 views
1,458 views

Published on

This slides presents a excellent work on flash memory from Non-Volatile Systems Laboratory, University of California, San Diego.

Published in: Technology, Business
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
1,646
On SlideShare
0
From Embeds
0
Number of Embeds
3
Actions
Shares
0
Downloads
8
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Hush…tell you something novel about flash memory

  1. 1. Hush…tell you something novel about flash memory ! Zhichao Liang frankey0207@gmail.com
  2. 2. Outline• Background• Some tests• Possible applications• Some extensions
  3. 3. Outline• Background• Some tests• Possible applications• Some extensions
  4. 4. Background• Flash manufacturers provide conservative and often vague guidelines about performance, energy consumption and reliability.• The lack of detail complicates the design of systems which fully exploit flash memory’s capabilities.
  5. 5. Outline• Background• Some tests• Possible applications• Some extensions
  6. 6. Test subjectsCharacterizing Flash Memory: Anomalies, Observations, andApplications by Laura M. Grupp, Adrian M. Caulfield, Joel Coburn etc.(MIRCO’09)
  7. 7. The testsQuantify known and unknown idiosyncrasies• Performance• Energy Efficiency• Reliability
  8. 8. Read Latency• The read latency varies little by manufacturer or chip, and are in good agreement with values from publicly available datasheets.
  9. 9. Erase Latency• Erase latency exhibits a smaller gap, but manufacturer B enjoys an advantage for SLC and E for MLC.
  10. 10. Program Latency• MLC chips have, on average, longer and enormously variable program latencies.
  11. 11. Program Speed Anomaly• Programming speed varies dramatically between pages in MLC devices in a predictable pattern.
  12. 12. Performance Increase Anomaly• Performance varies predictably as the devices begin to wear out.
  13. 13. Power• The table presents peak power, average power, idle power, and per-operation energy for each operation.
  14. 14. Program Energy• Fast and slow pages show a disparity similar to the one we observed for program time.
  15. 15. Reliability• Flash memory can corrupt data in three main ways: wear-out, program disturb and read disturb.• 10 erase-program-read cycles + 990 erase- program.• 1 million erases for SLC and 100,000 erases for MLC.
  16. 16. Error Rates• The difference between SLC and MLC is stark.
  17. 17. Disparity in MLC• MLC chips show large variation in error rates among pages in a single block.
  18. 18. Program Disturb• Erase a block and repeatedly program half of one page to 0.
  19. 19. Read Disturb• Write a test pattern to several blocks on the flash chip and repeatedly read the pattern back.
  20. 20. Summary• Fast pages and slow pages in MLC• High energy-consumption pages and low energy-consumption pages in MLC• Better program performance as wear out for SLC and MLC• High error-rate pages and low error-rate pages in MLC• Program disturb and read disturb
  21. 21. Outline• Background• Some tests• Possible applications• Some extensions
  22. 22. A variation-aware FTL• Mango adds a priority to incoming IO request and it will do its best to use fast pages for the high-priority writes.• This variation-aware FTL is evaluated in two scenarios: Swap&Netbook.• For Swap, it can significantly increase responsiveness for swap requests.• For Netbook, it can slightly reduce the energy drain on the battery.
  23. 23. Flash-aware data encoding• Womcode is a coding techniques makes rewriting wom possible!• Effective lifetime: - SLC: 2*(2/3) = 33% increase - MLC: (2*(2/3) + 1)*(1/2) = 17% increase
  24. 24. Outline• Background• Some tests• Possible applications• Some extensions
  25. 25. Gordon• A system architecture for data-centric applications that combines low-power processors, flash memory, and data-centric programming.• Performance & Reduced Power ConsumptionGordon: Using Flash Memory to Build Fast, Power-efficient Clusters for Data-intensive Applications by Adrian M. Caufield Laura M. Grupp and Steven Swanson(ASPLOS’09)
  26. 26. Gordon Node• 256GB flash storage, a flash storage controller, 2GB of ECC DDR2 SDRAM, a 1.9Ghz Intel Atom processor and other supporting circuitry.
  27. 27. Gordon Enclosure• A enclosure holds 16 nodes(4TB storage) and provides 14.4GB/s of aggregate IO bandwidth.
  28. 28. Q&A

×