GOEPEL Electronics TAP Checker
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GOEPEL Electronics TAP Checker

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Learn about TAP Checker, a software tool for BSDL verification and automated validation of chip-level JTAG / boundary-scan implementations; ...

Learn about TAP Checker, a software tool for BSDL verification and automated validation of chip-level JTAG / boundary-scan implementations;
support for multi-chip modules; IEEE 1149.1 and IEEE 1149.6 compliant; VHDL, VERILOG, and STIL output;

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GOEPEL Electronics TAP Checker GOEPEL Electronics TAP Checker Presentation Transcript

  • Automated validation ofJTAG / boundary scan implementations (C) 2012 GOEPEL Electronics, Austin, TX / USA
  • Outline• Why implement JTAG in ICs in the first place?• Why validate and verify JTAG implementations?• Automating the validation of JTAG implementations© 2012 GOEPEL electronics JTAG/Boundary Scan 2
  • Benefits of JTAG / boundary scan• Test for manufacturing defects at board and system level• Access to on-chip test / debug / emulation resources• In-system programming• Efficient ATPG tools, pin level diagnostics• Deterministic (predictive) test coverage• Standardized: IEEE 1149.1, 1149.4, 1149.6, 1149.7, 1500, 1532, P1149.8.1, P1687, ...© 2012 GOEPEL electronics JTAG/Boundary Scan 3 View slide
  • JTAG / boundary scan applications© 2012 GOEPEL electronics JTAG/Boundary Scan 4 View slide
  • Outline• Why implement JTAG in ICs in the first place?• Why validate and verify JTAG implementations?• Automating the validation of JTAG implementations© 2012 GOEPEL electronics JTAG/Boundary Scan 5
  • Why verify JTAG implementations?• IEEE standard compliance• Enable your customers to reap the benefits of JTAG• Board / system applications: • Connectivity tests rely on Boundary Register, EXTEST functionality • Multiple devices daisy chained need to coexist • Reliance on correct description of JTAG features (BSDL)© 2012 GOEPEL electronics JTAG/Boundary Scan 6
  • TAP Checker™ • Automated generation of test bench based on BSDL • IEEE 1149.1 and IEEE 1149.6 BSDL, .ALL IEEE 1149.1 IEEE 1149.6 • Support for multi-chip modules and 3-D ICs TAPChecker™ • Output formats: Verilog (IEEE 1364), VHDL (IEEE 1076), and STIL (IEEE 1450) Verilog, VHDL STIL • Validation of JTAG design prior to tape-out • Test on ATE for verification of JTAG implementation Semiconductor Simulator ATE© 2012 GOEPEL electronics JTAG/Boundary Scan 7
  • Outline• Why implement JTAG in ICs in the first place?• Why validate and verify JTAG implementations?• Automating the validation of JTAG implementations© 2012 GOEPEL electronics JTAG/Boundary Scan 8
  • TAP Checker™• Select the tests to include in the test bench© 2012 GOEPEL electronics JTAG/Boundary Scan 9
  • TAP Checker™• Select input and output directories and files© 2012 GOEPEL electronics JTAG/Boundary Scan 10
  • TAP Checker™• Adjust timing and test related settings as needed© 2012 GOEPEL electronics JTAG/Boundary Scan 11
  • TAP Checker™• Select output formats and select various output options as needed© 2012 GOEPEL electronics JTAG/Boundary Scan 12
  • TAP Checker™• Run the test bench generation• Output file(s) are generated and stored in specified location© 2012 GOEPEL electronics JTAG/Boundary Scan 13
  • Summary• JTAG/boundary scan features can provide huge benefits for device, board, and system test• Requirement: IEEE 1149.x compliance• JTAG implementations must be validated & verified© 2012 GOEPEL electronics JTAG/Boundary Scan 14
  • Thank you for your attention • For further information, please: • Visit our website at www.goepelusa.com • Call us at 1-888-4GOEPEL • Email us at sales@goepelusa.com© 2012 GOEPEL electronics JTAG/Boundary Scan 15