Your SlideShare is downloading. ×
0
Flip flop
Flip flop
Flip flop
Flip flop
Flip flop
Flip flop
Flip flop
Flip flop
Flip flop
Flip flop
Flip flop
Flip flop
Flip flop
Flip flop
Upcoming SlideShare
Loading in...5
×

Thanks for flagging this SlideShare!

Oops! An error has occurred.

×
Saving this for later? Get the SlideShare app to save on your phone or tablet. Read anywhere, anytime – even offline.
Text the download link to your phone
Standard text messaging rates apply

Flip flop

9,025

Published on

Published in: Technology, Business
0 Comments
3 Likes
Statistics
Notes
  • Be the first to comment

No Downloads
Views
Total Views
9,025
On Slideshare
0
From Embeds
0
Number of Embeds
0
Actions
Shares
0
Downloads
530
Comments
0
Likes
3
Embeds 0
No embeds

Report content
Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
No notes for slide
  • Give qualifications of instructors: DAP teaching computer architecture at Berkeley since 1977 Co-athor of textbook used in class Best known for being one of pioneers of RISC currently author of article on future of microprocessors in SciAm Sept 1995 RY took 152 as student, TAed 152,instructor in 152 undergrad and grad work at Berkeley joined NextGen to design fact 80x86 microprocessors one of architects of UltraSPARC fastest SPARC mper shipping this Fall
  • credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.
  • credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.
  • Transcript

    • 1. Sequential Circuits: Flip flops By: C.SARAVANAN D.EEE Reg No.29307106
    • 2. Overview <ul><li>Latches respond to trigger levels on control inputs </li></ul><ul><ul><li>Example: If G = 1, input reflected at output </li></ul></ul><ul><li>Difficult to precisely time when to store data with latches </li></ul><ul><li>Flip flips store data on a rising or falling trigger edge. </li></ul><ul><ul><li>Example: control input transitions from 0 -&gt; 1, data input appears at output </li></ul></ul><ul><ul><li>Data remains stable in the flip flop until until next rising edge. </li></ul></ul><ul><li>Different types of flip flops serve different functions </li></ul><ul><li>Flip flops can be defined with characteristic functions. </li></ul>
    • 3. D Latch Q Q’ C S’ R’ S R S R C Q Q’ 0 0 1 Q 0 Q 0 ’ Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q 0 Q 0 ’ Store 0 1 0 1 1 1 1 0 X 0 Q 0 Q 0 ’ D C Q Q’ <ul><li>When C is high, D passes from input to output (Q) </li></ul>D
    • 4. Clocking Event <ul><li>What if the output only changed on a C transition? </li></ul>Lo-Hi edge Hi-Lo edge C D Q Q’ 0 0 1 1 1 0 X 0 Q 0 Q 0 ’ D C Q Q’ Positive edge triggered
    • 5. Master-Slave D Flip Flop <ul><li>Consider two latches combined together </li></ul><ul><li>Only one C value active at a time </li></ul><ul><li>Output changes on falling edge of the clock </li></ul>
    • 6. D Flip-Flop D gets latched to Q on the rising edge of the clock. <ul><li>Stores a value on the positive edge of C </li></ul><ul><li>Input changes at other times have no effect on output </li></ul>C D Q Q’ 0 0 1 1 1 0 X 0 Q 0 Q 0 ’ D C Q Q’ Positive edge triggered
    • 7. Clocked D Flip-Flop <ul><li>Stores a value on the positive edge of C </li></ul><ul><li>Input changes at other times have no effect on output </li></ul>
    • 8. Positive and Negative Edge D Flip-Flop <ul><li>D flops can be triggered on positive or negative edge </li></ul><ul><li>Bubble before Clock (C) input indicates negative edge trigger </li></ul>Lo-Hi edge Hi-Lo edge
    • 9. Clocked J-K Flip Flop <ul><li>Two data inputs, J and K </li></ul><ul><li>J -&gt; set, K -&gt; reset, if J=K=1 then toggle output </li></ul>Characteristic Table
    • 10. Asynchronous Inputs <ul><li>J, K are synchronous inputs </li></ul><ul><ul><li>Effects on the output are synchronized with the CLK input . </li></ul></ul><ul><li>Asynchronous inputs operate independently of the synchronous inputs and clock </li></ul><ul><ul><li>Set the FF to 1/0 states at any time. </li></ul></ul>
    • 11. Asynchronous Inputs
    • 12. Asynchronous Inputs <ul><li>Note reset signal (R) for D flip flop </li></ul><ul><li>If R = 0, the output Q is cleared </li></ul><ul><li>This event can occur at any time, regardless of the value of the CLK </li></ul>
    • 13. Parallel Data Transfer <ul><li>Flip flops store outputs from combinational logic </li></ul><ul><li>Multiple flops can store a collection of data </li></ul>
    • 14. Summary <ul><li>Flip flops are powerful storage elements </li></ul><ul><ul><li>They can be constructed from gates and latches! </li></ul></ul><ul><li>D flip flop is simplest and most widely used </li></ul><ul><li>Asynchronous inputs allow for clearing and presetting the flip flop output </li></ul><ul><li>Multiple flops allow for data storage </li></ul><ul><ul><li>The basis of computer memory! </li></ul></ul><ul><li>Combine storage and logic to make a computation circuit </li></ul>

    ×