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Transcript

  • 1. Processing and Layout
    • Clean Room Requirements
  • 2. Processing and Layout
    • Silicon Start Material - epitaxy (on-arrangement)
      • Czochralski Method
      • Bridgeman Method
      • Current state of the art is 8” wafer dia.
  • 3. Processing and Layout
  • 4. Processing and Layout
    • Thermal Oxidation
      • Si + O 2 --> SiO 2
      • Si + 2H 2 O --> SiO 2 + 2H 2
      • Gate Oxidation
        • as thin as 40Å for a L=0.18µm CMOS Technology
      • Field Oxidation
        • thick 0.5µm to 1.5µm
  • 5. Processing and Layout
    • PhotoLithography
      • Photoresist: optically sensitive polymer which when exposed to UV light changes its solubility in specific chemicals
  • 6. Processing and Layout
    • Photo Mask Generation
  • 7. Processing and Layout
    • Etching
      • Wet etching (isotropic)
        • Use chemicals which react with underlying material but does not react with photoresist
      • Dry Etching (anisotropic or isotropic)
        • Use ionized gases and which react with underlying material but does not react with photoresist
  • 8. Processing and Layout
    • Doping Techniques - Diffusion
      • Wafers placed in a heated quartz tube (800°C to 1150°C)
      • Thermal energy results in dopant species to diffuse in the silicon lattice
  • 9. Processing and Layout
    • Doping Techniques - Ion Implantation
      • Energetic Ions are bombarded onto the silicon wafer
      • The depth and shape of the profile after implant can be modelled and depends on the energy and dose of the implant species
  • 10. Processing and Layout
    • Chemical Vapor Deposition
      • Silicon Nitride (Si 3 N 4 )
        • 3SiH 4 + 4NH 3 ------> Si 3 N 4 +12H 2
        • resistant to oxidation
      • Poly-Silicon
        • SiH 4 -----> Si + 2H 2
      • Oxide
        • SiH 4 +O 2 -----> SiO 2 + 2H 2
  • 11. Processing and Layout
    • Device Isolation
      • LOCOS (Local Oxidation of Silicon)
      • Use Nitride as a mask during oxidation

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