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  1. 1. Implementation of Temperature-Based Phase Change Memory Model Using Verilog-A Student : Yi-Bo Liao Adviser : Meng-Hsueh Chiang Ph.D. 1
  2. 2. Outline LOGO Background Verilog-A ideal PCM model Temperature-based PCM model Conclusion prospect 2
  3. 3. LOGO Background Verilog-A ideal PCM model Temperature-based PCM model Conclusion and prospect 3
  4. 4. LOGO Background Phase change memory; PCM Introduction of Verilog-A 4
  5. 5. LOGO Background Phase change memory; PCM Introduction of Verilog-A 5
  6. 6. Phase change memory (PCM) (1/2) LOGO Phase change memory; PCM. The material based on Ge2Sb2Te5 (GST). The first proposed by S. R. Ovshinsky in 1968 and is also called Ovonic Unified Memory (OUM). Top Electrode VIII 2 III IV V VI VII He GST 5 6 7 8 9 10 B C N O F Ne 13 14 15 16 17 18 Al Si P S Cl Ar 31 Ga 32 Ge 33 As 34 Se 35 Br 36 Kr Heater 49 In 50 Sn 51 Sb 52 Te 53 I 54 Xe Isolator 81 82 83 84 85 86 Tl Pb Bi Po At Rn Bottom Electrode 6
  7. 7. Phase change memory (PCM) (2/2) LOGO The PCM phase states: Amorphous state, Reset High resistance (~MΩ) Crystalline state, Set Low resistance (~kΩ) Partial crystalline The resistance between amorphous and crystalline. Ref. A. Itri et al., “Analysis of phase-transformation dynamics and estimation of amorphous-chalcogenide fraction in phase- change memories,” IEEE 42nd Annual International Reliability Physics Symposium, Phoenix, 2004. 7
  8. 8. Relation of time and temperature LOGO The PCM statuses can be altered by current pulsing. Amorphous state, Reset : Heating above the melting point (Tm) and then cooled down to Tx rapidly. Crystalline state, Set : A lower temperature between Tm and Tx should be kept for a certain period of time (TSet). Top Electrode GST Heater Isolator Bottom Electrode TReset TSet Ref. F.Atwood et al., “Current status of Chalcogenide phase change memory,” Device Research Conf. Tech. Dig., vol.1, pp. 29- 33, 2005. 8
  9. 9. PCM characteristics LOGO Non-linear I-V characteristic. (non-linear resistance) Programming region Read region ISet IReset I-V curve R-I curve 9
  10. 10. Threshold switching LOGO Threshold voltage, Vth Dynamic-on resistance, Ron Holding voltage, Vh Vth Ron 2.5kΩ Vth V − VB dVB IP IP = A − CP RL dt Vh Ref. D. Ielmini et al., “Parasitic reset in the programming transient of PCMs,” IEEE Electron Device Letter, vol.26, No. 11, Nov. 2005. 10
  11. 11. LOGO Background Phase change memory; PCM Introduction of Verilog-A 11
  12. 12. Introduction LOGO Verilog-Analog and Mixed-Signal In HSPICE version of 2006.03, it support compiler of Verilog-A. The Verilog-A model can be included in HSPICE. (seem a sub-circuit) Ref. Accellera, “Verilog_AMS language reference manual version2.2. November 2004,” available online: http://www.accellera.org/home. 12
  13. 13. Verilog-A characteristics LOGO Mathematical function (differential, integral) Module definition. dV ( p, n ) C module Cap(p,n); I ( p, n ) = C × inout p,n; dt electrical p,n; parameter real C=10p; analog begin I(p,n) <+ ddt(C*V(p,n)); end endmodule 13
  14. 14. LOGO Background Verilog-A ideal PCM model Temperature-based PCM model Conclusion and prospect 14
  15. 15. LOGO Verilog-A ideal PCM model Model structure Model implementation Model simulation results 15
  16. 16. LOGO Verilog-A ideal PCM model Model structure Model implementation Model simulation results 16
  17. 17. Model structure LOGO Ideal model only considers two states: Amorphous state, Reset Crystalline state, Set The ideal PCM approximated two types non-linear resistance. Top Electrode GST Set I-V curve ISet , TSet Set state or or Heater Isolator Bottom Electrode Reset I-V curve IReset , TReset Reset state p PCMR Decision Memory p module module module n To vary the state of model n 17
  18. 18. LOGO Verilog-A ideal PCM model Model structure Model implementation Model simulation results 18
  19. 19. PCMR module (1/3) LOGO To describe the I-V characteristic of the PCM There are two independent I-V curves I Ron (Vx,Ix) RSet Rsn (Vth,Ith) RReset V Vh 19
  20. 20. PCMR module (2/3) LOGO Amorphous state, Reset I if ( I(p,n) <= Ith ) begin Ron V(p,n) <+ I(p,n)*Rreset; end else begin (Vth, Ith) V(p,n) <+ Vh+I(p,n)*Ron; Ith RReset end Vh Vth V 20
  21. 21. PCMR module (3/3) LOGO Crystalline state, Set I if ( I(p,n) <= Ix ) begin Ron V(p,n) <+ I(p,n)*Rset; end (VX, IX) else begin IX RSet V(p,n) <+ Vh+I(p,n)*Ron; end Vh VX V 21
  22. 22. Decision module (1/4) LOGO The Set and Reset programming condition are determined respectively. ISet, TSet IReset, TReset The QS and QR output to memory module. Set part QS Input from PCMR module Output to memory module Reset part QR 22
  23. 23. Decision module (2/4) LOGO Using RC circuit to estimate the pulse width (TReset TSet). Using CCR (Current Control Resistance) to determine the pulse amplitude. ⎡ ⎛ − t ⎞⎤ VC (t ) = Vrc ⎢1 − exp⎜ ⎟ ⎜ R C ⎟⎥ ⎢ ⎣ ⎝ RC ⎠⎥ ⎦ Current Resistance TReset or TSet ⎡ Vrc ⎤ t = RRC C ln ⎢ ⎥ ⎣ Vrc − VC (t ) ⎦ AS Resistance (Ω) Fermi-Dirac AS − BS R(I ) = BS + 1 + exp[(I S − I )× F ] BS ISF Current (A) 23
  24. 24. Decision module (3/4) LOGO Set part (crystalline) <1> Iin<ISet Discharge (Do not estimate time) Vrc=1V <2> ISet≦Iin<IReset CCR_Set-1 Iin Charge (Estimate time) If T≧TSet,QS=1 RRC <3> Iin>IReset CCR_Set-2 Discharge (Do not estimate time) RMin R QS RMax RRC RRC CCR_Set-1 CCR_Set-3 CCR_Set-4 RMin RMin RMax RMin RMin CS CCR_Set-2 RMax RMax RMin RMax RMax CCR_Set-3 RMax RMax RMin CCR_Set-4 ISet IReset I 24
  25. 25. Decision module (4/4) LOGO Reset part (amorphous) <1> Iin<IReset Vrc=1V Discharge (Do not estimate time) CCR_Reset-1 Iin <2> Iin>IReset Charge (Estimate time) RRC If T≧TReset,QR=1 QR CCR_Reset-2 R RMax RMax RRC CCR_Reset-1 RMin CR RMax RMin RMin RMax CCR_Reset-2 ISet IReset I 25
  26. 26. Memory module LOGO Using VCR (Voltage Control Resistance) and capacitor to record the state. <1> QR=QS<1 VM=3V VCR_Reset and VCR_Set are high VCR_Reset resistance. QR QR=1 <2> QR=1 RMin QR=0 Charge, Mout is high stage (3V). RMax <3> QS=1 Mout Discharge, Mout is low stage (0V). VCR_Set QS QS=0 CM R RMax RMax VCR_Reset RMin QS=1 RMin RMax RMin VCR_Set 1V V 26
  27. 27. LOGO Verilog-A ideal PCM model Model structure Model implementation Model simulation results 27
  28. 28. Model simulation LOGO Ideal source testing DC analysis – PCM I-V characteristic Transient analysis – PCM R-I characteristic Current mirror source testing Current mirror Ip R1 = 2k (ohm) P P P Vpcm Iin Vin Iin Iin Ideal current source PCM + PCM PCM PCM Model Model Model model - N N N 28
  29. 29. Parameters LOGO Parameters Value Static resistance of Set, RSet 7kΩ Programming current of Set, ISet 600μA Programming time of Set, TSet 100ns Static resistance of Reset, RReset 200kΩ Programming current of Reset, IReset 1200μA Programming time of Reset, TReset 100ns Dynamic-on resistance, Ron 1kΩ Threshold voltage, Vth 0.78V Holding voltage, Vh 0.45V Initial condition, IC 0 or 1 Set Reset 29
  30. 30. DC analysis (1/2) LOGO 300 P Iin Set state PCM 250 Reset state Model N 200 Current (μA) 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Voltage (V) 30
  31. 31. DC analysis (2/2) LOGO R1 = 2k (ohm) 300 P Vin Set state + PCM 250 Reset state - Model N 200 Current (μA) 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Voltage (V) 31
  32. 32. Transient analysis (1/2) LOGO Input Reset and Set respectively. P IReset - 1200μA / 100ns Iin PCM ISet - 600μ A / 100ns Model N Input pulse Resistance of PCM model 1400 250 1200 200 1000 800 Current (μA) Resistance (kΩ) 150 600 400 100 200 50 0 -200 0 0 100 200 300 400 500 0 100 200 300 400 500 Time (ns) Time (ns) 32
  33. 33. Transient analysis (2/2) LOGO A series of current pulsing. R-I curve P Iin PCM Model N 250 1E+7 Real Device-Reset Real Device-Set 200 Verilog-A Model-Set 1E+6 Verilog-A Model-Reset Resistance (Ω) Current (μA) 150 1E+5 100 1E+4 50 0 1E+3 0 500 1000 1500 2000 2500 3000 0 200 400 600 800 1000 1200 1400 Time (ns) Current (μA) 33
  34. 34. Current mirror source testing (1/2) LOGO The variation of current pulse. Current mirror Ip 1800 Iin 1600 Iin Vpcm Ip 1400 Ideal current source PCM 1200 model Current (μA) 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 800 Time (ns) 34
  35. 35. Current mirror source testing (2/2) LOGO The variation of voltage and PCM Current mirror Ip resistance. Vpcm Iin Ideal current source PCM model 2.0 250 200 1.5 150 Rpcm (kΩ) Vpcm (V) 1.0 100 0.5 50 0.0 0 0 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700 800 Time (ns) Time (ns) 35
  36. 36. LOGO Background Verilog-A ideal PCM model Temperature-based PCM model Conclusion and prospect 36
  37. 37. LOGO Temperature-based PCM model Model structure Model implementation Model simulation results 37
  38. 38. LOGO Temperature-based PCM model Model structure Model implementation Model simulation results 38
  39. 39. Temperature-based PCM model LOGO Using temperature to determine the state of the PCM. Model will consider the partial crystalline 39
  40. 40. Model structure LOGO The temperature is constituted with two parts: Joule heating (Wj) t1 W − W TPCM = ∫ j d dt Heat dissipation (Wd) t0 C × V TPCM’ TPCM Wj p Temperature Crystalline VC PCMR Calculation Fraction n module module module Decision module Wd Heat Dissipation Feed VC back to calculate thermal conductivity (k) module Memory Deliver VMem to calculate module PCM resistance 40
  41. 41. LOGO Temperature-based PCM model Model structure Model implementation Model simulation results 41
  42. 42. PCMR module LOGO The PCM resistance based on the crystalline fraction (memorized), by a linear relation RPCM (VMem ) = RSet + (1 − VMem )(RReset − RSet ) The threshold voltage is also varied by crystalline fraction ( Vth (VMem ) = V X + (1 − VMem ) Vth _ Max − V X ) I Ron IX RPCM2 RPCM1 RSet RReset Vh VX Vth_2 Vth_1 Vth_Max V 42
  43. 43. Temperature calculation module (1/3)LOGO The temperature is constituted with two parts: t1 W − W C : Heat capacity ∫ Joule heating (Wj) TPCM = j d dt Heat dissipation (Wd) t0 C × V V : Volume of the active region W j = I PCM × VPCM = I PCM × (Vh + I PCM × Ron ) Considering the heat dissipation in one dimension, Wd can be approximated as ∂Q Wd = ∂t =∑ k∇TPCM k : thermal conductivity ⎛ ∂TPCM ∂TPCM ∂TPCM ⎞ TPCM − Troom = k⎜ ⎜ ∂x + ∂y + ∂z ⎟=k ⎟ ⎝ ⎠ d PCM 43
  44. 44. Temperature calculation module (2/3)LOGO The thermal energy differential equation yields ? d PCM W j ⎡ ⎛ −k ⎞⎤ TPCM (t ) = ⎢1 − exp⎜ ⎜d t ⎟⎥ + Troom ⎟ k ⎢ ⎣ ⎝ PCM CV ⎠⎥⎦ ? The thermal conductivity k is a function of the crystalline fraction VC, it is approximated as kC k (VC ) = (kC − k A )×VC + k A kA Ref. Y.-T. Kim et al., “Study on cell charateristics of PRAM using the phase-change simulation,” IEEE Simulation of Semiconductor Processes and Device Conference, pp.211-214, Sep. 2005. 44
  45. 45. Temperature calculation module (3/3)LOGO d PCM W j ⎡ ⎛ −k ⎞⎤ TPCM (t ) = ⎢1 − exp⎜ ⎜d t ⎟⎥ + Troom ⎟ k ⎢ ⎣ ⎝ PCM CV ⎠⎥⎦ The dPCM can be approached as d PCM = (Tm − Troom )× kC I Reset × (Vh + I Reset Ron ) Assuming the static temperature is reached after about a period of 5 time constants, CV is approximated as TReset × k A CV = 5 × d PCM 45
  46. 46. Crystalline fraction LOGO The crystalline fraction module follows JMA equation. If Tx≦TPCM<Tm Calculate VC Johnson-Mehl-Avrami (JMA) equation ⎡ ⎛t ⎞ p ⎛ − Ea ⎞⎤ VC = 1 − exp ⎢− ⎜ ⎟ exp⎜ ⎟⎥ ⎢ ⎜ t0 ⎟ ⎜k T ⎟⎥ t : time ⎣ ⎝ ⎠ ⎝ b PCM ⎠⎦ p : nucleation rate Ea : activation energy t0 : scaling factor kb : Boltzmann’s constant TPCM : temperature Ref. X. Q. Wei et al., “Universal HSPICE model for Chalcogenide based phase change memory elements,” IEEE Non-Volatile Memory Technology Symposium, 15-17, pp.88-91, Nov. 2004. 46
  47. 47. Memory module LOGO The memory module keeps VC unchanged unless temperature falls between Tx and Tm Input TPCM , VC Tx <= TPCM < Tm TPCM < Tx TPCM >= Tm && dVC >= 0 dt VMem VMem=VC VMem=0 Unchange Output VMem 47
  48. 48. LOGO Temperature-based PCM model Model structure Model implementation Model simulation results 48
  49. 49. Model simulation LOGO Ideal source testing DC analysis – PCM I-V characteristic Transient analysis – PCM R-I characteristic Current mirror source testing Current mirror Ip R1 = 2k (ohm) P P P Vpcm Iin Vin Iin Iin Ideal current source PCM + PCM PCM PCM Model Model Model model - N N N 49
  50. 50. Parameters LOGO Parameter Value Static resistance of Set, RSet 7kΩ Programming time of Set, TSet 10ns Static resistance of Reset, RReset 200kΩ Programming current of Reset, IReset 1200μA Programming time of Reset, TReset 200ns Dynamic-on resistance, Ron 1kΩ Threshold voltage, Vth 0.78V Holding voltage, Vh 0.45V Initial condition, IC 0 or 1 Environment temperature, Troom 300°K 50
  51. 51. DC analysis (1/2) LOGO 300 Iin P Rpcm=7k , Vc=1 PCM Model 250 Rpcm=26.3k , Vc=0.9 N Rpcm=84.2k , Vc=0.6 Rpcm=103.5k , Vc=0.5 200 Rpcm=130.52k , Vc=0.36 Current (μA) Rpcm=200k , Vc=0 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Voltage (V) 51
  52. 52. DC analysis (2/2) LOGO R1 = 2k (ohm) 300 Vin P Rpcm=7k , Vc=1 + PCM Model - Rpcm=26.3k , Vc=0.9 250 N Rpcm=84.2k , Vc=0.6 Rpcm=103.5k , Vc=0.5 200 Rpcm=130.52k , Vc=0.36 Current (μA) Rpcm=200k , Vc=0 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Voltage (V) 52
  53. 53. Transient analysis (1/2) LOGO Input the same pulse width but different amplitude. Pulse1 - 600μA / 100ns Pulse2 - 900μ A / 100ns Pulse3 - 1200μ A / 100ns 1400 250 1200 200 1000 800 Current (μA) Resistance (kΩ) 150 600 400 100 200 50 0 -200 0 0 200 400 600 800 0 200 400 600 800 Time (ns) Time (ns) 53
  54. 54. Transient analysis (2/2) LOGO 1E+6 Iin P 500ns 300ns PCM 200ns 100ns Model 80ns 50ns N 1E+5 Resistance (ohm) 1E+4 1E+6 1E+5 Resistance (ohm) 1E+3 1E+4 0 100 200 300 400 500 600 Current (μA) 1E+3 0 200 400 600 800 1000 1200 1400 Current (μA) 54
  55. 55. Current mirror source testing (1/2) LOGO 1800 Current mirror 1600 Iin Ip Ip Vpcm 1400 Iin Ideal current source 1200 PCM model 1000 Current (μA) 800 600 400 250 200 0 200 0 200 400 600 800 1000 1200 Time (ns) 150 Rpcm (kΩ) 100 50 0 0 200 400 600 800 1000 1200 Time (ns) 55
  56. 56. Current mirror source testing (2/2) LOGO 2.0 1.5 Vpcm (V) 1.0 2.0 250 0.5 Vpcm 1.5 Rpcm 200 0.0 0 200 400 600 800 1000 1200 Time (ns) 1.0 150 Vpcm (V) Rpcm (kΩ) Current mirror Ip 0.5 100 Vpcm Iin Ideal current source PCM 0.0 50 model -0.5 0 0 50 100 150 200 250 300 Time (ns) 56
  57. 57. Advanced application (1/3) LOGO We for the first time demonstrate that the same programming current amplitude can generate two states (Set and Reset) at only different pulse widths. Single pulse:1mA, 100ns (Amorphous programming) Multiple pulse:1mA, 5ns (Crystalline programming) 1200 1200 1000 1000 800 800 Current (μA) Current (μA) 600 600 400 400 200 200 0 0 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 Time (ns) Time (ns) 57
  58. 58. Advanced application (2/3) LOGO Single pulse 1050 950 1mA, 100ns 850 Temperature (°K) 750 650 550 450 350 1200 250 1000 0 20 40 60 80 100 120 140 160 180 200 Time (ns) 800 Current (μA) 600 0.10 400 Crystalline fraction 200 0 0.05 0 20 40 60 80 100 120 140 160 180 200 Time (ns) Amorphous 0.00 0 20 40 60 80 100 120 140 160 180 200 Time (ns) 58
  59. 59. Advanced application (3/3) LOGO Multiple pulse 1050 950 1mA, 5ns 850 Temperature (°K) 750 650 550 450 350 1200 250 1000 0 20 40 60 80 100 120 140 160 180 200 Time (ns) 800 Current (μA) 600 1.2 Crystalline 400 1.0 Crystalline fraction 200 0.8 0 0.6 0 20 40 60 80 100 120 140 160 180 200 Time (ns) 0.4 0.2 0.0 0 20 40 60 80 100 120 140 160 180 200 Time (ns) 59
  60. 60. LOGO Background Verilog-A ideal PCM model Temperature-based PCM model Conclusion and prospect 60
  61. 61. Conclusion and prospect LOGO We have presented a compact PCM model using Verilog-A. Ideal PCM model. Temperature-based PCM model. The model are predictive, yet simple to use and can be implemented in any circuit simulators with the Verilog-A option. 61
  62. 62. Conclusion and prospect LOGO PCM modeling with Verilog-A is flexible and has good convergence based on our simulation. Due to the physics based nature of the model, the model can be applied to non- conventional circuit design technique. Multi-level application. 62
  63. 63. 63

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