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Abhinav End Sem Presentation Software Defined Radio

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  • 1. Presented By Abhinav Kumar Tyagi M.Tech II Year IIT Kharagpur Under the Guidance of Prof R V Raja Kumar E&ECE Department, IIT Kharagpur
  • 2. CONTENTS
    • Introduction to Software Defined Radio
    • Ideal Architecture
    • Problems with Ideal Architecture implementation
    • Existing Software Defined Radio
    • Objective
    • Motivation
    • Work Done
    • Future Work
    • References
  • 3. Introduction to SDR
    • First introduced by J.Mitola in 1991
    • Refers to a technique in which all the processing is done in software
    • The processing mentioned include mixing, filtering, demodulation etc
    • The software can be used to implement different demodulation scheme and different standards can be implemented in the same device.
    • The software can be updated so the device doesn’t become obsolete with time.
  • 4. SDR EXPLAINED Software Defined Radio Hardware Radio
  • 5. IDEAL SDR Low Pass Filter Analog to Digital Converter Digital Signal Processor Antenna Block Diagram of Ideal SDR Receiver
  • 6. IDEAL SDR
    • High Frequency
    • Requires High Sampling Rate ADC
      • Costly, Power Hungry
    • High Speed Processor to Process High Sample Rate
      • Much Costly, Huge Power Consumption
    Thus a non feasible solution for commercial applications!
  • 7. PRACTICAL SDR ARCHITECTURE
    • Analog RF Front-End still required:
      • Digital-analog conversion, DAC/ADC
      • RF, IF Filtering
      • Mixing IF   RF
      • Amplification
      • Antennas
  • 8. EXISTING SDRs
    • TMDSSFFSDR, from Texas Instruments in 360-960 MHz range.
    • SDR-1000 from Flex-Radio System ; a commercial SDR; useful for amateur radio operators; 12KHz to 60MHz.
    • SDR-3000 & SDR-4000 from FlexComm , useful for tactical military communication system.
  • 9. MULTI MODE RADIO GSM Chipset CDMA chipset Processor Software Hardware Most of Mobile phone that work in more than one standards are based on this principle
  • 10. OBJECTIVE OF THE PROJECT
    • To develop a ‘Single Wideband’ RF Front end from 400MHz to 3.4 GHz.
    • This will cover all the existing/future standards like
      • GSM 850/900/1800, IS95, IS136, UMTS, WiFi, Wimax etc.
    • The design should have low cost and power efficient
      • Targets on reconfigurability and reusability.
    • No Single Wideband solution been reported till now!
  • 11. Motivation
    • The project involves development of complete system as a whole.
    • SDR is an emerging technology
    • It is very promising. SDR aims at
      • Providing multifunctionality to same device.
      • It supports Global Mobility
      • Ensures Compactness and Power Efficiency
      • Upgrades are easy with update of software
      • Evolution of new standards doesn’t make the device obsolete when compared to conventional multimode radios.
  • 12. WORK DONE
  • 13. Architecture of RF Front End Digital to Analog Converter DAC5687 Baseband Processor Baseband Processor Analog to Digital Converter ADC08200 ADC08200 ADC8369 ADC8369 AD 8347 MGA665P8 TRF3761 FREQUENCY SYNTHESIZER I/Q MODULATOR TRF3703 MwT-17Q3 RF Front End Baseband Section Architecture of RF Front End Tx Ant Rx Ant
  • 14. WORK DONE …
    • Study of basic receiver architectures
    • Study of TRF3761 Frequency Synthesizer Chip
    • Calculation of data words for programming TRF3761
    • Filter Design for Phased Lock Loop
    • Frequency Synthesizer PCB designed
    • Design of hardware required to program the chip
    • Testing of frequency synthesizer and reference oscillator
    • Non Linear modeling of LNA and Mixer
  • 15. Receiver Architectures
    • The basic receiver architectures are
      • Hetrodyne Receiver
      • Direct Conversion Receiver
      • Low IF Receiver
  • 16. Direct Conversion Receiver LO frequency is equal to RF carrier frequency Converts RF signal to Zero frequency and hence called as Zero IF Receiver Simple Low Pass filter is used Image reject filter is not required Well suited for integration whole receiver ON-CHIP.
  • 17. Low IF receiver
    • LO frequency is slightly different from RF carrier frequency.
    • Converts RF Signal to a very low IF frequency near to dc.
    • Have advantages of both Zero IF and Hetrodyne architectures but requires image reject mixer which is quite challenging for wideband applications
    • Less popular compared to Zero IF Architecture.
  • 18. Superhetrodyne Receiver
    • Converts RF signal to lower IF signal
    • Requires additional intermediate stages such as IF filter
    • Consumes more power
    • High Q IF filter are bulky compared to simple LPF for direct conversion type
    • Least popular architecture for On Chip solution
  • 19. Study of TRF3761 Frequency Synthesizer Block Diagram
  • 20. Application Schematic
  • 21. Layout
  • 22. Assembled Board Top and Bottom Side of Frequency synthesizer board with components mounted
  • 23. Output
    • Output of 20 MHz Reference Oscillator
  • 24.
    • Frequency Synthesizer Output
  • 25. Modeling of LNA and Mixer
    • Non Linear models of LNA and Mixer developed for the calculation of Intermodulation Products arising due to Simultaneous transmissions of two carriers.
  • 26. LNA Modeling
    • The current can be expressed as
    • I (v) = c 0 + c 1 V + c 2 V 2 +c 3 V 3
    • Where V=A (Cos (w1t) + Cos (w2t)) represents input signal
    • DC and fundamental terms amplitude is given by
    • [c 0 + c 2 A 2 ]+ [ c 1 A + (9/4)c 3 A 3 ] [Cos (w1t) + Cos (w2t)] … (E1)
    • Third order intermodulation terms are given as
    • (3/4 c 3 A 3 ) [Cos (w1+2w2) t + Cos (w1-2w2) t
    • + Cos (2w1+w2) t + Cos (2w1-w2) t] …. (E2) _
    • Since w1 and w2 are closer, 2w1-w2 and 2w2-w1 lies closer to w1 and w2
  • 27.
    • Equation E1 Shows gain compression with increase in level of input signal and is characterized by 1 dB compression point.
    • Equation E2 shows that 3 rd order distortion increases as cube of amplitude of the applied signal or 3 times in dB. The amplitude of input signal where IMD and Desired signal are equal is known as IIP3 or Input referred third order intercept point.
  • 28.
    • using IIP3 and P1dB data, the model is extracted for MGA665P8 from Avago Technologies.
    • y = 5.3088 Vin-16.882 V 3 ;
    • The model is implemented in Matlab
  • 29. Modeling of Mixer
    • The mixer is a non linear device and can be represented by a non linear polynomial of fourth degree to consider up to 3rd order IMD
    • The coefficients c i for above can be calculated by analyzing the output for known signal. The parameters taken into consideration to compute the model include LO to IF leakage, RF to IF leakage, Third order intercept point IIP3 and Conversion Loss.
    • The values of c1, c2, c3, c4 are respectively 0.15263, 0.9142, -0.6, 0.0077
    • The mixer is implemented in Matlab.
    • LNA and Mixer stages are cascaded and the output at each stage is shown.
  • 30. Output Obtained from Non Linear Models of LNA & Mixer
    • Considering two transmissions received at 935, 935.2 MHz with
    • -25 dBm level of each signal
  • 31. LNA Input Two Signals at 935 & 935.2 MHZ, -25 dBm each.
  • 32. Output of LNA The Intermodulation products are observed at 934.8 and 935.2 MHz
  • 33. Output of Mixer
  • 34. Considering GSM and WiFi transmission from 1805-1890 MHz and 2400-2420 MHz , the signal at different stages is shown in figure
    • F(MHz)
    P,dBm)
  • 35. LNA Output F(MHz) P,dBm)
  • 36. LNA Output (expanded) F(MHZ ) F(MHZ ) P,dBm) P,dBm)
  • 37. Mixer Output 1 Down converted GSM Signal 2 Down converted WiFi Signal 1 2 3 Third Order Intermodulation Products of WiFi and LO 3 4 Third order intermodulation product of LO and GSM signal along with RF to IF leakage 4 5 RF to IF leakage of WiFi 5 6,7 Upconverted GSM and WiFi Signals 6 7
  • 38. Future Work
    • The RF band from 400 MHz to 3.4 GHz is to be partitioned into different sub bands to avoid intermodulation products arising from mixing. Major concern is third order intermodulation products.
    • Types of filters to be used: Wideband RF filter or narrowband tunable filters is to be examined for suitability and compact size implementation.
    • RF switches used for switching modules for the above mentioned bands is to be done.
    • The frequency synthesizer hardware is to be finalized.
    • Wideband matching of LNA is to be done over whole band.
    • Analysis and implementation of other subsystems of the receiver and finally combining all the modules for final receiver system.
  • 39. References
    • [1] J Mitola, "The Software Radio," IEEE National Telesystems Conference, 1992.
    • [2]Shruti Shrivastava, “Design of a Wideband RF Front–End for Software Defined Radio,” M Tech Thesis, 2008, E&ECE Department, IIT Kharagpur.
    • [3]J.J. Spilker, “Digital Communication by satellite”, Prentice Hall Inc., Englewood cliffs, New Jersey.
    • [4] T.H. Lee, “The Design of CMOS RF Integrated Circuits”, Cambridge University Press, 1998
  • 40. Contd…
    • [5]TRF3761 Datasheet, Integer-N PLL with integrated VCO, Texas Instruments Inc.
    • [6] ADL5350 Datasheet, LF to 4GHz High Linearity Mixer, Analog Devices Inc.
    • [7] MGA665P8 Low noise amplifier Data Sheet, Avago Technologies.
  • 41.
    • THANKS

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