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Sofics, experts in ESD on chip protection

Sofics, experts in ESD on chip protection

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  • 1. SOFICSformerly known as Sarnoff Europe
    July 2009
    Pieter Donck
  • 2. TakeCharge used by >30 customers and licensees
    IDM – Fabless – Foundry partners
    Sofics © 2009
    Proprietary & Confidential
    2
  • 3. TakeCharge ESD implemented in >500 ICs
    TakeCharge milestones
    Since 2002: >500 volume production ICs reported
    Product proven in 8 CMOS generations, BiCMOS, BCD…
    Partnerships with major and specialty foundries
    July 2008: 40nm ESD solutions validated in silicon
    Sofics © 2009
    Proprietary & Confidential
    3
  • 4. TakeCharge complements ESD portfolio
    TakeCharge: complementary solutions
    Augment available portfolio
    Focus on custom or specialty requirements
    High speed applications
    Low leakage for green/mobile applications
    High ESD performance requirements
    Special analog requirements
    Small silicon area clamps
    Full chip implementation support
    Sofics © 2009
    Proprietary & Confidential
    4
    Standard logic
    ESD-circuit matching
    Low capacitance
    High ESD requirement
    Interdomain / core issues
  • 5. TakeCharge Engagement models
    ESD test service
    ESD analysis or qualification for your ASIC
    ESD consulting service
    Solve ESD issues, increase ESD confidence, quickly!
    TakeCharge Design Kits (TDK)
    Comprehensive solution set for 180nm – 40nm
    Optimize ESD independently from SOFICS.
    TakeCharge Technology transfer
    Consistently realize first-time-right, optimized, robust ESD design
    Independently migrate ESD solutions to multiple processes
    Sofics © 2009
    Proprietary & Confidential
    5
  • 6. TakeCharge ServiceESD TEST SERVICE
    Sofics © 2009
    Proprietary & Confidential
    6
  • 7. SOFICS has a state-of-the-art ESD lab
    Fully equipped ESD test lab
    HBM ANSI/ESDA and JEDEC on packaged dies
    MM ANSI/ESDA and JEDEC on packaged dies
    Latch-up JEDEC on packaged dies
    TLP (2) on packaged and bare dies
    VF-TLP on bare dies with high current RF probes
    Probe stations (3)
    DC leakage and IV tracing on packaged and bare dies
    Solid state pulsing on packaged and bare dies
    Thermo chuck
    Test boards and sockets for various packages
    Sofics © 2009
    Proprietary & Confidential
    7
  • 8. ESD test equipment
    ESD related equipment
    HBM, MM, latch-up: Keytek Mk.2
    TLP: BEI 4002 TLP: 75ns and 100ns pulse width
    VF-TLP: BEI 4012 VF-TLP: 1 ns, 2ns, 5ns, 10ns pulse width
    DC / latch-up equipment
    Parametric analyzer: Keithley 4200
    Curve tracer: Tektronix Type 576
    High temperature Micromanipulator
    Sofics © 2009
    Proprietary & Confidential
    8
  • 9. ESD, DC Analysis
    TLP, VFTLP, DC (parametric, curve tracer)
    Wafer or bare dies
    ESD Qualification
    HBM, MM, TLP, Latch-up
    Packaged samples
    DIL16 - DIL48
    QFP208
    Sofics © 2009
    Proprietary & Confidential
    9
  • 10. TakeCharge cells
    Sofics © 2009
    Proprietary & Confidential
    10
  • 11. TDK cells – Product proven ESD clamps
    Approach
    Purchase selected ESD clamps
    Single clamp or single voltage domain
    GDSII layout file, LVS netlist
    1 page description (connection guidelines, ESD behavior)
    Dual diode included for ‘domain’ purchases
    Customization services available
    Increase ESD performance
    Change metallization
    Change aspect ratio
    Cells for custom requirements available on request
    Customer integrates ESD clamps
    Implementation review services available
    Sofics © 2009
    Proprietary & Confidential
    11
  • 12. TDK ESD cells for foundry processes
    Silicon and product verified ESD clamps:
    TSMC
    350nm HV – 180nm – 130nm – 90nm – 65nm – 40nm
    UMC
    180nm HV – 130nm – 65nm
    Tower
    130nm – 350nm
    Other
    Fujitsu 65nm – Epson 130nm
    Chartered 65nm: qualification on-going
    Various other cells available
    Other voltage domains, process nodes, or foundries
    Sofics © 2009
    Proprietary & Confidential
    12
  • 13. TDK cells – Topology / clamp types
    Clamp types available
    Core protection
    IO clamps
    Input protection
    Output protection
    IO protection
    Special cells
    Low capacitive
    Overvoltage tolerant (OVT)
    Area information
    Includes guard bands and reverse diode
    ‘Both directions’ includes 2 local clamps and dual diode
    Sofics © 2009
    Proprietary & Confidential
    13
    VDD
    IO
    Circuit
    PAD
    RISO
    IO
    Circuit
    VSS
  • 14. Key benefits with TakeCharge solutions
    Key technical benefits
    Area efficient solutions
    Win business, volume and margins
    Scalable ESD performance
    Reach any ESD requirement
    Low leakage and Latch-up immune
    No interruption of normal operation
    Tunable trigger voltage and current
    Complete solution package.
    Protection of Analog IO’s
    No process changes for ESD solutions
    ‘Over voltage’ and ‘under voltage’ tolerant options
    Optimization through calculation tool
    Sofics © 2009
    Proprietary & Confidential
    14
  • 15. Calculation tool
    Sofics © 2009
    Proprietary & Confidential
    15
  • 16. Straightforward path to optimized ESD solutions
    TakeCharge ESD calculation tool
    Clear visualization & navigation
    Design guidance
    Automatic w/ pre-selections
    Design window calculation(any circuit-to-be-protected)
    Performance check
    Design optimization
    Full IC consideration
    Trade offs
    Capacitance, area, leakage,bus resistance…
    Sofics © 2009
    Proprietary & Confidential
    16
  • 17. Calculation tool
    Growing difficulty for ESD protection
    Advanced CMOS, Complex System-on-Chip designs
    Beyond standard ESD requirements
    Analog design requirements (capacitance, leakage)
    Solutions: ESD design tool
    Step-wise, easy to use GUI
    Easily compare different protection strategies
    Optimize functional – ESD trade-offs
    Based on on-Chip ESD IP blocks
    Customized per technology node and foundry
    Silicon proven IP in 8 CMOS generations and >500 IC’s
    Sofics © 2009
    Proprietary & Confidential
    17
  • 18. Advanced CMOS
    Sofics © 2009
    Proprietary & Confidential
    18
  • 19. TakeCharge – experience in advanced CMOS
    SOFICS experience in advanced IC applications
    SerDes IO’s in FPGA’s: 180nm – 40nm
    10Gbps Optical communications: 130nm – 180nm
    HDMI: 130nm
    USB 2.0: 130nm – 90nm
    Serial ATA: 130nm – 90nm
    ASICs: 180nm – 65nm
    ...
    Sofics © 2009
    Proprietary & Confidential
    19
  • 20. TakeCharge – flexible ESD solutions
    TakeCharge ESD protection
    Tunable trigger voltage Vt1
    External, exchangable trigger elements
    Tunable holding voltage Vhold
    Latch-up immunity
    Tunable failure current It2, Imax
    Any ESD specification possible
    Low dynamic resistance Ron
    Design margin for full chip ESD
    Low capacitive
    For high speed IOs
    Low leakage
    Sofics © 2009
    Proprietary & Confidential
    20
    Current
    Vdd
    Vmax
    Vburn-in
    It2
    Imax
    Damage
    of
    IO
    or core
    RON
    Voltage
    Vhold
    Vt1
  • 21. Universal power clamp
    Sofics © 2009
    Proprietary & Confidential
    21
  • 22. ESD protection for High Voltage applications
    Various ESD protection clamps in use (overview 1/2)
    HV NMOS: RC-BigFet
    Large silicon area, high leakage
    Tuning is difficult for high voltage processes
    HV NMOS bipolar: double snapback
    Low ESD robustness – non-uniform ESD current conduction & degradation
    Large silicon area, high leakage
    Latch-up due to deep snapback
    HV PMOS bipolar: no snapback
    Large silicon area, high leakage
    Limited portability between fabs and processes
    Large voltage drop during ESD stress
    Sofics © 2009
    Proprietary & Confidential
    22
  • 23. ESD protection for High Voltage applications
    Various ESD protection clamps in use (overview 2/2)
    Zener diode: reverse diode conduction
    Large silicon area, high leakage
    Large voltage drop during ESD stress
    High BD voltage – small margin for core protection
    HHI-SCR: SOFICS proprietary
    High ESD robustness in smallest area
    Tunable trigger conditions (Vt1, It1, Ihold)
    Latch-up free up-to predefined current level
    Universal HV power clamp: SOFICS proprietary
    High ESD robustness in smallest area
    Tunable device for triggering and clamping
    Latch-up immune for all current levels
    Sofics © 2009
    Proprietary & Confidential
    23
    AREA COMPARISON
    Zener100%
    PMOS50%
    SOFICS10%
    - HHI-SCR
    - Universal HV clamp
  • 24. Contact Us
    TakeCharge Technology
    Bart Keppens bkeppens@sofics.com
    Benjamin Van Camp bvancamp@sofics.com
    TakeCharge Business
    Pieter Donck pdonck@sofics.com
    Koen Verhaege kverhaege@sofics.com
    Sofics
    Brugsebaan 188A, B-8470 Gistel, BELGIUM
    (tel) +32-59-275-915, (fax) +32-59-275-916
    www.sofics.com
    Sofics © 2009
    Proprietary & Confidential
    24