566 Chapter 22
An external device activates the master request signal MREQ to take over control of the EISA Together with its new generation of PCs, the PS/2, IBM also implemented a new bus system
bus as a busmaster. The system arbitrator detects MREQ and passes control if no other master and a new PC architecture, the MicroChannel In view of its geometry as well as Its logical
is active. Normally, the CPU on the motherboard is the active busmaster. concept, this bus is a radical departure from the AT bus, which had been very successful up
until that time. Hardware compatibility to previous PC models is no longer kept, but there are
MSBURST some good reasons for this: the AT bus was only designed for 16-bit processors, but the new
Terminal E9 1386 and I486 CPUs run with 32 bits. Furthermore, because of its edge triggered interrupts, the
AT bus is directed to singletasking operating systems such as DOS. The aim when designing the
An EISA master activates the master burst signal MSBURST to inform the EISA bus controller PS/2, on the other hand, was to go over to multitasking systems, particularly OS/2. Therefore,
that the master can carry out the next bus cycle as a burst cycle. The bus transfer rate is thus the problems are similar to those already mentioned in connection with EISA. It Is also inter-
doubled. This is particularly advantageous for cache line fills and DMA transfers. esting that the microchannel was presented much earlier than EISA. EISA was supposedly
designed as a reaction to the microchannel, so as not to leave the 32-bit market all to IBM.
SLBURST Identical problems often lead to similar solutions, thus it is perhaps not surprising that the
Terminal E8 microchannel (apart from the completely Incompatible bus slot) does not differ radically from
An EISA slave activates the slave burst signal SLBURST to inform the bus controller that it can EISA. After all, at the operating system level, and especially at the application level, complete
follow a burst cycle. Typical EISA slaves that activate SLBURST are fast 32-bit main memories. compatibility with the AT must be achieved. Programs that do not explicitly refer to the hard-
ware registers also run on the PS/2 without any problems, and with no noticeable difference for
STAET the users.
This signal serves for clock signal coordination at the beginning of an EISA bus cycle. START
indicates the beginning of a cycle on the local bus.
Figure 231 shows a schematic block diagram of the microchannel architecture (MCA). A signifi-
W/R cant difference from EISA is the separate system clock which supplies a frequency of 10 MHz
Terminal E10 at most for all microchannel components. Only the local bus between the CPU and the memory
The signal serves to distinguish write and read EISA bus cycles. operates faster to carry out data accesses, of the CPU to main memory at a maximum speed.
Thus the microchannel is an asynchronous bus system; the CPU is clocked by Its own CPU clock.
The microchannel was Initially introduced with three different bus cycles:
D32-D63 (I/O; corresponding to BED, BE1, LA2-LA31)
Terminals C2-C8, E17-E18, E2Q-E23, E26^E29, E31, F18, F21, F23-F24, F26-F27, F31, Gl, G3-G4, - standard bus cycle,
H1-H3, H5 - synchronous extended bus cycle, and
- asynchronous extended bus cycle.
In an enhanced master burst the 30 address terminals LA2-LA31 and the two byte enable
terminals BEO and BE1 transfer the 32 high-order data bits of a 64-bit data quantity. The standard bus cycle corresponds to a conventional CPU bus cycle at 10 MHz with no wait
cycles. In an extended bus cycle the device addressed inserts wait states by means of the CHRDY
All other contacts are reserved (res), are grounded (GND), or transfer supply voltages for chips signal If CHRDY becomes active synchronous to the data half-cycle of the MCA bus cycle, this
(+5 V, -5 V) and Interfaces or drives (+12 V, -12 V).
is called a synchronous extended bus cycle, otherwise It is an asynchronous extended bus cycle.
CHRDY refers to the bus clock of 10 MHz but not to the CPU clock, which may be much higher,
especially with 1386 or i486 processors. Because of their high clock rates, 1386 and i486 always
insert several CPU wait cycles which are controlled by the bus controller using the READY
processor signal. One MCA bus cycle without wait cycles lasts for two bus clock cycles with
100 ns each. Thus the microchannel Is presently conceived for a maximum data transfer rate of
20 Mbytes/s. The data transfer rate can be slightly increased by the so-called matched-memory cycles.
These are only implemented with the 16 MHz model 80, and are controlled by the MMC and
MMCR signals. To carry out a matched-memory cycle the bus controller of the motherboard
32-bit MicroChannel - Revolution 569
System 10 MHz max.
are transferred within a single MCA bus clock cycle. Using this the data transfer rate Increases
Clock to 40 Mbytes/s for a short time. This Is even more than the 33 Mbytes/s for the EISA burst
CPU A further enhancement is possible with the. 64-bit SDP. Here, only during the first bus cycle Is
Interrupt the address output. The addressed device accepts and stores It. Afterwards, the data Is trans-
ferred not only via the 32-bit data bus, but also via the 32-bit address bus, that is, with a width
Bus Arbiter Parallel of 64 bits or 8 bytes in total. The device addressed comprises an address counter that counts up
with each 64-bit iSDP automatically. It therefore only needs the start address. With the 64-bit
Timer VGA SDP a data transfer rate of 80 Mbytes/s can be achieved. The extended 64-bit SDP is even more
powerful. Here the bus cycle is reduced from 100 ns down to 50 ns, but the transfer itself is
NMI Logic Auxiliary Serial identical to that of a normal 64-bit SDP. The data transfer rate doubles to 160 Mbytes/s, that is,
DRAy Interface Interface
Control a medium-sized hard disk could be read within one second.
Bus Buffer If 232 Bus Arbitration
MCA Bus Like EISA, the MCA also supports external busmasters on adapter cards. Including the CPU, up
Controller to 16 different busmasters can be Integrated. For this purpose, IBM implemented a dedicated
chip, the so-called central arbitration control point (CACP), which carries out the bus arbitration
and passes control to a busmaster. With the MCA the motherboard's CPU, the refresh logic, the
MicroChannel DMA controller and external busmasters on adapter cards can operate as busmasters. Table 23.1
shows the priorities assigned to these busmasters.
Figure 23.1: The MCA architecture.
activates the MMC (matched-memory cycle) signal If the addressed device responds with an -2d memory refresh
active JvfMCR (matched-memory cycle return), the bus controller shortens the cycle time of the -1d NMI
MCA bus clock to 93.75 ns. ADL and CMD are not generated here, but MMCCMD is. Because OOh D M A channel 0 * }
of the shorter cycle time, a data transfer rate of at most 21.4 Mbytes/s is possible; this is an •01 h D M A channel
02h D M A channel
incredible increase of 7%.
03h D M A channel
04h D M A channel 0*>
No wonder, then, that IBM mothballed the matched-memory cycle, and developed the streaming 05h D M A channel
data procedure (SDP) concept. Presently, three such SDPs have been designed: 06h D M A channel
- 32-bit SDP, 07h D M A channel
08h available for external busmaster
- 64~bit SDP, and
09h available for external busmaster
- extended 64-bit SDP. Oah available for external busmaster
Obh available for external busmaster
IBM uses the microchannel not only in its PS/2 series but also in much more powerful RISC Och available for external busmaster
System/6000 workstations with a basis of RISC processors with the POWER architecture (Per- Odh available for external busmaster
formance Optimization With Enhanced RISC). Oeh available for external busmaster
Ofh CPU on the motherboard
In view of the signal course, the 32-bit SDP coincides with the I486 burst mode. To request a
32-bit SDP the busmaster deactivates the BLAST signal. The device addressed responds with a *' Priority can be programmed freely.
BRDY to indicate that it is able to carry out 32-bit burst mode. With the 32-bit SDP four bytes
Table 23.1: Arbitration priorities in the PS/2
Chapter 23 32-bit MicroChannel - Revolution 571
The -2 priority of the memory refresh means that the arbitration logic always passes control of If the busmaster does not release control after 7.8 us, the CACP Interprets this as a malfunction*
the bus if a refresh Is requested. The memory refresh is located on the motherboard and drives It disconnects the busmaster from the bus, passes control to the CPU, and issues an NML
the arbitration logic by an internal refresh request signal. The next lower priority, - 1 , of the NMl
Is also processed internally. The source of an NMI is usually an error on an adapter card, a time- The CACP can be programmed via the arbitration register at I/O address 090h (Figure 23.2).
out In connection with bus arbitration, or another serious malfunction. The NMI may only be
serviced by the CPU on the motherboard. However, for this the CPU needs to be In control of
5 4 3 2 1 0
the system bus, because the program code of the accompanying Interrupt handler 2 must be O
read from memory. Therefore, an NMI always forces the CACP to snatch away the system bus
from another active busmaster, and to pass control to the CPU.
}xPC: CPU cycles during arbitration cycle
The lowest priority Ofh of the CPU means that the CPU on the motherboard is always In control 1 =yes 0=no (standard)
of the system bus if no other busmaster requests bus control No arbitration signal line is MAS: mask
necessary for this. Instead, the CACP automatically assigns the CPU control by means of the 1 =ARB//GNT always high 0=normal arbitration
HOLD and HLDA processor signals, in this case. EXT: extended arbitration cycle
All other busmasters can request control of the bus via the PREEMPT signal Then, by means PC4-PC0: reading=priority code of the busmaster that won the last arbitration
of ARB0-ARB3, the bus arbitration passes control to one of the requesting busmasters according writing=not defined, always equal 0
to a strategy using a largely equal treatment. For this, the following steps are carried out:
Figure 232: Arbitration register (Port 090h).
- The busmasters that want to take over control of the system bus set PREEMPT to a low
If you set bit uPC equal to 1, the CPU on the motherboard executes further bus cycles, for
- The CACP activates ARB/ GNT to indicate that an arbitration cycle Is In progress. example to fetch instructions while the CACP carries out an arbitration cycle. For the bus
- Each of the requesting busmasters outputs its priority code via ARBG-ARB3, and compares arbitration only the lines PREEMPT and ARB0-ARB3 are required, which are not used during
Its code with the code on ARB0-ARB3, which consists of the priority code of all the request- a CPU bus cycle. Therefore, the two cycles do not affect each other. If MAS Is set the CACP
always drives the ARB /GNT signal high, that is, always Indicates an arbitration cycle. As long
- If Its priority code Is lower then It deactivates Its code on ARB0-ARB3 and rules itself out as MAS is set, only the CPU is In control of the system bus, and all other busmasters are locked
of the competition, but continues to drive PREEMPT to indicate that it wants to take over out. By means of EXT, the arbitration cycle can be enhanced from the standard 300 ns up to
control in a later arbitration cycle.
600 ns. This is' advantageous if slow devices are present in the system. Finally, the five bits
- After a certain time period (in the PS/2 300 ns are usually available for this purpose), only PC4-PC0 indicate the priority code of the device that last won the bus arbitration. When writing
the highest priority code is still present on ARB0-ARB3. into the register, bits PC4-PC0 have no meaning and should always be set equal to 0.
~ The CACP pulls ARB/GNT down to a low level to Indicate that the bus control has passed
to a new busmaster (GNT = grant) whose priority code Is present on ARB0-ARB3.
- The new busmaster deactivates Its PREEMPT signal. All other busmasters which were unable 233 Memory System
to take over control continue to drive PREEMPT to a low level
- Now the new busmaster can control the bus for one bus cycle. The PS/2 memory system has also been improved with the development of the microchannel.
- Burst busmasters that want to transfer a whole data block and are allowed to keep control If the startup routine of the PC detects a defect in main memory, the memory is reconfigured
of the system bus for at most 7.8 us (the maximum allocation time for external busmasters) in 64 kbyte blocks so that eventually a continuous and error-free main memory again becomes
are an exception to this rule. Such busmasters activate the BURST signal to Inform the CACP available. The block with the defect is logically moved to the upper end of the main memory
that an arbitration cycle shall not be carried out for every bus cycle. But if PREEMPT or a and locked against access. If such a defect occurs in the lower address area in an AT, the whole
refresh request is active, an arbitration cycle is executed nevertheless. Thus, BURST only has of the main memory from the defective address upwards becomes unusable.
an effect if the current burst busmaster is the only one requesting control of the system bus.
- Afterwards, the CACP releases control to the CPU or starts a further arbitration cycle if For the PS/2 models 70 and 80, two memory configuration registers at the port addresses eOh
PREEMPT Is driven low by another busmaster. and elh are additionally available. Using these ports, the division of the first Mbyte in RAM can
be controlled so that, for example, the ROM BIOS is moved into the faster RAM (shadowing),
Every busmaster adapter has a local bus arbitrator which drives the adapter card's PREEMPT and or the memory is divided to be as RAM-saving as possible (split-memory option). These pos-
ARB0-ARB3, and compares the priority code of the busmaster adapter with the overall code
ARB0™ARB3. sibilities are not discussed here in detail because these setups can usually be done with the help
of the extended PS/2 setup during the course of the boot process.
Chapter 23 32-bit MicroChannel - Revolution
23.4 crashing the PC because of too few refresh cycles. Programmers can access the timer via port
041h, but passing new values doesn't have any effect on its behaviour.
In terms of their functions, the microchannel's support chips differ very little from their EISA
counterparts, but they are completely harmonized with this new and advanced bus system.
Thus, for example, the DMA controller always carries out a 32-bit DMA transfer for the com- 23.7 I/O Ports and I/O Address Space
plete address space if a 32-bit microchannel is present. There Is no 8237A-compatible DMA
transfer. Moreover, the microchannel architecture allows all eight DMA channels to be active As for EISA, in the PS/2 the support and controller chips are also accessed via ports. Table 23.2
simultaneously. Thus, MCA Is really well suited for multitasking operating systems. lists the new I/O address areas for MCA. Unlike ISA, the MCA slots, and therefore also the
inserted MCA adapters, can be addressed Individually. To do this, however, you must explicitly
Originally, in the PS/2 only a 16-bit DMA controller was Intended, which could only serve the activate a slot for a setup. This is necessary to configure MCA adapters with no DIP switches
first 16 Mbytes of memory. Here again you can see the enormously fast development in the field automatically.
of microelectronics. Although the microchannel and the PS/2 were intended as a new standard
to replace the AT and last for years, the 16 Mbytes (which seemed astronomically large a few
years ago) are no longer enough, since memory-eaters like OS/2 and Windows have appeared.
Modern motherboards can usually be equipped with 128 Mbytes of memory. 000h-01fh master DMA
020h-021h master 8259A
040h-043h timer 1
044h-047h failsafe timer
060h-064h keyboard/mouse controller
070h-071h real-time clock/CMOS RAM
As well as the bus system and the DMA controller, the interrupt controller was also harmonized 074h-076h extended CMOS RAM
with the new architecture. All interrupts are level-trigger invoked only. With EISA, on the other 080h-08fh DMA page register
hand, Interrupts can be level- or edge-triggered so that an ISA adapter can be operated as the 090h CACP
091 h feedback register
serial interface adapter, which operates exclusively with edge-triggering in an EISA slot. Be- 092h system control port A
cause of the level-triggering used in MCA, various sources can share one interrupt line IRCx. 096h adapter activation/setup register
Additionally, level-triggering is less susceptible to interference, as a noise pulse only leads to a OaOh-Oafh slave 8259A
very short voltage rise but level-triggering requires a lasting high level. For the microchannel, OcOh-Odfh slave DMA
255 different hardware interrupts are possible; the AT allows only 15. The assignment of the OeOh-Oefh memory configuration register
IRQ lines and the correspondence of hardware interrupt and Interrupt vector coincides with
100h-107h POS registers 0 to 7
that In the AT and EISA. 200h-20fh game adapter
Failsafe Timer 278h-27fh 2nd parallel interface
The MCA times comprises four channels in total, and is equivalent to an 8254 chip with four 300h-31fh prototype adapter
counters. The first three channels 0-2 are occupied by the internal system clock, memory refresh 320h-32fh available
and tone generation for the speaker, as Is the case In the AT. The fourth timer Is used as a 378h-37fh 1st parallel interface
380h-38fh SDLC adapter
failsafe or watchdog timer In the same sense as for EISA. It issues an NMI If a certain time
period has elapsed, thus preventing an external busmaster from keeping control too long and 3b0h-3b3h monochrome adapter
blocking necessary interrupts or the memory refresh. If an external busmaster retains control of 3b4h-3bah VGA
the MCA bus for too long, and thereby violates the bus arbitration rules, this Indicates a hard- 3bch-3beh parallel interface
ware error or the crash of an external busmaster. Then the failsafe timer Issues an NMI and the 3c0h-3dfh EGA/VAG
arbitration logic releases control to the CPU again so that it can handle the NMI. 3e0h-3e7h reserved
3f0h-3f7h floppy controller
On the PC/XT/AT, timer 1 for memory refresh Is programmable, but on the PS/2 It is not. IBM
thus wants to avoid nosy users who like to experiment with changing the refresh rate and Table 232: MCA port addresses
574 Chapter 23 32-bit MicroChannel - Revolution 575
M POS register Bit Meaning .
2 0 adapter enable
There Is also a significant advantage here compared to the old AT concept that of the automatic status for channel check available
identification of an adapter by the system, MicroChannel adapters, like their EISA counterparts 7 channel check active
are no longer configured by jumpers. This can Instead be carried out In a dialogue with the
accompanying system software. For this purpose, IBM assigns every adapter an Identification Table 23.4: Reserved POS register bits
number which can be read and analysed by the system. Also, third-party manufacturers get an
identification number for their MCA products which is centrally managed by IBM, The configu- the adapter also sets bit 6 to a value of 0. The remaining bits are freely available for Implement-
ration information is stored in an extended CMOS RAM (as is the case with EISA). Additionally, ing software option switches which replace the previous DIP switches.
you may activate or disable Individual MCA slots, thus a defective or suspicious adapter can The POS registers are present at the same address on all adapters and the motherboard, thus
be disabled until the maintenance technician arrives, without the need to open the PC and access conflicts seem to be preprogrammed. To avoid this, two additional registers are Imple-
remove the adapter. This also allows you to operate two adapters alternately, which normally mented, the adapter activation/setup register at I/O address 096h, and the motherboard acti-
disturb each other, without pottering around the PC all the time, vation/setup register at I/O address 094k
To achieve these advantages, all MCA adapters and the MCA motherboard hold so-called Each adapter can be operated in two different modes:
programmable option select (POS) registers. They always occupy the I/O address area OlOOh to
0107h. Table 233 lists the registers. - Active mode: the POS registers are not accessible and the adapter is operating normally. You
may access the ordinary control registers (the DAC colour register on a VGA, for example).
- Setup mode: here only the POS registers are accessible, not the ordinary control registers.
Number 3/0 address IVieariii/ig
Using the adapter activation/setup register you may activate a slot and thus an adapter well-
0 OlOOh adapter identification ID (low-byte) suited for setup of and access to Its POS registers. Figure 23.3 shows the assignment of this
1 0101 h adapter identification ID (high-byte)
2 0102h option byte 1
3 0103h option byte 2
4 0104h option byte 3 7 6 5 4 3 2 1 0
5 0105h option byte 4 |o:| I i H- < N | ^ I o U
sub-address extension (low-byte)
sub-address extension (high-byte)
g 1 Reserved CO
CHR: channel reset
Table 233: POS registers
0=no reset 1 =reset all adapters
res: reserved (=0)
SET: adapter setup
During the boot process the POST routine of the BIOS reads the adapter Identification ID and
0=normal mode 1 =setup mode
compares it with the configuration data which is held In the CMOS RAM. The adapter Identi- SL2-SL0: adapter/slot select
fication ID Is awarded centrally by IBM, that is, IBM assigns every manufacturer of an MCA 000=slot1 001=slot2 010=s!ot3 111=SlOt 8
adapter such a number for the product concerned. The four option bytes are available for
the adapter manufacturer to configure the Inserted adapter and thus fulfil the functions of the Figure 23.3: Adapter activation/setup register (port 096h).
former DIP switches. If the four option bytes are Insufficient, the manufacturer may implement
an additional configuration register on the adapter card. They are accessed by means of the two The three least-significant bits define the selected slot or adapter. A set adapter setup bit activates
sub-address extension registers. this adapter for a setup. The CDSETUP signal for a slot n is thus activated, and the adapter is
ready for a setup.
Three bits In the POS registers are predefined, and are listed in Table 23.4. By means of the bit
adapter activation In the POS register 2, the adapter concerned can be disabled or activated. If it Example: Activate adapter in slot 3 (note: the slots are enumerated 1 to 8 but the slot
selection with 0 to 7 ) .
is disabled the system behaves as if the adapter were not present. Therefore It is possible, for
example, alternately to operate two different graphics adapters with overlapping address areas MOV al, 0000 1010b ; slot select=2, setup active
In a PS/2. Their addresses do not then disturb each other. If a hardware error occurs on an OUT Q96h, al ; write register
adapter which leads to an NMI, then bit 7 In POS register 5 is set to 0 and the adapter generates Now you can access the POS registers of the selected adapter card and configure the adapter
an active CHCK signal. If additional status information is available in POS registers 6 and 7, or read the channel check bit.
576 ru 37-bit MicroChannel - Revolution 577
Chapter 23 S——~
If the channel reset bit is set in register 096h, the CHRESET signal is activated in the microcharinel — •
7 6 5 4 3 2 1 0
and all adapters are reset. Thus in the setup mode, channel reset must always be equal to 0.
After completion of the configuration the adapter activation bit in POS register 2 must be set to t
enable normal functioning of the adapter. This only refers to the adapter's logic. Write the value
ppX: extended mode of the parallel port
OOh into the adapter activation/setup register afterwards to enable the adapter (CDSETUP rises
0=no extended mode (standard) 1 =extended mode
to a high level). This only refers to driving the adapter. PP1, PPO: parallel port select
00=LPT1 (standard) 01 =LPT2 11 =LPT3
Besides the adapters, the motherboard also comprises various setup registers which may be PPE: parallel port enable
activated by means of the motherboard activation/setup register at I/O address 094h. Figure 0=disabled 1 =enabled (standard)
23.4 shows the structure of this register. SPS: serial port select
0=GOM1 (standard) 1=COM2
SPE: serial port enable
0=disabled 1 =enabled (standard)
7 6 5 4 3 2 1 0
FLE: floppy controller enable
Ico Reserved 0=disabled 1 =enabled (standard)
MBE: motherboard unit enable (except VGA)
STB: setup of board units except VGA 0=disabled 1 =enabled (standard)
0=setup mode 1 =normal mode
STV: VGA setup Figure 23.5: Motherbaord POS register 2 (Port 102h).
0=setup mode 1=normal mode
res: reserved (=0)
23.9 On-board VGA and External Graphics Adapters
Figure 23 A: Motherboard activation/setup register (Port 094h).
A main emphasis of the PS/2 concept is the integration of many units on the motherboard
If you clear the STV bit (set equal to 0) then you can configure the VGA option bytes. With a which previously have been located on separate adapter cards in a bus slot. To these units
value of 1 in this register the VGA operates normally. To the board units belong the VGA, RAM, belong, for example, the serial and parallel interface, and especially the video graphics array
floppy controller, and serial and parallel interfaces. If the STB bit is set equal to 0 then you can (VGA). All these units are accessed by means of the local channel or the peripheral standard bus.
access POS registers 2 and 3 of the motherboard units and configure them. As is the case with The VGA is functionally identical to (and also available as) the video graphics adapter (VGA) for
adapters, these POS registers are present at I/O addresses 102h and 103h. The structure of POS AT and EISA computers. Original VGA (that is, the video graphics array) is integrated on the
register 2 is shown in Figure 23.5. POS register 3 serves to configure the RAM, and Is very PS/2 motherboard, but the video graphics adapter is implemented as an adapter for a bus slot.
model-dependent. Thus, only POS register 2 Is described in further detail here. Information Thus, a PS/2 computer with an integrated VG array needs significantly fewer slots than an AT
concerning POS register 3 can be found In the technical reference manual for your PS/2. For all or EISA computer.
other users, this Information Is of no value.
For some users even the video graphics array with a resolution of 640 * 480 pixels and 256 colours
In extended mode the parallel port can be operated bidirectionally. The remaining bits are self- is not sufficient. In particular, high-resolution graphics applications like CAD need-more power-
evident. ful adapters. These adapters may be inserted into a bus slot, of course, but the only problem
is that the VGA on the motherboard is still present and must be disabled for correct operation
The adapter activation/setup register (port 096h) structure ensures that you can only activate of the new adapter. Removing the VGA is naturally impossible. Instead, IBM had a more
a single slot for a setup, thus setup conflicts on the adapters are Impossible. However, note that
elegant idea. One MCA slot in every PS/2 comprises a so-called video extension (see Figure 23.6).
you may put an adapter and the motherboard simultaneously Into the setup mode. This inevi-
An MCA graphics adapter must always be inserted into this slot to service the graphics signals.
tably leads to problems, and damage to chips may even occur. Therefore, be careful when
programming the setup! By pulling some of these signals to a low level, the inserted adapter can deactivate parts of the
on-board VGA and generate the corresponding signals itself. For this purpose, the connected
As was the case for EISA, every MCA product comes with a configuration disk which holds a monitor need not even be plugged in differently (if it accepts the new video mode, of course);
file containing the necessary Information. This file Is called the adapter description file (ADF). The it is still driven by the same plug of the PS/2. Internally, though, the change can be immense.
filename has the format «@iiii.adf», where iiii Is the four-digit adapter identification number in For example, the high-resolution 8514/A adapter with a dedicated graphics processor pulls the
hexadecimal notation. Like EISA, the ADF also uses a configuration language that reminds us ESYNC, EDCLK and EVIDEO signals to a low level. Then it generates its own synchronization,
of CONFIG.SYS commands. pixel clock and colour signals for the monitor which it transfers by means of the contacts
578 Chapter 23
. __ _—____^ uqYNC VSYNC BLANK, DCLK and P0-P7 to the motherboard's logic to drive the monitor
•I Thus the on-board VGA is more or less disabled and the monitor cut off. Only the DAC is sbU
ESYNC SV10E VSYNC
c GND HSYNC
o P5 BLANK
running, converting the digital video data P0-P7 to an analogue signal for the monitor. All
® c _< P6 }r
GND EDCLK £ control and pixel signals come from the 8514/A.
^> 9" P1
UJ GND GND SM4I res I ^ --r
MMCCMD I -S g
__ GND 3V1E
H res JM1E MMC _J C Q,
'"Audio GND 1011 CDSETUP Audio GND 3 01 t CDSETUP~i SZ X
Audio MADE 24 Audio MADE 24 _OUJ
GND GND GND GND
14.3MHz A11 14.3MHz A11/D43
GND A10 GND A10/D42 esSZ
A23 A9 A23/D55 A9/D41
A22 +5V A22/D54 +5V The PS/2 Model 30 occupies a special position. It is actually a hidden XT with the outward
A21 A8 A21/D53 A8/D40
aonearance of a PS/2 case. The model 30 thus has no microchannel, but instead the old XT bus.
A19 +5V A19/D51 +5V
fhe only advantage is that the model 30 is already prepared for the 1.44 Mbyte floppy and hard
A17 A3 A17/D49
A16 +5V A16/D48
+5V disk drives, and thus also has a much more modern BIOS.
A15 A2 A15/D47 A2/D34
GND A1 GND A1/D33
A14 3 E AO A14/D46 1 E A0/D32
c •A13 +12V A13/D45 +12V c
A12 I 1 20 I
o 201 ADL A12/D44 ADL o
GND 1 E I E
"C PREEMPT GND PREEMPT ""C
23.11 The IViCA Slot
±i GND ARB1 QNQ ARB1 ±2
_Q IRQ5 ARB2 |RQ5 ARB2
00 After deciding to throw the AT concept overboard, IBM was of course free to redesign the
GND ARB/GNT ARB/GNT
res 1 30 E TC
G N D
3 3OE TC
layout of the bus slots. Also, for a PS/2 there should be 8-bit adapters (for example, parallel
interface adapters), 16-bit adapters for models 50 and 60 with 80286 or ^ F " 0 * * ^
CMD M/iO CMD M/IO
1 C +12V
32-bit adapters (for example, fast ESDI controllers for the PS/2 models with l386 or i486 CPUs).
GND DO GND DO
D2 D1 ] E D2 Thus 8- 16- and 32-bit slots are required, with the 8-bit slot already implementing all the
+5V D3 3 E +5V
3 4OE D5
important control lines. The result is the MCA slot with various slot extensions, as shown m
CHRESET D7 CHRESET 3 [ D7
I E GND
3 REF GND 3 45 1
^ G N D 45E
i l l The kernel of the MCA slot is the 8-bit section with its 90 contacts. Unlike EISA, the MCA slot
"~ D8 3 48 £ +5V D8 148 E +5V "*
c D9 D10 D9
o only has contacts on a single layer, but they are much narrower and every fourth contact of a
o D14 +12V D14 +12V o row is grounded or at the power supply level. The ground and supply contacts on both sides
D15 res D15 res >_ Q_
CDDS16 _Q are shifted by two positions so that, effectively, every second contact pair has a ground or
+5V IRQ11 +5V
supply terminal. By the defined potential of these contacts, the noise resistance is significantly
3 60! res
better than on an AT.
The AT had up to 31 succeeding signal contacts without any interposed ground or supply
D19 contacts. With the EISA slot, the noise sensitivity is slightly reduced because the lower EISA
contact row has significantly more such contacts than the AT section of the EISA slot.
res 1 70 E D24 £Z
_o Besides the 8-bit section there are various extensions: the 16-bit section for 16-bit MCA adapters;
o the 32-bit section for 32-bit MCA adapters; the video extension for additional graphics adapters;
IQ and the matched-memory extension for memories with a higher access rate. The 16-bit PS/2
3 80 E CDDS32
models do not have any 32-bit extensions, of course. Because of the narrow contacts, the MCA
A25/D57 A26/D58 slot is nevertheless quite compact, although it holds up to 202 contacts.
res GND _J
Figure 23.6: The MCA slot. This section discusses the MCA contacts and the meaning of the signals which are supplied or
580 32-bit MicroChannel - Revolution 581
Because the microchannel supports busmasters on external adapters without any restriction, all VSYNC (I)
connections are bidirectional To show the data and signal flow more precisely, 1 have assumed Terminal VI Or
for the indicated transfer directions that the CPU (or another device on the motherboard) rep-
resents the current busmaster. The enumeration follows the original IBM convention; I indicates A high-level vertical synchronization pulse from the inserted adapter causes a vertical synchro-
the (according to the figure) left contact, and r the right contact. The MCA connections are nization, that is, a vertical retrace of the electron beam.
grouped corresponding to their functions.
Matched Memory Extension
MMC, MMCCMD, MMCR (O, O, I)
BLANK (I) Terminals Mir, M3r M21
These three signals control the so-called matched-memory cycles. To carry out a matched memory
A high-level signal from the inserted adapter blanks the screen. cycle the bus controller activates the matched-memory cycle signal MMC. If the addressed unit
supports this cycle type, it returns an active matched-memory cycle return signal MMCR with
a low level. Instead of CMD of the normal cycle, here the MMC command signal MMCCMD Is
used for controlling the bus transfer.
The data clock signal from the inserted adapter supplies the pixel clock for the OAC.
8-bit, 16-bit and 32-bit Section
Terminal V5r 143 MHz (O)
A low-level enable DCLK signal from the inserted adapter cuts the VGA on the motherboard
off from the pixel clock line to the video OAC. Instead, the DAC uses the clock signal DCLK This signal is the 14 317 180 Hz clock signal for timers and other components.
from the inserted adapters.
ESYNC (I) Terminals 61-81,101-121,141-161,181-201, 811-821, 841-861, 4r-6r, 8r-10r 12r-14r, 16r-18r, 82r-84r
These 32 connections form the 32-bit address bus of the microchannel.
A low-level enable synchronization signal from the inserted adapter causes the VGA on the
motherboard to be cut off from the three synchronization signals VSYNC, HSYNC and BLANK.
EVIDEO (I) Terminal 20r
Terminal VI r
A low-level address latch signal indicates that a valid address is present on the microchannel,
A low-level enable video signal from the inserted adapter cuts off the VGA on the motherboard and activates the address decoder latches.
from the palette bus. Using this, the inserted adapter can supply the video data P7-PD.
Terminals 24r-26r, 28r
These four arbitration signals Indicate (in binary-encoded form) which of the maximum 16
A high-level horizontal synchronization pulse from the inserted adapter causes a horizontal
possible busmasters has won the bus arbitration and gets control of the system bus.
synchronization, that is, a horizontal retrace of the electron beam.
P7-P0 (I) ARB/GNT (O)
Terminals V21-V41, V61-V81, V2r, V6r Terminal 29r
These eight signals form the binary video data for the video DAC (digital to analogue converter) If this arbitration/grant connection is on a high level, an arbitration cycle Is in progress. If ARB/
on the motherboard, which then generates the analogue signal for the monitor. By means of the GOT falls to a low level the arbitration signals ARB0-ARB3 are valid and Indicate the new
eight bits P7-PQ, the 256 simultaneously display able colours of the VGA can be encoded. busmaster.
Chapter 23 32-bit MicroChannel - Revolution
Audio, AudioGND (I, I) CHRDY (i)
Terminals 11, 21 Terminal 36r
These two connections supply the tone signal and the accompanying tone signal ground to the A high-level signal at this channel ready connection indicates that the addressed unit is ready,
motherboard. An adapter is thus able to use the speaker logic of the motherboard. The adapter that is, has completed the intended access. Thus this contact transfers the ready signal from
applies the tone signal which the system speaker outputs to the connection Audio. addressed devices on an adapter card. If CHRDY is low the processor or DMA chip extends the
bus cycles; it inserts one or more wait states.
Terminals 761-781, 78r CHRDYRTN (i)
These four byte enable signals indicate on which byte of the 32-bit data bus data is transferred. Terminal 351
They correspond to the address bits AO and Al, therefore. The signals come directly from the A high channel ready return level as the return signal from the addressed device indicates that
CPU. BED refers to the least significant byte D0-D7 of the data bus, BE3 the high-order byte the I/O channel is ready.
1 CHRESET (O)
BURST CO) ; Terminal 421
A high level at this channel reset connection resets all adapters.
A low-level signal instructs the bus system to carry out a burst cycle.
CDDS16 (I) Terminal 341
If the command signal CMD Is active (that is, low), the data- on the bus is valid.
The inserted adapter card applies a high-level signal to this card data size 16 connection to indicate
that it is running with a data width of 16 bits. Then the bus controller operates accordingly. O0-O31 (I/O)
Terminals 381-401, 481-491, 511-531, 641-661, 681-691, 721-741, 37r-39r, 40r-42r, 49r-51r, 66r-68r,
CDDS32 (I) 70r-72r, 74r-75r
These 32 connections • form the 32-bit data bus of the microchannel.
If the inserted adapter card applies a low-level signal to this card data size 32 connection, it has
a data width of 32 bits. OS16RTN CD
COSETUP (i A data size 16 return signal with a low level from the addressed device indicates that the device
Terminal Ir is running at a data bus width of 16 bits. The bus controller thus splits 32-bit quantities into
An active (low) card setup level instructs the addressed adapter to carry out a setup. 16-bit portions, and combines two 16-bit items into a single 32-bit quantity.
CDSFDBK (I) DS32RTN (I)
Terminal 361 Terminal 79r
An active (low) card select feedback level indicates that the addressed adapter card is ready. A data size 32 return signal with a low level indicates that the addressed device is running at
CDSFDBK is the return signal for the adapter selection. the full data bus width of 32 bits.
CHCK (i) IRQ3-IRQ7, IRQ9-IRQ12, IRQ14, IRQ15 (I)
Terminal 321 Terminals 221-241, 261-281, 551-571, 57r-58r
Via this channel check contact the adapter cards apply error information to the motherboard to These 11 Interrupt request connections are available for hardware Interrupt requests from
indicate, for example, a parity error on a memory expansion adapter, or a general error on an peripheral adapters. The microchannel operates with level-triggered hardware Interrupts.
adapter card. IRQO (system clock), IRQ1 (keyboard), IRQ2 (cascading according to the second AT PIC), IRQ8
584 Chapter 23 32-bit MicroChannel - Revolution 585
(real-time clock) and IRQ13 (coprocessor) are reserved for components on the motherboard, and TR32 CD
therefore do not lead into the bus slots. Terminal 801
A high-level translate 32 signal indicates that the external busmaster is a 32-bit device and
MADE 24 (O) drives BE0-BE3 instead of SBHE.
For the extension of the standard MCA specification and the 32-bit streaming data procedures
A high-level memory address enable 24 signal activates the address line A24. to 64-bit SDPs the address contacts A0-A31 are used for data transfer and mapped onto the 32
high-order data bits D32-D63.
All other contacts are reserved (res), are grounded (GND), or transfer supply voltages for chips
Terminal 34r (+5 V, -5 V) and interfaces or drives (+12 V, -12 V).
A high-level memory/IO signal indicates a memory cycle; a low-level signal an access to the
I/O address space.
Terminal 21 r
A low-level signal issues an arbitration cycle for passing the bus to various busmasters. External
busmasters activate PREEMPT to request control of the bus.
The refresh signal is at a low level if the motherboard is currently executing a memory refresh.
With this signal, the dynamic memory on adapter cards (for example, the video RAM) can also
be refreshed synchronous to main memory. Thus the adapter does not need its own refresh logic
and no additional time is wasted for refreshing DRAM on the adapters. The REF signal indi-
cates that the address bus has a row address for the refresh.
SO, SI (O; O)
These two contacts transfer the corresponding status bits of the microchannel.
A high-level system byte high enable signal indicates that the high-order data bus byte D8-D15
of the 16-bit microchannel section transfers valid data.
A low-level signal at this terminal count pin indicates that the counter of the active DMA
channel has reached its terminal value and the DMA transfer is complete.