496 CHAPTER 12 INTERRUPTS
11. Explain how a type 0 interrupt occurs. CHAPTER 13
12. Where is the interrupt descriptor table located for protected mode operation?
13. Each protected mode interrupt descriptor contains what information?
Describe the differences between a protected and real mode interrupt.
Describe the operation of the BOUND instruction.
Direct Memory Access
Describe the operation of the INTO instruction.
What memory locations contain the vector for an INT 44H instruction? and DMA-Controlled I/O
18. Explain the operation of the IRET instruction.
19. What is the purpose of interrupt vector type number 7?
20. List the events that occur when an interrupt becomes active.
21. Explain the purpose of the interrupt flag (IF).
22. Explain the purpose of the trap flag (TF).
23. How is IF cleared and set?
24. How is TF cleared and set?
25. The NMI interrupt input automatically vectors through which vector type number?
26. Does the INTA signal activate for the NMI pin?
27. The INTR input is _______ -sensitive. INTRODUCTION
28. The NMI input is _______ -sensitive.
29. When the INTA signal becomes a logic 0, it indicates that the microprocessor is waiting for In previous chapters, we discussed basic and interrupt-processed I/O. Now we turn to the final
an interrupt __________ number to be placed on the data bus (DO-D7). form of I/O called direct memory access (DMA). The DMA I/O technique provides direct ac-
30. What is a FIFO? cess to the memory while the microprocessor is temporarily disabled. This allows data to be
31. Develop a circuit that places interrupt type number 86H on the data bus in response to the transferred between memory and the I/O device at a rate that is limited only by the speed of the
INTR input. memory components in the system or the DMA controller. The DMA transfer speed can ap-
32. Develop a circuit that places interrupt type number CCH on the data bus in response to the proach 32-40 M-byte transfer rates with today's high-speed RAM memory components.
INTR input. DMA transfers are used for many purposes, but more common are DRAM refresh, video
33. Explain why pull-up resistors on DO-D7 cause the microprocessor to respond with interrupt displays for refreshing the screen, and disk memory system reads and writes. The DMA
vector type number FFH for the INTA pulse. transfer is also used to do high-speed memory-to-memory transfers.
34. What is a daisy-chain? This chapter also explains the operation of disk memory systems and video systems that
35. Why must interrupting devices be polled in a daisy-chained interrupt system? are often DMA-processed. Disk memory includes floppy, fixed, and optical disk storage. Video
36. Whatisthe8259A? systems include digital and analog monitors.
37. How many 8259As are required to have 64 interrupt inputs?
38. What is the purpose of the IRO-IR7 pins on the 8259A?
39. When are the CAS2-CASO pins used on the 8259A? CHAPTER OBJECTIVES
40. Where is a slave INT pin connected on the master 8259A in a cascaded system?
41. WhatisanlCW? Upon completion of this chapter, you will be able to:
42. What is an OCW?
1. Describe a DMA transfer.
43. How many ICWs are needed to program the 8259A when operated as a single master in a
2. Explain the operation of the HOED and HEDA direct memory access control signals.
3. Explain the function of the 8237 DMA controller when used for DMA transfers.
44. Where is the vector type number stored in the 8259A?
4. Program the 8237 to accomplish DMA transfers.
45. Where is the sensitivity of the IR pins programmed in the 8259A?
5. Describe the disk standards found in personal computer systems.
46. What is the purpose of ICW1?
6. Describe the various video interface standards that are found in the personal computer.
47. What is a non-specific EOI?
48. Explain priority rotation in the 8259A.
49. What is the purpose of IRR in the 8259A?
50. At which I/O ports is the master 8259A PIC found in the personal computer?
51. At which I/O ports is the slave 8259A found in the personal computer? 13-1 BASIC DMA OPERATION
Two control signals are used to request and acknowledge a direct memory access (DMA)
transfer in the microprocessor-based system. The HOED pin is an input that is used to request a
DMA action and the HEDA pin is an output that acknowledges the DMA action. Figure 13-1
shows the timing that is typically found on these two DMA control pins.
498 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-2 THE 8237 DMA CONTROLLER 499
FIGURE 13-1 HOLD and orT. FIGURE 13-2 A circuit that Vcc
HLDA timing for the micro- generates system control sig-
processor. nals in a DMA environment.
2 1A 4 IPlRP
, 3 1B 1Y
HLDA W/R l[02 5 2A
V^ , 11 3A 9
74F04 10 3B 3Y
14 4A 4Y
Whenever the HOLD input is placed at a logic 1 level, a DMA action (hold) is re- 13 4B
quested. The microprocessor responds, within a few clocks, by suspending the execution of
HL DA 15,,
the program and by placing its address, data, and control bus at their high-impedance states. G
The high-impedance state causes the microprocessor to appear as if it has been removed from
its socket. This state allows external I/O devices or other microprocessors to gain access to
the system buses so that memory can be accessed directly.
As the timing diagram indicates, HOLD is sampled in the middle of any clocking cycle.
Thus, the hold can take effect any time during the operation of any instruction in the micro-
processor's instruction set. As soon as the microprocessor recognizes the hold, it stops executing 13-2 THE 8237 DMA CONTROLLER
software and enters hold cycles. Note that the HOLD input has a higher priority than the INTR
or NMI interrupt inputs. Interrupts take effect at the end of an instruction, while a HOLD takes The 8237 DMA controller supplies the memory and I/O with control signals and memory ad-
effect in the middle of an instruction. The only microprocessor pin that has a higher priority than dress information during the DMA transfer. The 8237 is actually a special-purpose micro-
a HOLD is the RESET pin. Note that the HOLD input may not be active during a RESET or the processor whose job is high-speed data transfer between memory and the I/O. Figure 13-3
reset is not guaranteed. shows the pin-out and block diagram of the 8237 programmable DMA controller. Although this
The HLDA signal becomes active to indicate that the microprocessor has indeed placed its device may not appear as a discrete component in modern microprocessor-based systems, it does
buses at their high-impedance state, as can be seen in the timing diagram. Note that there are a appear within system controller chip-sets found in most systems. Although not described be-
few clock cycles between the time that HOLD changes and until HLDA changes. The HLDA cause of its complexity, the chip set (82357 ISP or integrated system peripheral controller) and
output is a signal to the external requesting device that the microprocessor has relinquished con- its integral set of two DMA controllers are programmed exactly as the 8237. The ISP also pro-
trol of its memory and I/O space. You could call the HOLD input a DMA request input and the vides a pair of 8259A programmable interrupt controllers for the system.
HLDA output a DMA grant signal. The 8237 is a four-channel device that is compatible with the 8086/8088 microprocessors.
The 8237 can be expanded to include any number of DMA channel inputs, although four chan-
Basic DMA Definitions nels seem to be adequate for many small systems. The 8237 is capable of DMA transfers at rates
of up to 1.6M bytes per second. Each channel is capable of addressing a full 64K-byte section of
Direct memory accesses normally occur between an I/O device and memory without the use of
memory and can transfer up to 64K bytes with a single programming.
the microprocessor. A DMA read transfers data from the memory to the I/O device. A DMA
write transfers data from an I/O device to memory. In both operations, the memory and I/O are
controlled simultaneously, which is why the system contains separate memory and I/O control Pin Definitions
signals. This special control bus structure of the microprocessor allows DMA transfers. A DMA CLK The clock input is connected to the system clock signal as long as that
read causes both the MRDC and IOWC signals to simultaneously activate, transferring data from signal is 5 MHz or less. In the 8086/8088 system, the clock must be
the memory to the I/O device. A DMA write causes the MWTC and IORC signals to both acti- inverted for the proper operation of the 8237.
vate. These control bus signals are available to all microprocessors in the Intel family except the cs Chip select enables the 8237 for programming. The CS pin is normally
8086/8088 system. The 8086/8088 require their generation with either a system controller or a
connected to the output of a decoder. The decoder does not use the
circuit such as the one illustrated in Figure 13-2. The DM A controller provides the memory with
8086/8088 control signal IO/M (M/IO) because it contains the new
its address and a signal from the controller (DACK) selects the I/O device during the DMA
memory and I/O control signals (MEMR, MEMW, IOR, and IOW).
The data transfer speed is determined by the speed of the memory device or a DMA con- RESET The reset pin clears the command, status, request, and temporary
troller that often controls DMA transfers. If the memory speed is 100 ns, DMA transfers occur at registers. It also clears the first/last flip-flop and sets the mask register.
rates of up to 1/100 ns or 10 M-bytes per second. If the DMA controller in a system functions at This input primes the 8237 so it is disabled until programmed
a maximum rate of 5 MHz and we still use 100 ns memory, the maximum transfer rate is 5 MHz otherwise.
because the DMA controller is slower than the memory. In many cases, the DMA controller READY A logic 0 on the ready input causes the 8237 to enter wait states for
slows the speed of the system when DMA transfers occur. slower memory and/or I/O components.
CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-2 THE 8237 DMA CONTROLLER 501
ADSTB Address strobe functions as ALE, except that it is used by the DMA
controller to latch address bits A15-A8 during the DMA transfer.
MEMR Memory read is an output that causes memory to read data during a
DMA read cycle.
MEMW Memory write is an output that causes memory to write data during a
DMA write cycle.
CAR The current address register is used to hold the 16-bit memory
address used for the DMA transfer. Each channel has its own current
address register for this purpose. When a byte of data is transferred
during a DMA operation, the CAR is either incremented or
decremented, depending on how it is programmed.
CWCR The current word count register programs a channel for the number
of bytes (up to 64K) transferred during a DMA action. The number
loaded into this register is one less than the number of bytes transferred.
FIGURE 13-3 The 8237A-5 programmable DMA controller, (a) Block diagram, and (b) pin-out. For example, if a 10 is loaded into the CWCR, then 11 bytes are
(Courtesy of Intel Corporation.) transferred during the DMA action.
BA and BWC The base address (BA) and base word count (BWC) registers are used
HLDA A hold acknowledge signals the 8237 that the microprocessor has when auto-initialization is selected for a channel. In the auto-
relinquished control of the address, data, and control buses. initialization mode, these registers are used to reload both the CAR and
CWCR after the DMA action is completed. This allows the same count
DREQ3-DREQO The DMA request inputs are used to request a DMA transfer for each
and address to be used to transfer data from the same memory area.
of the four DMA channels. Because the polarity of these inputs is
programmable, they are either active-high or active-low inputs. CR The command register programs the operation of the 8237 DMA
controller. Figure 13-4 depicts the function of the command register.
DB7-DBO The data bus pins are connected to the microprocessor data bus
connections and are used during the programming of the DMA The command register uses bit position 0 to select the memory-to-
memory DMA transfer mode. Memory-to-memory DMA transfers use
DMA channel 0 to hold the source address and DMA channel 1 to hold the
IOR I/O read is a bi-directional pin used during programming and during a destination address. (This is similar to the operation of a MOVSB instruc-
DMA write cycle. tion.) A byte is read from the address accessed by channel 0 and saved
IOW I/O write is a bi-directional pin used during programming and during a
DMA read cycle.
FIGURE 13-4 8237 A-5 7 6 5 4 3 2 1 (H -Bit Number
EOF End-of-process is a bi-directional signal that is used as an input to
terminate a DMA process or as an output to signal the end of the DMA
command register. (Courtesy i.i.u.i.iTTi
transfer. This input is often used to interrupt a DMA transfer at the end
of a DMA cycle.
of Intel Corporation.)
k o Memory-to memory disable
1 Memory-to-memory enable
' 0 Channel 0 address hold disable
A3-AO These address pins select an internal register during programming and
also provide part of the DMA transfer address during a DMA action. .X Ifbit0 = 0
___ T 0 Controller enable
A7-A4 These address pins are outputs that provide part of the DMA transfer L1 Controller disable
address during a DMA action. '0 Normal timing
HRQ Hold request is an output that connects to the HOLD input of the
.X If bit 0 = 1
microprocessor in order to request a DMA transfer.
F 0 Fixed priority
DACK3-DACKO DMA channel acknowledge outputs acknowledge a channel DMA L 1 Rotating priority
request. These outputs are programmable as either active-high or active- I" 0 Late write selection
low signals. The DACK outputs are often used to select the DMA
LX If bit 3 = 1
controlled I/O device during the DMA transfer.
T0 DREQ sense active hiah
AEN The address enable signal enables the DMA address latch connected to L1 DREQ sense active low
the DB7-DBO pins on the 8237. It is also used to disable any buffers in f0 DACK sense active low
the system connected to the microprocessor. L1 DACK sense active high
13-2 THE 8237 DMA CONTROLLER 503
502 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O
within the 8237 in a temporary holding register. Next, the 8237 initiates FIGURE 13-6 8237A-5 re- 5 4 3 2 1 0 ^ -Bit Number
quest register. (Courtesy of
a memory write cycle, in which the contents of the temporary holding
register are written into the address selected by DMA channel 1. The 00 Select channel 0
number of bytes transferred is determined by the channel 1 count register. 01 Select channel 1
10 Select channel 2
The channel 0 address hold enable bit (bit position 1) programs 11 Select channel 3
channel 0 for memory-to-memory transfers. For example, if you must 0 Reset request bit
fill an area of memory with data, channel 0 can be held at the same 1 Set request bit
address while channel 1 changes for memory-to-memory transfer. This
copies the contents of the address accessed by channel 0 into a block of
EOF is input or until the DREQ input becomes inactive. Single mode
memory accessed by channel 1.
releases the HOLD after each byte of data is transferred. If the DREQ
The controller enable/disable bit (bit position 2) turns the entire
pin is held active, the 8237 again requests a DMA transfer through the
controller on and off. The normal and compressed bit (bit position 3)
DRQ line to the microprocessor's HOED input. Block mode automati-
determine whether a DMA cycle contains 2 (compressed) or 4 (normal)
cally transfers the number of bytes indicated by the count register for
clocking periods. Bit position 5 is used in normal timing to extend the
the channel. DREQ need not be held active through the block mode
write pulse so it appears one clock earlier in the timing for I/O devices
transfer. Cascade mode is used when more than one 8237 is present
that require a wider write pulse. in a system.
Bit position 4 selects priority for the four DMA channel DREQ
RR The request register is used to request a DMA transfer via software
inputs. In the fixed priority scheme, channel 0 has the highest priority
and channel 3 has the lowest. In the rotating priority scheme, the most (see Figure 13-6). This is very useful in memory-to-memory transfers,
where an external signal is not available to begin the DMA transfer.
recently serviced channel assumes the lowest priority. For example, if
channel 2 just had access to a DMA transfer, it assumes the lowest MRSR The mask register set/reset sets or clears the channel mask, as
priority and channel 3 assumes the highest priority position. Rotating illustrated in Figure 13-7. If the mask is set, the channel is disabled.
priority is an attempt to give all channels equal priority. Recall that the RESET signal sets all channel masks to disable them.
The remaining two bits (bit positions 6 and 7) program the polarities MSR The mask register (see Figure 13-8) clears or sets all of the masks with
of the DREQ inputs and the DACK outputs. one command instead of individual channels, as with the MRSR.
MR The mode register programs the mode of operation for a channel. SR The status register shows the status of each DMA channel (see
Note that each channel has its own mode register (see Figure 13-5), Figure 13-9). The TC bits indicate whether the channel has reached its
as selected by bit positions 1 and 0. The remaining bits of the mode terminal count (transferred all its bytes). Whenever the terminal count
register select the operation, auto-initialization, increment/decrement, is reached, the DMA transfer is terminated for most modes of operation.
and mode for the channel. Verification operations generate the DMA The request bits indicate whether the DREQ input for a given channel
addresses without generating the DMA memory and I/O control signals. is active.
The modes of operation include demand mode, single mode, block
mode, and cascade mode. Demand mode transfers data until an external FIGURE 13-7 8237A-5 7 6 5 4 3 2 1 0-* -Bit Number
mask register set/reset I I I I I I I I I
mode. (Courtesy of Intel
7 6 5 4 3 2 1 CH -Bit Number Don't Care 00 Select channel 0 mask bit
FIGURE 13-5 8237A-5 Corporation.)
mode register (Courtesy of
Select channel 1 mask bit
Select channel 2 mask bit
Select channel 3 mask bit
00 Channel 0 select
01 Channel 1 select "0 Clear mask bit
10 Channel 2 select . 1 Set mask bit
11 Channel 3 select
[" 00 Verify transfer
01 Write transfer FIGURE 13-8 8237A-5 7 6 5 4 3 2 1 0 * - -Bit Number
10 Read transfer mask register. (Courtesy of II I I I I I I I
LXX If bits 6 and 7 = 11
0 Autoinitialization disable
k 0 Clear channel 0 mask bit
1 Set channel 0 mask bit
1 Autoinitialization enable
0 Address increment select 4 0 Clear channel 1 mask bit
1 Set channel 1 mask bit
1 Address decrement select
Demand mode select
Single mode select
-tr 0 Clear channel 2 mask bit
1 Set channel 2 mask bit
0 Clear channel 3 mask bit
10 Block mode select
11 Cascade mode select 1 Set channel 3 mask bit
504 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-2 THE 8237 DMA CONTROLLER 505
FIGURE 13-9 8237A-5 7 6 5 4 3 2 1 -Bit Number Signals
status register. (Courtesy of 1 1 1 1 1 1 1 1 CS IOR IOW A3 A2 A1 AO
Internal Flip-Flop L/atcl DllS UDU-UD/
Intel Corporation.) ' — 1 Channel 0 has reached TC 0 Base and Current Address Write 0 1 0 0 0 0 0 0 AO-A7
' ——— 1 Channel 1 has reached TC 0 1 0 0 0 0 0 1 A8-A15
———— 1 Channel 2 has reached TC Current Address Read 0 0 1 0 0 0 0 0 AO-A7
0 0 1 0 0 0 0 1 A8-A15
Base and Current Word Count Write 0 1 0 0 0 0 1 0 WO-W7
0 1 0 0 0 0 1 1 W8-W15
Current Word Count Read 0 0 1 0 0 0 1 0 WO-W7
' ————————————— 1 Channel 3 reauest 0 0 1 0 0 0 1 1 W8-W15
1 Base and Current Address Write 0 1 0 0 0 1 0 0 AO-A7
0 1 0 0 0 1 0 1 A8-A15
Current Address Read 0 0 1 0 0 1 0 0 AO-A7
Software Command 0 0 1 0 0 1 0 1 A8-A15
Base and Current Word Count Write 0 1 0 0 0 1 1 0 WO-W7
Three software commands are used to control the operation of the 8237. These commands do not 0 1 0 0 0 1 1 1 W8-W15
have a binary bit pattern, as do the various control registers within the 8237. A simple output to Current Word Count Read 0 0 1 0 0 1 1 0 WO-W7
the correct port number enables the software command. Figure 13-10 shows the I/O port assign- 0 0 1 0 0 1 1 1 W8-W15
2 Base and Current Address Write 0 1 0 0 1 0 0 0 AO-A7
ments that access all registers and the software commands. 0 1 0 0 1 0 0 1 A8-A15
The function of the software commands are explained in the following list: Current Address Read 0 0 1 0 1 0 0 0 AO-A7
0 0 1 0 1 0 0 1 A8-A15
1. Clear the first/last flip-flop—Clears the first/last (F/L) flip-flop within the 8237. The F/L
Base and Current Word Count Write 0 1 0 0 1 0 1 0 WO-W7
flip-flop selects which byte (low or high order) is read/written in the current address and cur- 0 1 0 0 1 0 1 1 W8-W15
rent count registers. If F/L = 0, the low order byte is selected; if F/L = 1, the high order byte Current Word Count Read 0 0 1 0 1 0 1 0 WO-W7
is selected. Any read or write to the address or count register automatically toggles the F/L 0 0 1 0 1 0 1 1 W8-W15
flip-flop. 3 Base and Current Address Write 0 1 0 0 1 1 0 0 AO-A7
0 1 0 0 1 1 0 1 A8-A15
2. Master clear—Acts exactly the same as the RESET signal to the 8237. As with the RESET
Current Address Read 0 0 1 0 1 1 0 0 AO-A7
signal, this command disables all channels. 0 0 1 0 1 1 0 1 A8-A15
3. Clear mask register—Enables all four DMA channels. Base and Current Word Count Write 0 1 0 0 1 1 1 0 WO-W7
0 1 0 0 1 1 1 1 W8-W15
Programming the Address and Count Registers Current Word Count Read 0 0 1 0 1 1 1 0
0 0 1 0 1 1 1 W8-W15
Figure 13-11 illustrates the I/O port locations for programming the count and address registers
for each channel. Notice that the state of the F/L flip-flop determines whether the LSB or MSB FIGURE 13-11 8237A-5 DMA channel I/O port addresses. (Courtesy of Intel Corporation.)
is programmed. If the state of the F/L flip-flop is unknown, the count and address could be pro-
grammed incorrectly. It is also important that the DMA channel be disabled before its address
There are four steps required to program the 8237: (1) the F/L flip-flop is cleared using a
and count are programmed. clear F/L command, (2) the channel is disabled, (3) the LSB and then MSB of the address are
programmed, and (4) the LSB and MSB of the count are programmed. Once these four opera-
FIGURE 13-10 8237 A-5
tions are performed, the channel is programmed and ready to use. Additional programming is re-
Operation quired to select the mode of operation before the channel is enabled and started.
command and control port as- A3 A2 A1 AO IOR IOW
signments. (Courtesy of Intel 1 0 0 0 0 1 Read Status Register
Corporation.) 1 n 0 0 1 0 Write Command Register The 8237 Connected to the 80X86 Microprocessor
1 0 0 1 0 1 Illegal
1 o 0 1 1 0 Write Request Register Figure 13-12 shows an 80X86-based system that contains the 8237 DMA controller.
1 o 1 0 0 1 Illegal
The address enable (AEN) output of the 8237 controls the output pins of the latches and
1 0 1 0 1 0 Write Single Mask Register Bit
the outputs of the 74LS257 (E). During normal 80X86 operation (AEN = 0), latches A and C and
1 n 1 1 0 1 Illegal
1 0 1 1 1 0 Write Mode Register the multiplexer (E) provide address bus bits A19-A16 and A7-AO. The multiplexer provides the
1 1 0 0 0 1 Illegal system control signals as long as the 80X86 is in control of the system. During a DMA action
1 1 0 0 1 0 Clear Byte Pointer Flip/Flop
(AEN = 1), latches A and C are disabled along with the multiplexer (E). Latches D and B now
1 1 0 1 0 1 Read Temporary Register
provide address bits A19-A16 and A15-A8. Address bus bits A7-AO are provided directly by
1 1 0 1 1 0 Master Clear
1 1 1 0 0 1 Illegal the 8237 and contain a part of the DMA transfer address. The control signals MEMR, MEMW,
1 1 1 0 1 0 Clear Mask Register IOR, and IOW are provided by the DMA controller.
1 1 1 1 0 1 Illegal The address strobe output (ADSTB) of the 8237 clocks the address (A15-A8) into latch D
1 1 1 1 1 0 Write All Mask Register Bits
during the DMA action so that the entire DMA transfer address becomes available on the address
o FIGURE 13-12 Complete 8088 minimum mode DMA system.
508 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-2 THE 8237 DMA CONTROLLER 509
TABLE 13-1 DMA page ;Calling parameters:
register ports. Channel Port number (A16-A23) Port number (A24-A31) SI = source address
; DI = destination address
0 87H 487 H CX - count
1 83H 483H ES - segment of source and destination
2 81H 481 H = 0010 LATCHB EQU 10H ; latch B
3 82H 482H = 007C CLEAR_F EQU 7CH ;F/L flip flop
4 8FH 48FH = 0070 CHO_A EQU 7 OH ; channel 0 address
= 0072 CH1_A EQU 72H ; channel 1 address
5 8BH 48BH
= 0073 CH1_C EQU 73H ; channel 1 count
6 89H 489H = 007B MODE EQU 7BH ; mode
7 8AH 48AH = 0078 CMMD EQU 78H ; command
= 007F MASKS EQU 7FH ; masks
= 0079 REQ EQU 79H ; request register
= 0078 STATUS EQU 78H ; status register
bus. Address bus bits A19-A16 are provided by latch B, which must be programmed with these four 0000 TRANS PROC FAR USES AX
address bits before the controller is enabled for the DMA transfer. The DMA operation of the 8237
is limited to a transfer of not more than 64K bytes within the same 64K-byte section of the memory. 0001 8C CO MOV AX,ES ; program latch B
The decoder (F) selects the 8237 for programming and the 4-bit latch (B) for the upper- 0003 8A C4 MOV AL,AH
0005 CO E8 SHR AL, 4
most four address bits. The latch in a PC is called the DMA page register (8-bits) that holds ad- 0008 E6 10 OUT LATCHB , AL
dress bits A16-A23 for a DMA transfer. A high page register also exists, but its address is OOOA E6 7C OUT CLEAR_F , AL ;clear F/L flip-flop
chip-dependent. The port numbers for the DMA page registers are listed in Table 13-1 (these are OOOC 8C CO MOV AX,ES ; program source address
for the Intel ISP). The decoder in this system enables the 8237 for I/O port addresses OOOE Cl EO SHL AX, 4
XX60H-XX7FH, and the I/O latch (B) for ports XXOOH-XX1FH. Notice that the decoder 0011 03 C6 ADD AX, SI ; form source offset
output is combined with the IOW signal to generate an active-high clock for the latch (B). 0013 E6 70 OUT CHO_A,AL
0015 8A C4 MOV AL,AH
During normal 80X86 operation, the DMA controller and integrated circuits B and D are 0017 E6 70 OUT CHO_A, AL
disabled. During a DMA action, integrated circuits A, C, and E are disabled so that the 8237 can
0019 8C CO MOV AX,ES
take control of the system through the address, data, and control buses. 001B Cl EO
; program destination address
SHL AX, 4
In the personal computer, the two DMA controllers are programmed at I/O ports 001E 03 C7 ADD AX,DI ; f orm destination offset
OOOOH-OOOFH for DMA channels 0-3, and at ports OOCOH-OODFH for DMA channels 4-7. 0020 E6 72 OUT CH1_A,AL
0022 8A C4 MOV AL,AH
Note that the second controller is programmed at even addresses only, so the channel 4 base and 0024 E6 72 OUT CH1_A,AL
current address is programmed at I/O port OOCOH and the channel 4 base and current count is
programmed at port OOC2H. The page register, which holds address bits A23-A16 of the DMA 0026 8B Cl MOV AX,CX ; program count
0028 48 DEC- AX
address, are located at I/O ports 0087H (CH-0), 0083H (CH-1), 0081H (CH-2), 0082H (CH-3), 0029 E6 73
; ad just count
(no channel 4), 008BH (CH-5), 0089H (CH-6) and 008AH (CH-7). The page register functions 002B 8A C4 MOV AL,AH
as the address latch described with the examples in this text. 002D E6 73 OUT CH1_C , AL
002F BO 88 MOV AL, 88H ; program mode
Memory-to-Memory Transfer with the 8237 0031 E6 7B OUT MODE , AL
0033 BO 85 MOV AL, 85H
The memory-to-memory transfer is much more powerful than even the automatically repeated 0035 E6 7B OUT MODE , AL
MOVSB instruction. While the repeated MOVSB instruction tables the 8088 4.2 [as per byte, the
0037 BO 01 MOV AL,1 ; enable block transfer
8237 requires only 2.0 |is per byte, which is over twice as fast as a software data transfer. This is 0039 E6 78 OUT CMMD, AL
not true if an 80386, 80846, or Pentium/Pentium Pro is in use in the system.
003B BO OE MOV AL,OEH ; unmask channel 0
Sample Memory-to-Memory DMA Transfer, Suppose that the contents of memory locations 10000H- 003D E6 7F OUT MASKS , AL
13FFFH are to be transferred into memory locations 14000H-17FFFH. This is accomplished with
003F BO 04 MOV AL,4 ; start DMA transfer
a repeated string move instruction, or, at a much faster rate, with the DMA controller. 0041 E6 79 OUT REQ , AL
Example 13-1 illustrates the software required to initialize the 8237 and program latch B in
Figure 13-12 for this DMA transfer. This software is written for an embedded application. For it to . REPEAT ;wait until DMA complete
0043 E4 78 IN AL, STATUS
function in the PC, you must use the port addresses listed in Table 13-1 for the page registers. .UNTIL AL &1
EXAMPLE 13-1 RET
;A procedure that transfers a block of data using the ENDP
;8237A DMA controller in Figure 13-12. This is a
;memory-to-memory block transfer.
Programming the DMA controller requires a few steps, as illustrated in Example 13-1.
The leftmost digit of the 5-digit address is sent to latch B. Next, the channels are programmed
510 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O
13-2 THE 8237 DMA CONTROLLER 511
after the F/L flip-flop is cleared. Note that we use channel 0 as the source and channel 1 as the 0013 8C CO MOV AX,ES ; program source address
destination for a memory-to-memory transfer. The count is next programmed with a value that is 0015 Cl EO 04 SHL AX, 4
0018 03 C7 ADD AX,DI ; form source offset
one less than the number of bytes to be transferred. Next, the mode register of each channel is 001A E6 70 OUT CHO_A,AL
programmed, the command register selects a block move, channel 0 is enabled, and a software 001C 8A C4 MOV AL,AH
DMA request is initiated. Before return is made from the procedure, the status register is tested 001E E6 70 OUT CHO_A,AL
for a terminal count. Recall that the terminal count flag indicates that the DMA transfer is com- 0020 8C CO MOV AX,ES /program destination address
pleted. The TC also disables the channel, preventing additional transfers. 0022 Cl EO 04 SHL AX, 4
0025 03 C7 ADD AX,DI ; f orm destination offset
Sample Memory Fill Using the 8237. In order to fill an area of memory with the same data, the 0027 48 INC AX
channel 0 source register is programmed to point to the same address throughout the transfer. 0028 E6 72 OUT CH1_A,AL
002A 8A C4 MOV AL,AH
This is accomplished with the channel 0 hold mode. The controller copies the contents of this 002C E6 72 OUT CH1_A,AL
single memory location to an entire block of memory addressed by channel 1. This has many
002E 8B Cl MOV AX,CX ; program count
useful applications. 0030 48 DEC AX ; ad just count
For example, suppose that a video display must be cleared. This operation can be per- 0031 48 DEC AX
formed using the DMA controller with the channel 0 hold mode and a memory-to-memory 0032 E6 73 OUT CH1_C , AL
0034 8A C4 MOV AL,AH
transfer. If the video display contains 80 columns and 25 lines, it has 2000 display positions that 0036 E6 73 OUT CH1_C , AL
must be set to 20H (an ASCII space) to clear the screen.
Example 13-2 shows a procedure that clears an area of memory addressed by ES:DI. The 0038 BO 88 MOV AL,88H ; program mode
003A E6 7B OUT MODE , AL
CX register transfers the number of bytes to be cleared to the CLEAR procedure. Notice that this 003C BO 85 MOV AL, 85H
procedure is nearly identical to Example 13-1, except that the command register is programmed 003E E6 7B OUT MODE , AL
so the channel 0 address is held. The source address is programmed as the same address as 0040 BO 03 MOV AL,3 ,- enable block hold transfer
ES:DI, and then the destination is programmed as one location beyond ES:DI. Also note that this 0042 E6 78 OUT CMMD,AL
program is designed to function with the hardware in Figure 13-12 and will not function in the
0044 BO OE MOV AL,OEH ; unmask channel 0
personal computer unless you have the same hardware. 0046 E6 7F OUT MASKS , AL
EXAMPLE 13-2 0048 BO 04 MOV AL,4 ; start DMA transfer
004A E6 79 OUT REQ , AL
A procedure that clears an area of memory using the
8237A DMA controller in Figure 13-12. This is a .REPEAT ;wait until DMA complete
memory-to-memory block transfer with a channel 0 hold. 004C E4 78 IN AL , STATUS
.UNTIL AL &1
Calling parameters: RET
DI = offset address of area cleared
ES = segment address of area cleared
CX = number of bytes cleared
LATCHB EQU 10H latch B
DMA-Processed Printer Interface
CLEAR_F EQU 7CH F/L flip flop
CHO_A EQU 70H channel 0 address Figure 13-13 illustrates the hardware added to Figure 13-12 for a DMA-controlled printer inter-
CH1_A EQU 72H channel 1 address face. Little additional circuitry is added for this interface to a Centronics-type parallel printer. The
CH1_C EQU 73H channel 1 count latch is used to capture the data as it is sent to the printer during the DMA transfer. The write pulse
MODE EQU 7BH mode
CMMD EQU 78H command
passed through to the latch during the DMA action also generates the data strobe (DS) signal to the
MASKS EQU 7FH masks printer through the single-shot. The ACK signal returns from the printer each time it is ready for ad-
REQ EQU 79H request register ditional data. In this circuit, ACK is used to request a DMA action through a flip-flop.
STATUS EQU 78H status register
Notice that the I/O device is not selected by decoding the address on the address bus.
ZERO EQU OH
During the DMA transfer, the address bus contains the memory address and cannot contain the
0000 CLEAR PROC FAR USES AX I/O port address. In place of the I/O port address, the DACK3 output from the 8237 selects the
latch by gating the write pulse through an OR gate.
0001 8C CO MOV AX,ES ; program latch B
0003 8A C4 MOV AL,AH Software that controls this interface is simple because only the address of the data and the
0005 CO E8 04 SHR AL,4 number of characters to be printed are programmed. Once programmed, the channel is enabled,
0008 E6 10 OUT LATCHB , AL and the DMA action transfers a byte at a time to the printer interface each time that the interface
OOOA E6 7C OUT CLEAR_F,AL ; clear F/L flip-flop receives the ACK single from the printer.
The procedure that prints data from the current data segment is illustrated in Exam-
OOOC 2E: AO 0000 MOV AL,CS:ZERO ple 13-3. This procedure programs the 8237, but doesn't actually print anything. Printing is ac-
0010 26: 88.05 MOV ES:[DI],AL ; save zero in first
complished by the DMA controller and the printer interface.
512 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 513
0017 E6 76 OUT CH3_A, AL
FIGURE 13-13 DMA-
0019 8A C4 MOV AL,AH
processed printer interface. 001B E6 76 OUT CH3_A,AL
001D 8B Cl MOV AX,CX ; program count
001F 48 DEC AX ; adjust count
0020 E6 77 OUT CH3_C,AL
0022 8A C4 MOV AL,AH
0024 E6 77 OUT CH3_C,AL
ACK 0026 BO OB MOV AL,OBH ; program mode
0028 E6 7B OUT MODE , AL
002A BO 00 MOV AL, 0 ; enable block hold transfer
002C E6 78 OUT CMMD , AL
002E BO 07 MOV AL,7 ;unmask channel 3
0030 E6 7F OUT MASKS , AL
A secondary procedure is needed to determine whether the DMA action has been com-
pleted. Example 13-4 lists the secondary procedure that tests the DMA controller to see whether
the DMA transfer is complete. The TEST_P procedure is called before programming the DMA
controller to see whether the prior transfer is complete.
;A procedure that tests for a complete DMA action
STATUS EQU 78H ;status register
TEST_P PROC NEAR USES AX
0001 E4 78 IN AL,STATUS
.UNTIL AL &8
A procedure that prints data via the printer interface
in Figure 13-13. 0009 TEST_P ENDP
BX = offset address of printer data Printed data can be double-buffered by first loading buffer 1 with data to be printed. Next,
DS = segment address of printer data the PRINT procedure is called to begin printing buffer 1. Because it takes very little time to pro-
CX = number of bytes to print
gram the DMA controller, a second buffer (buffer 2) can be filled with new printer data while the
= 0010 LATCHB EQU 10H latch B first buffer (buffer 1) is printed by the printer interface and DMA controller. This process is re-
= 007C CLEAR_F EQU 7CH F/L flif> flop peated until all data are printed.
= 0076 CH3_A EQU 76H channel 0 address
= 0077 CH3_C EQU 77H channel 1 count
= 007B MODE EQU 7BH mode
= 0078 CMMD EQU 78H command
= 007F MASKS EQU 7FH masks
= 0079 REQ EQU 79H request register 13-3 SHARED-BUS OPERATION
0000 PRINT PROC FAR USES AX CX BX
Complex present-day computer systems have so many tasks to perform that some systems are
0003 66| B8 00000000 MOV EAX, 0 using more than one microprocessor to accomplish the work. This is called a multiprocessing
0009 8C D8 MOV AX,DS program latch B
system. We also sometimes call this a distributed system. A system that performs more than one
OOOB 66 | Cl E8 04 SHR
OOOF 50 PUSH AX task is called a multitasking system. In systems that contain more than one microprocessor,
0010 66| Cl E8 10 SHR EAX , 1 6 some method of control must be developed and employed. In a distributed, multiprocessing,
0014 E6 10 OUT LATCHB , AL multitasking environment, each microprocessor accesses two buses: (1) the local bus and (2) the
0016 58 ;program address remote or shared bus.
514 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 515
the system's shared bus space. As mentioned, the shared bus in the personal computer is what we
often call the local bus in the personal computer because it is local to the microprocessor in the
Figure 13-15 shows an 8088 microprocessor that is connected as a remote bus master. The term
bus master applies to any device (microprocessor or otherwise) that can control a bus containing
FIGURE 13-14 A block diagram illustrating the shared and local buses.
This section of the text describes shared bus operation for the 8086 and 8088 microproces-
sors using the 8289 bus arbiter. The 80286 uses the 82289 bus arbiter and the 80386/80486 uses
the 82389 bus arbiter. The Pentium-Pentium II directly support a multiuser environment, as de-
scribed in Chapters 16, 17, and 18. These systems are much more complex and difficult to illus-
trate at this point in the text, but their terminology and operation is essentially the same as for the
The local bus is connected to memory and I/O devices that are directly accessed by a single
microprocessor without any special protocol or access rules. The remote (shared) bus contains
memory and I/O that are accessed by any microprocessor in the system. Figure 13-14 illustrates
this idea with a few microprocessors. Note that the personal computer is also configured in the
same manner as the system in Figure 13-14. The bus master is the main microprocessor in the
personal computer. What we call the local bus in the personal computer is the shared bus in this
illustration. The ISA bus is operated as a slave to the personal computer's microprocessor as well
as any other devices attached to the shared bus.
Types of Buses Defined
The local bus is the bus that is resident to the microprocessor. The local bus contains the resident
or local memory and I/O. All microprocessors studied thus far in this text are considered to be
local bus systems. The local memory and local I/O are accessed by the microprocessor that is di- ADDRESS/DATA A
rectly connected to them. NT-
A shared bus is one that is connected to all microprocessors in the system. The shared bus
is used to exchange data between microprocessors in the system. A shared bus may contain
memory and I/O devices that are accessed by all microprocessors in the system. Access to the FIGURE 13-15 The 8088 operated in the remote mode, illustrating the local and shared bus
shared bus is controlled by some form or arbiter that allows only a single microprocessor to access connections.
516 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 517
memory and I/O. The 8237 DMA controller presented earlier in the chapter is an example of a FIGURE 13-16 The
S2C 1 20 UV C C
remote bus master. The DMA controller gained access to the system memory and I/O space to 8289 pin-out and block
IOB[ 2 9 3 si
cause a data transfer. Likewise, a remote bus master gains access to the shared bus for the same diagram. (Courtesy of Intel SYSB/RESB C 3 8 3 so
purpose. The difference is that the remote bus master microprocessor can execute variable soft- Corporation.) RESBC 4 3 CLK
ware, whereas the DMA controller can only transfer data. BCLKC 5 BUS 6 3 CocR
Access to the shared bus is accomplished by using the HOLD pin on the microprocessor iNffc 6 ' 5 ] CRQLCK
BREQ.C 7 4 3 ANYRQST
for the DMA controller. Access to the shared bus for the remote bus master is accomplished via
BPROC 8 3 3 AEN
a bus arbiter, which functions to resolve priority between bus masters and allows only one de- BPRNC 9 2 3 CBRQ
vice at a time to access the shared bus. GNDC 10 1 3 BUSY
Notice in Figure 13-15 that the 8088 microprocessor has an interface to both a local, resi-
dent bus and the shared bus. This configuration allows the 8088 to access local memory and I/O
or, through the bus arbiter and buffers, the shared bus. The task assigned to the microprocessor
/- -K •*-
might be data communications. It may, after collecting a block of data from the communications ARBITRATION v-~y - INIT
interface, pass those data on to the shared bus and shared memory so that other microprocessors »- BREQ
attached to the system can access the data. This allows many microprocessors to share common & MULTIBUS ^_ -BPRN -
•>• INTERFACE SIGNALS
^ STATE »BPRO
data. In the same manner, multiple microprocessors can be assigned various tasks in the system, *" GENERATOR -<- -BUSY
drastically improving throughput. »• CBRQ
LOCK- _f ^
The Bus Arbiter CLK-
!»• — *•
Before Figure 13-15 can be fully understood, the operation of the bus arbiter must be grasped. ANYRQST - &•
The 8289 bus arbiter controls the interface of a bus master to a shared bus. Although the 8289 is JOB- !»•
not the only bus arbiter, it is designed to function with the 8086/8088 microprocessors, so it is
presented here. Each bus master or microprocessor requires an arbiter for the interface to the | GND
shared bus, which Intel calls the Multibus and IBM calls the Micro Channel.
The shared bus is used only to pass information from one microprocessor to another; oth-
erwise, the bus masters function in their own local bus modes by using their own local programs, BPRO The bus priority output is a signal that is used to resolve priority in a
memory, and I/O space. Microprocessors connected in this kind of system are often called par- system that contains multiple bus masters.
allel or distributed processors because they can execute software and perform tasks in parallel.
BREQ The bus request output is used to request access to the shared bus.
8289 Architecture. Figure 13-16 illustrates the pin-out and block diagram of the 8289 bus ar-
biter. The left side of the block diagram depicts the connections to the microprocessor. The right BUSY The busy input/output indicates, as an output, that an 8289 has acquired
side denotes the 8289 connection to the shared (remote) bus or Multibus. the shared bus. As an input, BUSY is used to detect that another 8289 has
The 8289 controls the shared bus by causing the READY input to the microprocessor to acquired the shared bus.
become a logic 0 (not ready) if access to the shared bus is denied. The blocking occurs whenever CBRQ The common bus request input/output is used when a lower-priority
another microprocessor is accessing the shared bus. As a result, the microprocessor requesting microprocessor is asking for the use of the shared bus. As an output,
access is blocked by the logic 0 applied to its READY input. When the READY pin is a logic 0, CBRQ becomes a logic 0 whenever the 8289 requests the shared bus and
the microprocessor and its software wait until access to the shared bus is granted by the arbiter. remains low until the 8289 obtains access to the shared bus.
In this manner, one microprocessor at a time gains access to the shared bus. No special instruc- The clock input is generated by the 8284A clock generator and provides
tions are required for bus arbitration with the 8289 bus arbiter because arbitration is accom- the internal timing source to the 8289.
plished strictly by the hardware.
The common request lock input prevents the 8289 from surrendering the
Pin Definitions shared bus to any of the 8289s in the system. This signal functions in
conjunction with the CBRQ pin.
AEN The address enable output causes the bus drivers in a system to switch to
INIT The initialization input resets the 8289 and is normally connected to the
their three-state, high-impedance state.
system RESET signal.
ANYRQST The any request input is a strapping option that prevents a lower-priority
microprocessor from gaining to the shared bus. If tied to a logic 0, normal IOB The I/O bus input selects whether the 8289 operates in a shared-bus
arbitration occurs and a lower priority microprocessor can gain access to system (if selected by RESB) with I/O (IOB = 0) or with memory and I/O
(IOB = 1).
the shared bus if CBRQ is also a logic 0.
BCLK The bus clock input synchronizes all shared-bus masters. LOCK The lock input prevents the 8289 from allowing any other microprocessor
from gaining access to the shared bus. An 8086/8088 instruction that
BPRN The bus priority input allows the 8289 to acquire the shared bus on the contains a LOCK prefix will prevent other microprocessors from accessing
next falling edge of the BLCK signal. the shared bus.
518 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 519
RESB The resident-bus input is a strapping connection that allows the 8289 to This means that the transfer requires 10 seconds. Rather than tie up the bus master for 10 sec-
operate in systems that have either a shared-bus or resident-bus system. If onds, microprocessor B patiently performs the data transfer from its own local memory and the
RESB is a logic 1, the 8289 is configured as a shared-bus master. If RESB is local communications interface. This frees the bus master for other tasks. The only time the mi-
a logic 0, the 8289 is configured as a local-bus master. When configured as a croprocessor B interrupts the bus master is to transfer data between the shared memory and its
shared-bus master, access is requested through the SYSB/RESB input pin. local memory system. This data transfer, betweem microporcessor B and the bus master, re-
S2, SI, and SO The status inputs initiate shared-bus requests and surrenders. These pins quires only a few hundred microseconds.
connect to the 8288 system bus controller status pins. Microprocessor C is used as a print spooler. Its only task is to print data on the printer.
SYSB/RESB The system bus/resident bus input selects the shared-bus system when Whenever the bus master requires printed output, it transfers the task to microprocessor C. Mi-
placed at a logic 1 or the resident local bus when placed at a logic 0. croprocessor C then accesses the shared memory and captures the data to be printed and stores it
in its own local memory. Data are then printed from the local memory, freeing the bus master to
General 8289 Operation. As the pin descriptions demonstrate, the 8289 can be operated in three perform other tasks. This allows the system to execute a program with the bus master, transfer
basic modes: (1) I/O peripheral bus mode, (2) resident bus mode, and (3) single-bus mode. See data through the communications interface with microprocessor B, and print information on the
Table 13-2 for the connections required to operate the 8289 in these modes. In the I/O peripheral printer with microprocessor C. These tasks all execute simultaneously. There is no limit to the
bus mode, all devices on the local bus are treated as I/O, including memory, and are accessed by I/I number of microprocessors connected to a system or the number of tasks performed simultane-
instructions. All memory references access the shared bus and all I/O access the resident local bus. ously using this technique. The only limit is that introduced by the system design and the de-
The resident bus mode allows memory and I/O accesses on both the local and shared buses. Fi-
nally, the single-bus mode interfaces a microprocessor to a shared-bus, but the microprocessor has
no local memory or local I/O. In many systems, one microprocessor is set up as the shared-bus
Priority Logic Using the 8289
master (single-bus mode) to control the shared-bus and become the shared-bus master. The shared- In applications that use the 8289, there is always more than one microprocessor connected 10 a
bus master controls the system through shared memory and I/O. Additional microprocessors are shared bus. Because only one can access the shared bus at a time, some method of resolving pri-
connected to the shared bus as resident or I/O peripheral bus masters. These additional bus masters ority must be employed. Priority prevents more than one microprocessor from accessing the bus
usually perform independent tasks that are reported to the shared-bus master through the shared bus. at a time. There are two methods for resolving priority with the 8289 bus arbiter: the daisy-chain
(serial) scheme and the parallel-priority scheme.
System Illustrating Single-bus and Resident-bus Connections. Single-bus operation interfaces a
microprocessor to a shared bus that contains both I/O and memory resources that are shared by Daisy-Chain Priority. The daisy-chain priority scheme connects the BPRO output to the BPRN
other microprocessors. Figure 13-17 illustrates three 8088 microprocessors, each connected to a input of the next-lower priority 8289 and is the least expensive to implement. Figure 13-18 il-
shared bus. Two of the three microprocessors operate in the resident-bus mode, while the third lustrates the daisy-chain scheme for connecting several 8289s in a system. Because the BPRN
operates in the single-bus mode. Microprocessor A, in Figure 13-17, operates in the single-bus input of the higher priority 8289 is grounded, it gets an immediate acknowledgment whenever its
mode and has no local bus. This microprocessor accesses only the shared memory and I/O space. microprocessor requests access to the shared bus. The BPRO output is a logic 0 if the 8289 and
Microprocessor A is often referred to as the system bus master because it is responsible for co- its microprocessor are inactive, and a logic 1 if the 8289 and its microprocessor are actively
ordinating the main memory and I/O tasks. The remaining two microprocessors (B and C) are using the shared bus. If no requests are active, all BPRN inputs will see a logic 0. As soon as the
connected in the resident-bus mode, which allows them access to both the shared bus and their highest-priority 8289s receives a bus acknowledgment, its BPRO output goes high, blocking all
own local buses. These resident-bus microprocessors are used to perform tasks that are indepen- lower-priority 8289s from accessing the shared bus. If more than one 8289 receives an acknowl-
dent from the system bus master. In fact, the only time that the system bus master is interrupted edgment, more than one 8289 will function at the same time. This scheme is seldom used be-
cause two microprocessors can access the shared bus at a time. For this reason, Intel
from performing its tasks are when one of the two resident-bus microprocessors needs to transfer
recommends that this scheme be limited to no more than three 8289s in a system that uses a bus
data between itself and the shared bus. This connection allows all three microprocessors to per-
clock of 10 MHz or less. With this frequency bus clock, no conflict occurs and only one micro-
form tasks simultaneously, yet data can be shared between microprocessors when needed.
processor accesses the shared bus at a time. If more arbiters are connected, Intel suggests that the
In Figure 13-17, the bus master (A) allows the user to operate with a video terminal that priority be resolved using the parallel scheme.
allows the execution of programs and generally controls the system. Microprocessor B handles
all telephone communications and passes this information to the shared memory in blocks. This Parallel Priority
means that microprocessor B waits for each character to be transmitted or received and controls
the protocol used for the transfers. For example, suppose that a IK byte-block of data are trans- Figure 13-19 illustrates a parallel-priority scheme in which four 8289 bus arbiters are connected
mitted across the telephone interface and this occurs at the rate of 100 characters per second. with a parallel circuit. Here, a 74LS148, eight-input priority encoder is used to resolve priority
conflicts in parallel. In this example, only four of the inputs are used to resolve priority for the
four 8289s. The four unused encoder inputs are pulled up to a logic 1 to disable these unneeded
TABLE 13-2 8289 modes inputs to the encoder. Note that this circuit can be expanded to provide priority for up to eight
of operation. Mode Pin Connections 8289s with their microprocessors.
Single bus IOB = 1 and RESB = 0 The circuit in Figure 13-19 functions as follows. If all 8289 arbiters are idle (no requests
Resident bus JOB = 1 and RESB = 1 for the shared bus through the SYSB/RESB input), all BREQ outputs are high and the outputs of
I/O bus JOB = 0 and RESB = 0 the 74LS148 are logic Is (A and B are both 1). This means that the highest-priority 8289 will
I/O bus and resident bus IOB = 0 and RESB = 1 gain access to the shared bus if it is requested by its microprocessor. On the other hand, if a lower
priority request is made, the BREQ output becomes a logic 0. This causes the priority encoder to
520 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 521
Fl G U R E 13-17 (continued)
FIGURE 13-18 Daisy-chain
8289 priority resolver.
,A A ,„, — ^ CBRQ
BUSY CBRQ BUSY CBRQ BUSY CBRQ
8289 8289 8289
BPRN BPRO BPRN BPRO BPRN BPRO
FIGURE 13-17 Three 8088 microprocessors that share a common bus system. Microprocessor A is the bus
master in control of the shared memory and CRT terminal. Microprocessor B is a bus slave controlling its local
telephone interface and memory. Microprocessor C is also a slave that controls a printer, disk memory system,
and local memory.
bus mode. Because two microprocessors exist, one can print data while the other is used to
place a logic 0 on the corresponding BPRN input pin of the 8289, allowing access to the shared process new information in the interim.
bus. For example, if the rightmost 8289 places a logic 0 on its BREQ output pin, the priority en- In this interface, the slave microprocessor transfers data to the printer from its local memory
coder will have a zero on input 3. This causes the 74LS148 to generate a 00 on its output pins. without intervention from the system bus master. Data are transferred to the local memory of the
The 00 causes the 74LS138 to activate the BPRN input of the rightmost 8289, giving it access to slave microprocessor whenever it accesses the shared memory for additional data.
the shared bus. This also locks out any other requests because the BUSY signal becomes a logic Single-mode Bus-master Interface. Figure 13-21 illustrates the 8088 bus master, operated in
0. If simultaneous requests occur, they are automatically prioritized by the 74LS148, preventing single mode, interfaced to the shared bus. The shared bus master has access to every memory lo-
conflicts no matter how many 8289s are connected in a system. For this reason, this priority cation and I/O device on the shared bus. The BCLK signal is generated by an 8284A clock gen-
scheme is desirable. erator used as a 10-MHz oscillator.
The 8289 arbiter is operated with no I/O bus, no resident bus, and ANYRQST pulled high
Print Spooler and Interface so that the shared bus can be accessed for all memory and I/O transfers. This system uses the
Figure 13-20 shows the block diagram of a printer interface and spooler (print queue), which is daisy-chain priority scheme, which means that the BREQ signal is not connected. This interface
controlled by an 8088 microprocessor. Here, two microprocessors are placed in a system with allows the slave microprocessor to access shared memory whenever necessary and thus prevents
one (the system bus master) operated in single-bus mode and a second operated in the resident- the slave microprocessor from locking the bus for too long.
522 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 523
FIGURE 13-19 Parallel-
priority resolver for the 8289.
3 A A 3
C C 1
Priority 4 0
5 Ei 5 o
-4 — r
Eg 7 0
FIGURE 13-20 Block dia-
gram of two 8088s used to
control a printer interface and
AA bus AN e
VV interface Vv d
FIGURE 13-21 An 8088 connected for the single-bus mode of operation.
Resident-bUS Operation Of the Slave 8088. Figure 13-22 illustrates the slave 8088 microprocessor
that functions as a print spooler. This microprocessor is connected as a resident-bus master. This il-
lustration depicts the resident-local-bus interface as well as the shared-bus interface.
In addition to the normal bus signals, this circuit also provides the shared bus with a 2.5 Whenever the slave 8088 microprocessor accesses memory above location 7FFFFH, it
MHz PCLK signal for any I/O device. The RDY input is shown, in case system memory and I/O places a logic 1 on the SYS/RESB input to the 8289 and the CEN pin of the shared-bus master's
require wait states. 8288. This requests access to the shared bus through the 8289 bus arbiter. If the address is below
524 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 525
526 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 527
FIGURE 13-23 Memory Memory map Memory map FIGURE 13-24 Resident BUSY flip-flop
maps for the print spooler. FFFFF local bus for the print spooler.
(a) Shared-bus master, and
(b) bus-slave memory map. Shared
2K x 8
A16 ——— c A 1111111111111
0 (: OE CE
Resident A17 ———— C B 1
————— *- DS
A 19 ——— c
(b) E3 3 —— | 74LS244
80000H, the SYS/RESB pin on the 8289 is grounded and a logic 1 is placed on the CEN pin of
the local bus 8288. This requests access to the resident-local bus for control of the printer and Printer
resident-local bus memory. Notice that no attempt is made to access the shared-bus I/O because ——
——— , data
the purpose of the slave 8088 is to access the printer interface on its local bus as local I/O.
Figure 13-23 shows the memory maps of both the slave 8088 local memory and the shared
memory and the local memory of the 8088 bus master. The bus master has access to all of the
shared memory, while the slave can only access locations 80000H-FFFFFH. Transfers to the
print spooler are made through the upper half of the shared memory.
The resident-local bus in this system contains EPROM, DRAM, and a printer interface.
The EPROM contains the program that controls the slave 8088, the DRAM contains the data for ACK —— —— » Q D 1
the printer, and the printer interface controls the printer. Figure 13-24 illustrates these three de-
vices on the resident-local bus of the slave 8088 microprocessor.
The decoder in this illustration selects EPROM for locations OOOOOH-OFFFFH, the printer r- "> )
for locations 10000H-1FFFFH, and the DRAM for locations 20000H-7FFFFH. This allows the D°7
r A0 Of
spooler to hold up to 384K bytes of data (see Figure 13-25). If the printer can produce 1,000 •
lines per minute (high-speed printer), then this represents about three minutes of printing and Do N
about 50—75 printed pages of data. If the system is expanded with a fixed memory system, the WR
capacity of the spooler can become almost boundless because of the huge capacity of a modern
fixed-disk memory system. For simplicity's sake, this is not added to this example. SEL3
The printer is interfaced to the slave microprocessor through a 74LS244 that is operated as SEL5
a strobed-output interrupting device. Whenever the printer completes printing a character, as sig-
naled by the ACK signal, an interrupt is generated, causing the slave microprocessor to retrieve
data from the print queue for the printer. This process continues until the queue is empty, when
the slave microprocessor disables interrupt requests until new information is placed in the queue FIGURE 13-25 8088 resi- Memory map
for printing. dent local bus memory map.
Print Spooler Software, The software for the print spooler is fairly straightforward. The entire
software listing is provided in sections so that a study can be made of initialization, data transfer,
and interrupt-controlled printer service procedures. The only software not illustrated is that - 384K Bytes
which are required to program and initialize the system. When the system is initialized, the input
and output pointers of the queue are both set up with address 20000H. This condition (equal
pointers) indicates that the queue is empty. The segment portion of the pointers contains 2000H
and the offset portion contains OOOOH. 20000
Example 13-5 lists the software that transfers data into the print spooler from the shared Printer
bus. In this software, the bus master loads a block of shared memory with printer data, called a
print buffer (BUFFER beginning at location 80002H). Then it signals the slave 8088 that data 00000
528 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 529
are available through a flip-flop, which acts as an indicator to the slave. This flag flip-flop is set 0014 E8 OOOD ;fill queue
by the master whenever printer data are available and cleared by the slave after the slave has re- 0017 FB STI
moved the data from the shared memory. One additional piece of information is also placed in 0018 E6 00 OUT 0,AL ;clear FLAG
the shared memory for the slave — the length of the block of data. Location 80000H holds a 001A EB E4 JMP TRANS
word that indicates the length of the printed block of data. The maximum size of the buffer is 001C TRANS ENDP
; Data used with FILL
EXAMPLE 13-5 001C 0000 IN_PS DW •p ;input pointer
001E 0000 IN_PO •p
A procedure found in the master system una i_ ueaua the
0020 0000 OUT_PS DW •p
FLAG to determine if the slave is busy. If the slave
is not busy, data are transferred to the print buffer 0022 0000 OUT_PO DW •p ;output pointer
and the FLAG is set to indicate that data are available
for printing. ;Procedure that fills the printer queue.
Calling parameters: 0024 FILL PROC NEAR
DS:SI = address of printer data 0024 FC CLD ;clear direction
CX = number of bytes to print 0025 2E: Al 001C R MOV AX,CS:IN_PS
0029 8E CO MOV ES,AX
0000 LOAD PROC FAR USES ES 002B 2E: 8B 3E 001E R MOV DI,CS:IN_PO ;load input address
. REPEAT ;test FLAG 0030 E8 0014 CALL TESTF ;test for full queue
0001 E4 00 IN AL,0 .UNTIL IZERO? ;while full
.UNTIL AL==0 0035 A4 MOVSB ;store byte
0036 E8 0024 CALL INCP ;increment pointer
0007 BF 0002 MOV DI , 2 ; off set of buffer 0039 8C CO MOV AX,ES
OOOA B8 8000 MOV AX,8000H ; segment of buffer & count 003B 2E: A3 001C R MOV CS:IN_PS,AX
OOOD 8E CO MOV ES,AX 003F 2E: 89 3E 001E R MOV CS:IN_PO,DI ; save input pointer
OOOF 26: 89 OE 0000 MOV ES:,CX ; save count .UNTILCXZ
0014 F3/ A4 REP MOVSB ; save data to buffer 0046 C3 RET
0016 BO FF MOV AL,OFFH 0047 FILL ENDP
0018 E6 00 OUT 0,AL ; set FLAG
RET 0047 TESTF PROC NEAR USES DI DS
001C LOAD ENDP 0047 E8 0011 CALL INCP ; increment pointer
004C 8C D8 MOV AX, DS
004E 2E: 3B 06 0020 R CMP AX,CS:OUT_PS
Once the slave notices a logic 1 in the flag flip-flop, it begins transferring data from the 0053 75 05 JNE TESTF1
shared memory into its own local memory. The data are stored in the local memory organized as 0055 2E: 3B 3E 0022 R CMP DI,CS:OUT_PO
a FIFO (first in, first out), or queue. In this example, the size of the queue is 384K bytes. Ex- 005A TESTF1:
ample 13-6 lists the software used by the slave to load the queue from the shared memory buffer.
In this software, the slave tests the flag flip-flop to see whether the master has filled the buffer in 005D TESTF ENDP
the shared memory. If the buffer is filled, the slave microprocessor transfers its contents form the
005D INCP PROC
shared memory into its queue. Once the transfer is complete, the slave clears the flag flip-flop so
that the master may begin filling the buffer with additional printer data. 005D 47 INC DI
.IF DI == 0
0062 8C CO MOV AX,ES
EXAMPLE 13-6 0064 05 1000 ADD AX,1000H
;A procedure found in the slave system that tests the .IF AX == 8000H
;FLAG to determine if data are available for printing. 006C B8 2000 MOV AX,2000H
;If data are available, data are transferred into the .ENDIF
;queue for the printer. 006F 8E CO MOV ES,AX
0000 TRANS PROC FAR 0071 C3 RET
. REPEAT ;test FLAG 0072 ENDP
0000 E4 00 IN AL , 0
0002 A8 01 TEST AL,1
.UNTIL AL = = 0 ;if not finished Example 13-7 lists the software that prints data from the queue. This software is interrupt
driven, and therefore runs as a background program virtually hidden from the software listed in Ex-
0008 B8 8000 MOV AX,8000H ; segment of buffer & count ample 13-6, except for the interrupt enable instruction. Whenever the printer interface, through a
OOOB 8E D8 MOV DS , AX
MOV CX,DS:  ;get count flip-flop, indicates that it is ready to accept additional data, an interrupt occurs calling this interrupt
OOOD 8B OE 0000
0011 BE 0002 • MOV SI, 2 ; address buffer service procedure. The procedure extracts data from the queue and sends them to the printer.
CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O
13-4 DISK MEMORY SYSTEMS 531
The latest optical disk technology is called DVD (digital versatile disk). This section of the
chapter provides an introduction to disk memory systems so that they may be used with com-
0072 PRINT PROC FAR USES AX BP DS DI ES
puter systems. It also provides details of their operation.
.IF ZERO? ;if empty Floppy Disk Memory
007C 8B EC MOV BP,SP /interrupt off
007E 8B 46 OC MOV AX, [BP+12] The most common and the most basic form of disk memory is the floppy, or flexible disk. This
0081 80 E4 FD AND
MOV [BP+12] ,AX magnetic recording media is available in three sizes: the 8" standard, 5l/4" mini-floppy, and the
0084 89 46 OC
.ELSE 3l/2" micro-floppy. Today, the 8" standard version has all but disappeared, giving way to the
0089 B8 1000 MOV AX, 1000H mini- and micro-floppy disks. The 8" disk is too large and difficult to handle and stockpile. To
008C 8E CO
solve this problem, industry developed the 5V4" mini-floppy disk. Today, the micro-floppy disk
008E 8A 05 MOV
0090 26: A2 0000 MOV ES:,AL ; print data has just about replaced the mini-floppy in newer systems because of its reduced size, ease of
0094 E8 001E CALL INCO storage, and durability. Even so, a few systems are still marketed with both the mini- and micro-
. ENDIF floppy disk drives.
All disks have several things in common. They are all organized so that data are stored in
PRINT ENDP tracks. A track is a concentric ring of data that is stored on a surface of a disk. Figure 12-36 il-
lustrates the surface of a 5lk" mini-floppy disk, showing a track that is divided into sectors. A
sector is a common subdivision of a track that is designed to hold a reasonable amount of data.
In many systems, a sector holds either 512 or 1024 bytes of data. The size of a sector can vary
009D TESTE PROC from 128 bytes to the length of one entire track.
2E: Al 0020 R MOV AX , CS : OUT_PS Notice in Figure 13-26 that there is a hole through the disk that is labeled an index hole.
OOA1 8E D8 MOV DS , AX The index hole is designed so that the electronic system that reads the disk can find the begin-
00 A3 2E: 8B 3E 0022 R MOV DI , CS : OUT_PO ning of a track and its first sector (00). Tracks are numbered from track 00, the outermost track,
OOA8 2E: 3B 06 001C R CMP AX,CS:IN_PS
75 05 JNE TESTE1 in increasing value toward the center or innermost track. Sectors are often numbered from sector
OOAF 2E: 3B 3E 001E R CMP DI , CS : IN_PO 00 on the outermost track, to whatever value is required to reach the innermost track and its last
OOB4 TESTE1: sector.
OOB4 C3 RET
7776 51/4 " Mini-floppy Disk. Today, the 5V4" floppy is probably the most popular disk size used
OOB5 TESTE ENDP
with older microcomputer systems. Figure 13-27 illustrates this mini-floppy disk. The floppy
OOB5 INCO PROC NEAR
OOB5 47 INC DI FIGURE 13-26 The format Sector
.IF DI == 0 of a 51/4" floppy disk.
OOBA 8C D8 MOV AX,DS
ODBC 05 1000 ADD AX,1000H
.IF AX == 8000H
OOC4 B8 2000 MOV AX,2000H
OOC7 8E D8 MOV DS , AX
OOC9 2E: A3 0020 R MOV CS : OUT_PS , AX
OOCD 2E: 89 3E 0022 R MOV CS : OUT_PO , DI
OOD2 C3 RET
OOD3 INCO ENDP
13-4 DISK MEMORY SYSTEMS
Disk memory is used to store long-term data. Many types of disk storage systems are available
today and they use magnetic media, except the optical disk memory that stores data on a plastic
disk. Optical disk memory is either a CD-ROM (compact disk/read only memory) that is read,
but never written, or a WORM (write once/read mostly) that is read most of the time, but can be
written once by a laser beam. Also becoming available is optical disk memory that can be read
and written many times, but there is still a limitation on the number of write operations allowed.
532 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-4 DISK MEMORY SYSTEMS
FIGURE 13-27 The 5 /4"
mini-floppy disk. Data
Write protect notch _
FIGURE 13-28 The non-return to zero (NRZ) recording technique
separate erase head would be required. The mechanical alignment of a separate erase head and a
separate read/write head is virtually impossible. The magnetic flux density of the NRZ signal is
so intense that it completely saturates (magnetizes) the surface of the disk, erasing all prior data.
Head slot It also ensures that information will not be affected by noise because the amplitude of the mag-
netic field contains no information. The information is stored in the placement of the changes of
the magnetic field.
Data are stored in the form of MFM (modified frequency modulation) in modern floppy
disk systems. The MFM recording technique stores data in the form illustrated in Figure 13-29.
disk is rotated at 300 RPM inside its semi-rigid plastic jacket. The head mechanism in a floppy Notice that each bit time is 2.0 jis wide on a double-density disk. This means that data are
disk drive makes physical contact with the surface of the disk, which eventually causes wear and recorded at the rate of 500,000 bits per second. Each 2.0 jus bit time is divided into two parts: one
damage to the disk. part is designated to hold a clock pulse and the other holds a data pulse. If a clock pulse is present,
Today, most mini-floppy disks are double-sided. This means that data are written on both it is 1 (is wide, as is a data pulse. Clock and data pulses are never present at the same time in one
the top and bottom surfaces of the disk. A set of tracks called a cylinder consists of one top and bit period. (Note that high-density disk drives halve these times so that a bit time is 1.0 }is and a
one bottom track. Cylinder 00, for example, consists of the outermost top and bottom tracks. clock or data pulse is 0.5 u,s wide. This also doubles the transfer rate to 1 million bits per second.)
Floppy disk data are stored in the double-density format, which uses a recording technique If a data pulse is present, the bit time represents a logic 1. If no data or no clock is present,
called MFM (modified frequency modulation) to store the information. Double-density, double- the bit time represents a logic 0. If a clock pulse is present with no data pulse, the bit time also
sided (DSDD) disks are normally organized with 40 tracks of data on each side of the disk. A represents a logic 0. The rules followed when data are stored using MFM are as follows:
double-density disk track is typically divided into nine sectors, with each sector containing 512 1. A data pulse is always stored for a logic 1.
bytes of information. This means that the total capacity of a double-density, double-sided disk is 2. No data and no clock is stored for the first logic 0 in a string of logic Os.
40 tracks per side x 2 sides x 9 sectors per track x 512 bytes per sector, or 368,640 (360K) bytes 3. The second and subsequent logic Os in a row contain a clock pulse, but no data pulse.
Earlier disk memory systems used single-density and FM (frequency modulation) to store The reason that a clock is inserted as the second and subsequent zero in a row is to main-
information in 40 tracks on one or two sides of the disk. Each of the eight or nine sectors on the tain synchronization as data are read from the disk. The electronics used to recapture the data
single-density disk stored 256 bytes of data. This meant that a single-density disk stored 90K from the disk drive use a phase-locked loop to generate a clock and a data window. The phase-
locked loop needs a clock or data to maintain synchronized operation.
bytes of data per side. A single-density, double-sided disk stored 180K bytes of data.
Also common today are high-density (HD) mini-floppy disks. A high-density mini-floppy The 31/2" Micro-floppy disk. Another very popular disk size is the 3V2" micro-floppy disk. Re-
disk contains 80 tracks of information per side, with eight sectors per track. Each sector contains cently, this size floppy disk has begun to sell very well and is the dominant floppy disk size. The
1024 bytes of information. This gives the 5l/4" high-density, mini-floppy disk a total capacity of micro-floppy disk is a much improved version of the mini-floppy disk described earlier. Figure
80 tracks per side x 2 sides x 15 sectors per track x 512 bytes per sector, or 1,228,800 (approxi- 13-30 illustrates the 3lh" micro-floppy disk.
mately 1.2 M) bytes of information.
The magnetic recording technique used to store data on the surface of the disk is called
FIGURE 13-29 Modified
non-return to zero (NRZ) recording. With NRZ recording, magnetic flux placed on the surface
frequency modulation (MFM)
of the disk never returns to zero. Figure 13-28 illustrates the information stored in a portion of a used with disk memory.
track. It also shows how the magnetic field encodes the data. Note that arrows are used in this il-
lustration to show the polarity of the magnetic field stored on the surface of the disk.
The main reason that this form of magnetic encoding was chosen is that it automatically Ci D C : D C | D C | D
erases old information when new information is recorded. If another technique were used, a
CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O
13-4 DISK MEMORY SYSTEMS 535
on a high-density, double-sided micro-floppy disk is 80 tracks per side x 2 sides x 18 sectors per
Write protect .
i track x 512 bytes per sector, or 1,474,560 (1.44M) bytes of information.
Recently, a new size SVz" floppy disk has been introduced, the EHD (extended high den-
sity) floppy disk. This new format stores 2.88M bytes of data on a single floppy disk. At this
time, this format is expensive and will take time to become common. Also available is the flop-
tical disk, which stores data magnetically by using an optical tracking system. The floptical disk
stores 21M bytes of data.
„ Drive hub
Hard Disk Memory
Larger disk memory is available in the form of the hard disk drive. The hard disk drive is often
called a fixed disk because it is not removable like the floppy disk. A hard disk is also often called
a rigid disk. The term Winchester drive is also used to describe a hard disk drive, but less com-
o . Head slot
monly today. Hard disk memory has a much larger capacity than the floppy disk memory. Hard
disk memory is available in sizes exceeding 1G byte of data. Common, low-cost (less than $0.30
per megabyte) sizes are presently 3.2G bytes to 12G bytes.
There are several differences between the floppy disk and the hard disk memory. The hard
disk memory uses a flying head to store and read data from the surface of the disk. A flying head,
which is very small and light, does not touch the surface of the disk. It flies above the surface on
a film of air that is carried with the surface of the disk as it spins. The hard disk typically spins at
Disk designers noticed several shortcomings of the mini-floppy, which is a scaled down 3000 to 10,000 R.P.M, which is more than 10 times faster than the floppy disk. This higher rota-
version of the 8" standard floppy, soon after it was released. Probably one of the biggest prob- tional speed allows the head to fly (just as an airplane flies) just over the top of the surface of the
lems with the mini-floppy is that it is packaged in a semi-rigid plastic cover that bends easily. disk. This is an important feature because there is no wear on the hard disk's surface, as there is
The micro-floppy is packaged in a rigid plastic jacket that will not bend easily. This provides a with the floppy disk.
much greater degree of protection to the disk inside the jacket. Problems can arise because of flying heads. One problem is a head crash. If the power is
Another problem with the mini-floppy is the head slot that continually exposes the surface abruptly interrupted or the hard disk drive is jarred, the head can crash onto the disk surface,
of the disk to contaminants. This problem is also corrected on the micro-floppy because it is con- which can damage the disk surface or the head. To help prevent crashes, some drive manufac-
structed with a spring-loaded sliding head door. The head door remains closed until the disk is turers have included a system that automatically parks the head when power is interrupted. This
inserted into the drive. Once inside the drive, the drive mechanism slides open the door, ex- type of disk drive has auto-parking heads. When the heads are parked, they are moved to a safe
posing the surface of the disk to the read/write heads. This provides a great deal of protection to landing zone (unused track) when the power is disconnected. Some drives are not auto-parking;
they usually require a program that parks the heads on the innermost track before power is dis-
the surface of the micro-floppy disk.
Yet another improvement is the sliding plastic write-protection mechanism on the micro- connected. The innermost track is a safe landing area because it is the very last track filled by the
floppy disk. On the mini-floppy disk, a piece of tape was placed over a notch on the side of the disk drive. Parking is the responsibility of the operator in this type of disk drive.
jacket to prevent writing. This plastic tape easily became dislodged inside disk drives, causing Another difference between a floppy disk drive and a hard disk drive is the number of heads
problems. On the micro-floppy, an integrated plastic slide has replaced the tape write-protection and disk surfaces. A floppy disk drive has two heads, one for the upper surface and one for the
mechanism. To write-protect (prevent writing) the micro-floppy disk, the plastic slide is moved lower surface. The hard disk drive may have up to eight disk surfaces (four platters), with up to
to open the hole though the disk jacket. This allows light to strike a sensor that inhibits writing. two heads per surface. Each time that a new cylinder is obtained by moving the head assembly, 16
Still another improvement is the replacement of the index hole with a different drive mech- new tracks are available under the heads. See Figure 13-31, which illustrates a hard disk system.
anism. The drive mechanism on the mini-floppy allows the disk drive to grab the disk at any Heads are moved from track to track by using either a stepper motor or a voice coil. The
point. This requires an index hole so that the electronics can find the beginning of a track. The stepper motor is slow and noisy, while the voice coil mechanism is quiet and quick. Moving the
index hole is another trouble spot because it collects dirt and dust. The micro-floppy has a drive head assembly requires one step per cylinder in a system that uses a stepper motor to position the
mechanism that is keyed so that it only fits one way inside the disk drive. The index hole is no heads. In a system that uses a voice coil, the heads can be moved many cylinders with one
longer required because of this keyed drive mechanism. Because of the sliding head mechanism sweeping motion. This makes the disk drive faster when seeking new cylinders.
and the fact that no index hole exists, the micro-floppy disk has no place to catch dust or dirt. Another advantage of the voice coil system is that a servo mechanism can monitor the am-
Two types of micro-floppy disks are widely available: the double-sided, double-density plitude of the signal as it comes from the read head and make slight adjustments in the position
(DSDD) and the high-density (HD). The double-sided, double-density micro-floppy disk has 80 of the heads. This is not possible with a stepper motor, which relies strictly on mechanics to po-
tracks per side, with each track containing nine sectors. Each sector contains 512 bytes of infor- sition the head. Stepper-motor-type head positioning mechanisms can often become misaligned
mation. This allows 80 tracks per side x 2 sides x 9 sectors x 512 bytes per sector, or 737,280 with use, while the voice coil mechanism corrects for any misalignment.
(720K) bytes of data to be stored on a double-density, double-sided floppy disk. Hard disk drives often store information in sectors that are 512 bytes long. Data are ad-
The high-density, double-sided micro-floppy disk stores even more information. The high- dressed in clusters of eight or more sectors, which contain 4096 bytes (or more) on most hard
density version has 80 tracks per side, but the number of sectors is doubled to 18 per track. This disk drives. Hard disk drives use either MEM or RLL to store information. MEM is described
format still uses 512 bytes per sector, as did the double-density format. The total number of bytes with floppy disk drives. Run-length limited (RLL) is described here.
CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-4 DISK MEMORY SYSTEMS 537
FIGURE 13-31 A hard disk Actuator arm Data RLL
drive that uses four heads per Disk platters 101001011 =010001001001001000
platter. Head [J
Drive spindle -
010 001 001 001 001 000
A typical older MFM hard disk drive uses 18 sectors per track so that 18 K bytes of data are
FIGURE 13-32 A comparison of MFM with RLL using data 101001011.
stored per track. If a hard disk drive has a capacity of 40M bytes, it contains approximately 2280
tracks. If the disk drive has two heads, this means that it contains 1140 cylinders; if it contains
four heads, then it has 570 cylinders. These specifications vary from disk drive to disk drive. a data pulse for MFM. A 40M-byte MFM disk can hold 60M bytes of RLL-encoded data. Be-
RLL Storage. Run-length limited (RLL) disk drives use a different method for encoding the sides holding more information, the RLL drive can be written and read at a higher rate.
data than MFM. The term RLL means that the run of zeros (zeros in a row) is limited. A common All hard disk drives use either MFM or RLL encoding. There are a number of disk drive
RLL encoding scheme in use today is RLL 2,7. This means that the run of zeros is always be- interfaces in use today. The oldest is the ST-506 interface, which uses either MFM or RLL data.
A disk system using this interface is also called either MFM or RLL disk system. Newer stan-
tween two and seven. Table 13-3 illustrates the coding used with standard RLL.
Data are first encoded by using Table 13-3 before being sent to the drive electronics for dards are also found in use today, which include ESDI, SCSI, and IDE. All of these newer stan-
storage on the disk surface. Because of this encoding technique, it is possible to achieve a 50 per- dards use RLL, even though they normally do not call attention to it. The main difference is the
cent increase in data storage on a disk drive when compared to MFM. The main difference is that interface between the computer and the disk drive. The IDE system is becoming the standard
hard disk memory interface.
the RLL drive often contains 27 tracks instead of the 18 found on the MFM drive. (Some RLL
The enhanced small disk interface (ESDI) system, which has disappeared, is capable of
drives also use 35 sectors per track.)
In most cases, RLL encoding requires no change to the drive electronics or surface of the transferring data between itself and the computer at rates approaching 10 M bytes per second. An
ST-506 interface can approach a transfer rate of 860 K bytes per second.
disk. The only difference is a slight decrease in the pulse width using RLL, which may require
slightly finer oxide particles on the surface of the disk. Disk manufacturers test the surface of the The small computer system interface (SCSI) system is also in use because it allows up to
disk and grade the disk drive as either an MFM-certified or an RLL-certified drive. Other than seven different disk or other interfaces to be connected to the computer through same interface
grading, there is no difference in the construction of the disk drive or the magnetic material that controller. SCSI is found in some PC-type computers and also in the Apple Macintosh system.
An improved version, SCSI-II, has started to appear in some systems. In the future, this interface
coats the surface of the disks.
may be replaced with IDE in most applications.
Figure 13-32 shows a comparison of MFM data and RLL data. Notice that the amount of
time (space) required to store RLL data is reduced when compared to MFM. Here a 101001011 The newest system is integrated drive electronics (IDE), which incorporates the disk
is coded in both MFM and RLL so that these two standards can be compared. Notice that the controller in the disk drive and attaches the disk drive to the host system through a small inter-
width of the RLL signal has been reduced so that three pulses fit in the same space as a clock and face cable. This allows many disk drives to be connected to a system without worrying about bus
conflicts or controller conflicts. IDE drives are found in newer IBM PS-2 systems and many
clones. Even Apple computer systems are starting to be found with IDE drives in place of the
TABLE 13-3 Standard RLL SCSI drives found in older Apple computers. The IDE interface is also capable of driving other
2,7 coding. Input Data Stream RLL Output I/O devices besides the hard disk. This interface also usually contains at least a 32K-byte cache
memory for disk data. The cache speeds disk transfers. Common access times for an IDE drive
000 000100 are often less than 10 ms, where the access time for a floppy-disk is about 200 ms.
0010 00100100 Optical Disk Memory
11 1000 Optical disk memory (see Figure 13-33) is commonly available in two forms: the CD-ROM
011 001000 (compact disk/read only memory) and the WORM (write once/read mostly). The CD-ROM is
the lowest cost optical disk, but it suffers from lack of speed. Access times for a CD-ROM are
538 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-5 VIDEO DISPLAYS 539
available in late 1996 or early 1997. The DVD functions exactly as the CD-ROM except that the
bit density is much higher. The CD-ROM stores 660 M bytes of data, while the current-genre
DVD stores 4.7G bytes or 8.5G bytes, depending on the current standard. The future standard,
which requires a new drive, stores up to 17G bytes of data.
13-5 VIDEO DISPLAYS
Modern video displays are OEM (original equipment manufacturer) devices that are usually
purchased and incorporated into a system. Today, there are many different types of video dis-
plays available. Of the types available, either color or monochrome versions are found.
Monochrome versions usually display information using amber, green, or paper-white dis-
plays. The paper-white display is becoming extremely popular for many applications. The most
common of these applications are desk-top publishing and computer-aided drafting (CAD).
The color displays are more diverse. Color display systems are available that accept in-
formation as a composite video signal, much as your home television, as TTL voltage level sig-
nals (0 or 5 V), and as analog signals (0-0.7 V). Composite video displays are disappearing
because the available resolution is too low. Today, many applications require high-resolution
graphics that cannot be displayed on a composite display such as a home television receiver.
Early composite video displays were found with Commodore 64, Apple 2, and similar computer
FIGURE 13-33 The optical CD-ROM memory system.
Figure 13-34 illustrates the signal sent to a composite video display. This signal is composed
of several parts that are required for this type of display. The signals illustrated represent the
typically 300 ms or longer, about the same as a floppy disk. (Note that slower CD-ROM devices signals sent to a color composite-video monitor. Notice that these signals include not only
are on the market and should be avoided.) Hard disk magnetic memory can have access times as video, but also include sync pulses, sync pedestals, and a color burst. Notice that no audio
little as 11 ms. A CD-ROM stores 660M bytes of data, or a combination of data and musical pas- signal is illustrated because one often does not exist. Rather than include audio with the com-
sages. As systems develop and become more visually active, the use of the CD-ROM drive will posite video signal, audio is developed in the computer and output from a speaker inside the
become even more common. computer cabinet. It can also be developed by a sound system and output in stereo to external
The WORM drive sees far more commercial application than the CD-ROM. The problem speakers. The major disadvantages of the composite video display are the resolution and color
is that its application is very specialized due to the nature of the WORM. Because data may be limitations. Composite video signals were designed to emulate television video signals so that
written only once, the main application is in the banking industry, insurance industry, and other a home television receiver could function as a video monitor.
massive data storing organizations. The WORM is normally used to form an audit trail of trans- Most modern video systems use direct video signals that are generated with separate sync
actions that are spooled onto the WORM and retrieved only during an audit. You might call the signals. In a direct video system, video information is passed to the monitor through a cable that
WORM an archiving device. uses separate lines for video and also synchronization pulses. Recall that these signals were com-
Many WORM and read/write optical disk memory systems are interfaced to the micro- bined in a composite video signal.
processor by using the SCSI or ESDI interface standards used with hard disk memory. The dif- A monochrome (one color) monitor uses one wire for video, one for horizontal sync, and
ference is that the current optical disk drives are no faster than the most floppy drives. Some CD- one for vertical sync. Often, these are the only signal wires found. A color video monitor uses three
ROM drives are interfaced to the microprocessor through proprietary interfaces that are not com- video signals. One signal represents red, another green, arid the third blue. These monitors are
patible with other disk drives. often called RGB monitors for the video primary colors of light: red (R), green (G), and blue (B).
The main advantage of the optical disk is its durability. Because a solid state laser beam is
used to read the data from the disk, and the focus point is below a protective plastic coating, the
surface of the disk may contain small scratches and dirt particles and still be read correctly. This
The TTL RGB Monitor
feature allows less care of the optical disk than a comparable floppy disk. About the only way to The RGB monitor is available as either an analog or TTL monitor. The RGB monitor uses TTL
destroy data on an optical disk is to break it or deeply scar it. level signals (0 or 5 V) as video inputs and a fourth line called intensity to allow a change in in-
The read/write CD-ROM drive is here and its cost is dropping rapidly. In the near future, we tensity. The RGB video TTL display can display a total of 16 different colors. The TTL RGB
should start seeing the read/write CD-ROM replacing floppy disk drives. The main advantage is monitor is used in the CGA (color graphics adapter) system found in older computer systems.
the vast storage available on the read/write CD-ROM. Soon, the format will change so that many Table 13-4 lists these 16 colors and also the TTL signals present to generate them. Eight
G bytes of data will be available. The new versatile read/write CD-ROM, called a DVD, became of the 16 colors are generated at high intensity and the other eight at low intensity. The three
540 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-5 VIDEO DISPLAYS 541
Color burst FIGURE 13-35 The 9-pin DB9 Pin Function
connector found on a TTL
Sync pulse monitor. 1 Ground
. Black level 2 Ground
3 Red video
4 Green video
5 Blue video
7 Normal video
8 Horizontal retrace
Sync pedestal -
9 Vertical retrace
The Analog RGB Monitor
In order to display more than 16 colors, an analog video display is required. These are often
FIGURE 13-34 The composite video signal. called analog RGB monitors. Analog RGB monitors still have three video input signals, but
don't have the intensity input. Because the video signals are analog signals instead of two-level
TTL signals, they are any voltage level between 0.0 V and 0.7 V, which allows an infinite
video colors are red, green, and blue. These are primary colors of light. The secondary colors are number of colors to be displayed. This is because an infinite number of voltage levels between
cyan, magenta, and yellow. Cyan is a combination of blue and green video signals, and is blue- the minimum and maximum could be generated. In practice, a finite number of levels are gener-
green in color. Magenta is a combination of blue and red video signals, and is a purple color. ated. This is usually either 256K, 16M, or 24M colors, depending on the standard.
Yellow (high-intensity) and brown (low-intensity) are both a combination of red and green video Figure 13-36 illustrates the connector used for an analog RGB or analog monochrome
signals. If additional colors are desired, TTL video is not normally used. A scheme was devel- monitor. Notice that the connector has 15 pins and supports both RGB and monochrome analog
oped by using low and medium color TTL video signals, which provided 32 colors, but it proved displays. The way data are displayed on an analog RGB monitor depends upon the interface
of little application and never found widespread use in the field. standard used with the monitor. Pin 9 is a key, which means that no hole exists on the female
Figure 13-35 illustrates the connector most often found on the TTL RGB monitor or a connector for this pin.
TTL monochrome monitor. The connector illustrated is a 9-pin connector. Two of the connec- Most analog displays use a digital-to-analog converter (DAC) to generate each color
tions are used for ground, three for video, two for synchronization or retrace signals, and one video voltage. A common standard uses a 6-bit DAC for each video signal to generate 64 dif-
for intensity. Notice that pin 7 is labeled normal video. This is the pin used on a monochrome ferent voltage levels between 0 V and 0.7 V. There are 64 different red video levels, 64 different
monitor for the luminance or brightness signal. Monochrome TTL monitors use the same 9-pin green video levels, and 64 different blue video levels. This allows 64 x 64 x 64, or 262,144
connector as RGB TTL monitors. (256K) colors to be displayed.
TABLE 13-4 16 colors Color
Intensity Red Green Blue
found in the CGA display.
1 Red video
0 0 0 0 Black 2 Green video (monochrome video)
0 0 0 1 Blue 3 Blue video
0 0 1 0 Green 4 Ground
0 0 1 1 Cyan
0 1 0 0 Red
6 Red ground
0 1 0 1 Magenta
7 Green ground (monochrome ground)
0 1 1 0 Brown
0 1 1 1 White 8 Blue ground
1 0 0 0 Gray 9 Blocked as a key
1 0 0 1 Bright Blue 10 Ground
1 0 1 0 Bright Green 11 Color detect (ground on a color monitor)
1 0 1 1 Bright Cyan 12 Monochrome detect (ground on a monochrome monitor)
1 1 0 0 Bright Red 13 Horizontal retrace
1 1 0 1 Bright Magenta 14 Vertical retrace
1 1 1 0 Yellow 15 Ground
1 1 1 1 Bright White
FIGURE 13-36 The 15-pin connector found on an analog monitor.
542 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O
13-5 VIDEO DISPLAYS 543
Other arrangements are possible, but the speed of the DAC is critical. Most modern dis-
plays require an operating conversion time of 25 ns to 40 ns maximum. When converter tech- / 4 DO QO 1Y1 1A1
nology advances, additional resolution at a reasonable price will become available. If 7-bit D2
converters are used for generating video, 128 x 128 x 128, or 2,097,152 (2M) colors are dis-
played. In this system, a 21-bit color code is needed so that a 7-bit code is applied to each DAC.
8-bit converters also find applications and allow 256 x 256 x 256, or 16,777,216 (16M) colors. OC 1G
Figure 13-37 illustrates the video generation circuit employed in many common video stan- 74F374 74F244
dards such as the short-lived EGA (enhanced graphics adapter) and VGA (variable graphics
array), as used with an IBM PC. This circuit is used to generate VGA video. Notice that each DO
Q1 /-& 1Y1
color is generated with an 18-bit digital code. Six of the 18 bits are used to generate each video D2 Q2
R 1Y3 1A3
color voltage when applied to the inputs of a 6-bit DAC.
A high-speed palette SRAM (access time of less than 40 ns) is used to store 256 different 4 D6
D7 Q7 19__ ^3
18-bit codes that represent 256 different hues. This 18-bit code is applied to the digital-to- -^ OC
analog converters. The address input to the SRAM selects one of the 256 colors stored as 18-bit 74F374 74F244
binary codes. This system allows 256 colors out of a possible 256K colors to be displayed at U3 U6
one time. In order to select any of 256 colors, an 8-bit code that is stored in the computer's
video display RAM is used to specify the color of a picture element. If more colors are used in
a system, the code must be wider. For example, a system that displays 1024 colors out of 256K [X5-D5 n
n 1Y1 1A1
1 Y4 1 A4
2Y1 2A1 13 |
•^i D5 Q5 Tfi — ^^
colors requires a 10-bit code to address the SRAM that contains 1024 locations, each con- D7 Q7 19_ 2Y4 2A4 JH
taining an 18-bit color code. Some newer systems use a larger palette SRAM to store up to 64K >CLK
of different color codes. 74F374 74F244
The Apple Macintosh-IIci uses a 24-bit binary code to specify each color in its color video
adapter. Each DAC is eight bits wide. This means that each converter can generate 256 different 2
U10 ^± D1 Q1
video voltage levels. There are 256 x 256 x 256, or 16,777,216 different possible colors. As with 6
AO DO _/ D2 Q2
5 A1 9
the IBM VGA standard, only 256 colors are displayed at a time. The SRAM in the Apple inter- D2 Q2
D2 D4 Q4
face is 256 x 24 instead of 256 x 18.
D3 Q3 D3 _/
^± D5 Q5
D7 Q7 _ia_
Whenever a color is placed on the video display, provided that RTC is a logic 0, the system —/ 1
-J2- D7 Q7 19
~~y . —— 1 ^>CLK
sends the 8-bit code that represents a color to the DO-D7 connections. The PAL 16R8 then gen- D8
erates a clock pulse for U10, which latches the color code. After 40 ns (one 25 MHz clock), the y
PAL generates a clock pulse for the DAC latches (U7, U8, and U9). This amount of time is re- U12
WE D13 ^ DO QO
11 O1 D14 ID1 Q1
quired for the palette SRAM to look up the 18-bit contents of the memory location selected by 12 O2 D-f- D15
g D2 Q2 9
13 O3 D16 D3 Q3 12 DAC
U10. Once the color code (18-bit) is latched into U7-U9, the three DACs convert it to three 6 D4 Q4
video voltages for the monitor. This process is repeated for each 40 ns-wide picture element
(pixel) that is displayed. The pixel is 40 ns wide because a 25 MHz clock is used in this system.
Palette RAM dfc
Higher resolution is attainable if a higher clock frequency is used with the system.
If the color codes (18-bits) stored in the SRAM must be changed, this is always accom-
plished during retrace when RTC is a logic 1. This prevents any video noise from disrupting the X^ 4 5
__ 7 6
image displayed on the monitor. N^_ 8 9
x^_ 13 12 DAC
In order to change a color, the systems uses the SO, SI, and S2 inputs of the PAL to select 14 15
Ul, U2, U3, or U10. First, the address of the color to be changed is sent to latch U10, which ad- dfc D6 06
D7 Q7 i
dresses a location in the palette SRAM. Next, each new video color is loaded into Ul, U2, and ——— TT°
U3. Finally, the PAL generates a write pulse for the WE input to the SRAM to write the new - — 74F374
color code into the palette SRAM.
Retrace occurs 70.1 times per second in the vertical direction and 31,500 times per second FIGURE 13-37 Generation of VGA video signals.
in the horizontal direction for a 640 x 480 display. During retrace, the video signal voltage sent
to the display must be 0 V, which causes black to be displayed during the retrace. Retrace itself
is used to move the electron beam to the upper left-hand corner for vertical retrace and to the left The resolution of the display, for example 640 x 480, determines the amount of memory
margin of the screen for horizontal retrace. required for the video interface card. If this resolution is used with a 256-color display (eight bits
The circuit illustrated causes U4-U6 buffers to be enabled so that they apply 00000 each to per pixel), then 640 x 480 bytes of memory (307,200) are required to store all of the pixels for
the display. Higher-resolution displays are possible, but, as you can imagine, even more memory
the DAC latch for retrace. The DAC latches capture this code and generate 0 V for each video
color signal to blank the screen. By definition, 0 V is considered to be the black level for video is required. A 640 x 480 display has 480 video raster lines and 640 pixels per line. A raster line
is the horizontal line of video information that is displayed on the monitor. A pixel is the smallest
and 0.7 V is considered to be the full intensity on a video color signal.
subdivision of this horizontal line.
544 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-6 SUMMARY 545
FIGURE 13-38 A video rate must be greater than or equal to 50 Hz, or flickering will occur. The vertical rate must not be
screen illustrating the raster higher than about 75 Hz or problems with the vertical deflection coil may occur. The electron
lines and retrace. beam in a monitor is positioned by an electrical magnetic field generated by coils in a yoke that
surrounds the neck of the picture tube. Because the magnetic field is generated by coils, the fre-
quency of the signal applied to the coil is limited.
The horizontal scanning rate is also limited by the physical design of the coils in the yoke.
Video line '
Because of this, it is normal to find the frequency applied to the horizontal coils within a narrow
Horizontal retrace ' range. This is usually 30,000 Hz-37,000 Hz or 15,000 Hz-17,000 Hz. Some newer monitors are
called multisync monitors because the deflection coil is taped so that it can be driven with dif-
ferent deflection frequencies. Sometimes, both the vertical and horizontal coils are both taped for
different vertical and horizontal scanning rates.
High-resolution displays use either interlaced or non-interlaced scanning. The non-interlaced
scanning system is used in all standards except the highest. In the interlaced system, the video image
is displayed by drawing half the image first with all of the odd scanning lines, then the other half is
drawn using the even scanning lines. Obviously, this system is more complex and is only more effi-
cient because the scanning frequencies are reduced by 50 percent in an interlaced system. For ex-
ample, a video system that uses 60 Hz for the vertical scanning frequency and 15,720 Hz for the
horizontal frequency generates 262 (15,720/60) lines of video at the rate of 60 full frames per
second. If the horizontal frequency is changed slightly to 15,750 Hz, 262.5 (15,750/60) lines are
generated, so two full sweeps are required to draw one complete picture of 525 video lines. Notice
how just a slight change in horizontal frequency doubled the number of raster lines.
Figure 13-38 illustrates the video display, showing the video lines and retrace. The slant of
each video line in this illustration is greatly exaggerated, as is the spacing between lines. This il-
lustration shows retrace in both the vertical and horizontal directions. In the case of a VGA dis-
play, as described, the vertical retrace occurs exactly 70.1 times per second and the horizontal
retrace occurs exactly 31,500 times per second. (The Apple Macintosh-IIci uses a vertical rate of 13-6 SUMMARY
66.67 Hz and a horizontal rate of 35 KHz to generate a 640 x 480 color display.)
In order to generate 640 pixels across one line, it takes 40 ns x 640, or 25.6 jis. A hori- 1. The HOLD input is used to request a DMA action, and the HLDA output signals that the
zontal time of 31,500 Hz allows a horizontal line time of 1/31,500, or 31.746 jis. The difference hold is in effect. When a logic 1 is placed on the HOLD input, the microprocessor (1) stops
between these two times is the retrace time allowed to the monitor. (The Apple Macintosh Ilci executing the program; (2) places its address, data, and control bus at their high-impedance
has a horizontal line time of 28.57 |0,s.) state; and (3) signals that the hold is in effect by placing a logic 1 on the HLDA pin.
Because the vertical retrace repetition rate is 70.1 Hz, the number of lines generated is de- 2. A DMA read operation transfers data from a memory location to an external I/O device. A
termined by dividing the vertical time into the horizontal time. In the case of a VGA display (a DMA write operation transfers data from an I/O device into the memory. Also available is a
640 x 400 display), this is 449.358 lines. Only 400 of these lines are used to display information; memory-to-memory transfer that allows data to be transferred between two memory loca-
the rest are lost during the retrace. Because 49.358 lines are lost during the retrace, the retrace tions by using DMA techniques.
time is 49.358 x 31.766 (is, or 1568 [is. It is during this relatively large amount of time that the 3. The 8237 direct memory access (DMA) controller is a four-channel device that can be ex-
color palette SRAM is changed or the display memory system is updated for a new video dis- panded to include an additional channel of DMA.
play. In the Apple Macintosh Ilci computer (640 x 480), the number of lines generated is 525 4. Disk memory comes in the form of floppy disk storage that is found as either the 5lfa" mini-
lines Of the total number of lines, 45 are lost during vertical retrace. floppy disk or 3!/2" micro-floppy disk. Both disks are found as double-sided, double-density
Other display resolutions are 800 x 600 and 1024 x 768. The 800 x 600 SVGA (super
(DSDD), or as high-density (HD) storage devices. The DSDD 5V4" disk stores 360 K bytes
VGA) display is ideal for a 14" color monitor, while the 1024 x 768 EVGA or XVGA (extended
of data and the HD 5V4" disk stores 1.2 M bytes of data. The DSDD 3V2" disk stores 720 K
VGA) is ideal for a 21" or 25" monitor used in CAD systems. These resolutions sound like just
bytes of data and the HD 3l/2" disk stores 1.44 M bytes of data.
another set of numbers, but realize that an average home television receiver has a resolution ap-
proximately 400 x 300. The high-resolution display available on computer systems is much 5. Floppy disk memory data are stored using NRZ (non-return to zero) recording. This method
clearer than that available as home television. A resolution of 1024 x 768 approaches that found saturates the disk with one polarity of magnetic energy for a logic 1 and the opposite polarity
in 35 mm film. The only disadvantage of the video display on a computer screen is the number for a logic 0. In either case, the magnetic field never returns to 0. This technique eliminates
of colors displayed at a time, but as time passes, this will surely improve. Additional colors allow the need for a separate erase head.
the image to appear more realistically because of subtle shadings that are required for a true 6. Data are recorded on disks by using either modified frequency modulation (MFM) or run-
high-quality, life-like image. length limited (RLL) encoding schemes. The MFM scheme records a data pulse for a logic
If a display system operates with a 60 Hz vertical time and a 15,600 Hz horizontal time, the 1, no data or clock for the first logic 0 of a string of zeros, and a clock pulse for the second
number of lines generated is 15,600/60, or 260 lines. The number of usable lines in this system is and subsequent logic 0 in a string of zeros. The RLL scheme encodes data so that 50 percent
most likely 240, where 20 are lost during vertical retrace. It is clear that the number of scanning more information can be packed onto the same disk area. Most modern disk memory sys-
lines is adjustable by changing the vertical and horizontal scanning rates. The vertical scanning tems use the RLL encoding scheme.
546 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O
13-7 QUESTIONS AND PROBLEMS
7. Video monitors are either TTL or analog. The TTL monitor uses two discrete voltage levels 27. What is a WORM?
of 0 V and 5.0 V. The analog monitor uses an infinite number of voltage levels between 28. What is a CD-ROM?
0.0 V and 0.7 V. The analog monitor can display an infinite number of video levels, while
29. What is the difference between a TTL monitor and an analog monitor?
the TTL monitor is limited to two video levels. 30. What are the three primary colors of light?
8. The color TTL monitor displays 16 different colors. This is accomplished through three 31. What are the three secondary colors of light?
video signals (red, green, and blue) and an intensity input. The analog color monitor can dis- 32. What is a pixel?
play an infinite number of colors through its three video inputs. In practice, the most
33. A video display with a resolution of 800 x 600 contains __ _ lines of video informa-
common form of color analog display system (VGA) can display 256K different colors.
tion, with each line divided into _____ pixels.
9. The video standards found today include VGA (640 x 480), SVGA (800 x 600), and EVGA
34. Explain how a TTL RGB monitor can display 16 different colors.
or XVGA (1024 x 768). In all three cases, the video information can be 256 colors out of a
35. Explain how an analog RGB monitor can display an infinite number of colors.
total possible 256K colors.
36. If an analog RGB video system uses 7-bit DACs, it can generate ______ different colors.
37. Why does standard VGA allow only 256 different colors out of 256K colors to be displayed
at one time?
38. If a video system uses a vertical frequency of 60 Hz and a horizontal frequency of 32,400
13-7 QUESTIONS AND PROBLEMS Hz, how many raster lines are generated?
1. Which microprocessor pins are used to request and acknowledge a DMA transfer?
2. Explain what happens whenever a logic 1 is placed on the HOLD input pin.
3. A DMA read transfers data from _______ to _______.
4. A DMA write transfers data from _______ to _______.
5. The DMA controller selects the memory location used for a DMA transfer through what bus
6. The DMA controller selects the I/O device used during a DMA transfer by which pin?
7. What is a memory-to-memory DMA transfer?
8. Describe the effect on the microprocessor and DMA controller when the HOLD and HLDA
pins are at their logic 1 levels.
9. Describe the effect on the microprocessor and DMA controller when the HOLD and HLDA
pins are at their logic 0 levels.
10. The 8237 DMA controller is a _____ channel DMA controller.
11. If the 8237 DMA controller is decoded at I/O ports 2000H-200FH, what ports are used to
program channel 1 ?
12. Which 8237 DMA controller register is programmed to initialize the controller?
13. How many bytes can be transferred by the 8237 DMA controller?
14. Write a sequence of instructions that transfer data from memory location 21000H-210FFH
to 20000H-200FFH by using channel 2 of the 8237 DMA controller. You must initialize the
8237 and use the latch described in Section 12-1 to hold A19-A16.
15. Write a sequence of instructions that transfer data from memory to an external I/O device by
using channel 3 of the 8237. The memory area to be transferred is at location 20000H-
16. The 5 l /4" disk is known as a _______- floppy disk.
17. The 3V4" disk is known as a - floppy disk.
18. Data are recorded in concentric rings on the surface of a disk known as a ________.
19. A track is divided into sections of data called _______.
20. On a double-sided disk, the upper and lower tracks together are called a _______.
21. Why is NRZ recording used on a disk memory system?
22. Draw the timing diagram generated to write a 1001010000 using MFM encoding.
23. Draw the timing diagram generated to write a 1001010000 using RLL encoding.
24. What is a flying head?
25. Why must the heads on a hard disk be parked?
26. What is the difference between a voice coil head position mechanism and a stepper motor
head positioning mechanism?